From patchwork Thu Aug 24 06:02:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suneel Garapati X-Patchwork-Id: 805242 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="D53bpXji"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xdDH606rrz9s65 for ; Thu, 24 Aug 2017 16:02:57 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A7B38C21DF0; Thu, 24 Aug 2017 06:02:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AAA31C21C97; Thu, 24 Aug 2017 06:02:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DC658C21C97; Thu, 24 Aug 2017 06:02:48 +0000 (UTC) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by lists.denx.de (Postfix) with ESMTPS id 457D2C21C62 for ; Thu, 24 Aug 2017 06:02:48 +0000 (UTC) Received: by mail-pg0-f66.google.com with SMTP id b3so2473859pga.2 for ; Wed, 23 Aug 2017 23:02:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=q7fzc3LRC3XbpMKVWLRVz8UG5D6/YohKazvrMRSB8JU=; b=D53bpXji93busoTrhyddevLuZs0Oa/gH1EXANmnXIS4jMm+IH6Y6m2MYtDZCpcWD1o FCz73v109a2O7rCJyOfnJbMDmp/skZnRuucrUZ4EFIHJIVdlQjGOMVCNjmgQgVce75OL nY+29zbTQmuzdEAjD4s9i/q/sEiMOV5Hge+ApjNRWIZjIJCNIBvSNNOhy/OL9LerNxMY 2uyu/gHRiuEyE07TO/U68IayAXBUUaqMN7dueSHGf5Xzod3ucKBxdPV1HPDCieGhnXSz kJcDd8/Ozm21h0yh/I1uBi+HZnhLaBNGjCQbNXYtn1emiJjmdG5/QMob+U6jlW5db3fQ NcVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=q7fzc3LRC3XbpMKVWLRVz8UG5D6/YohKazvrMRSB8JU=; b=ZQs8yH8bR6ZOrza9v0EYBFU94xLZ0QHZ9pu9dUWrgQLDDhgcGHyZdrlcxBX6scgK+y x4HQO6CLlCdhcAYnEJ8GAZ2bSIVynPguq7cojSujVwavrOfXoiQ7WOfVqquHuQjxO99f xpQb5FvjB2PttKZeqcMfO4ATQp3fmeiV3FdMRgdkPinOKKcDBeA+xF9eq5rH/mwV0nLi yrLWyPO8iUT+GLr2VuLf2sT6Lcf1ClpL+BYcAAj7imRHESuPQz/alaL+OBjVO4jfHgcI owDmxCjmJ4dGsAqigJM9o0TIfHFJjj1PdoZT1/kS7Ef4n2R/2gqy5DAdsF53MK+q+MuH M5Ow== X-Gm-Message-State: AHYfb5jEeeOLYXqVp4uY9zb5oDtFoemxol5vLRw3uDw2YD2gQXbCqHOt 1BzHv6MfwiLjtQ== X-Received: by 10.98.31.195 with SMTP id l64mr5483632pfj.128.1503554566460; Wed, 23 Aug 2017 23:02:46 -0700 (PDT) Received: from suneel.hsd1.ca.comcast.net ([2601:646:8e00:e521:f83b:d54f:852e:f5ca]) by smtp.gmail.com with ESMTPSA id l2sm4910014pgc.27.2017.08.23.23.02.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Aug 2017 23:02:46 -0700 (PDT) From: Suneel Garapati To: Bin Meng Date: Wed, 23 Aug 2017 23:02:41 -0700 Message-Id: <1503554561-18257-1-git-send-email-suneelglinux@gmail.com> X-Mailer: git-send-email 2.7.4 Cc: u-boot@lists.denx.de, Michal Simek Subject: [U-Boot] [U-BOOT][PATCH] drivers: ahci: write upper 32 bits for clb and fis registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If 64-bit capability is supported, commandlistbase and fis base should be split as lower32 and upper32. upper32 should be written to PORT_(LST/FIS)_ADDR_HI. Signed-off-by: Suneel Garapati Reviewed-by: Bin Meng --- drivers/ata/ahci.c | 11 +++++++++-- include/ahci.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 5e4df19..df50c82 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -607,10 +607,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, + if (uc_priv->cap & HOST_CAP_64) + writel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)), + port_mmio + PORT_LST_ADDR_HI); + writel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)), port_mmio + PORT_LST_ADDR); - writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + if (uc_priv->cap & HOST_CAP_64) + writel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)), + port_mmio + PORT_FIS_ADDR_HI); + writel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)), + port_mmio + PORT_FIS_ADDR); #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); diff --git a/include/ahci.h b/include/ahci.h index 33171b7..80e7f13 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -40,6 +40,7 @@ #define HOST_RESET (1 << 0) /* reset controller; self-clear */ #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ +#define HOST_CAP_64 (1 << 31) /* 64bit addressing capability */ /* Registers for each SATA port */ #define PORT_LST_ADDR 0x00 /* command list DMA addr */