From patchwork Thu May 25 10:05:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keerthy X-Patchwork-Id: 766916 X-Patchwork-Delegate: jh80.chung@samsung.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wYPzJ327nz9s7B for ; Thu, 25 May 2017 20:05:48 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="GkZfwBOm"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 19D7AC21D17; Thu, 25 May 2017 10:05:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 83970C21C6C; Thu, 25 May 2017 10:05:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BC73FC21C6C; Thu, 25 May 2017 10:05:40 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id F394FC21C25 for ; Thu, 25 May 2017 10:05:39 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4PA5bJn002330; Thu, 25 May 2017 05:05:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495706737; bh=hbC426hwxTdlSHfuOOVb+Ai0IyyDNGNHJ2BL0DEnWGU=; h=From:To:CC:Subject:Date; b=GkZfwBOm9j0MRTO0/cFOFCsQalOTj5qdiDyChP+SDJX3Nt4zx1LlNx38EpuxJJVBs l18ELBMCJrsvxQzd0rdks23rtgzA9jr2t0yQCadQT6ncgNGcQATTjLJWNRAWKB5SWV 8auzjpfVKy/wPPnKZaW+s/AyWJuG38XGZqMJs9H8= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4PA5bkr025327; Thu, 25 May 2017 05:05:37 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Thu, 25 May 2017 05:05:37 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4PA5Zot020946; Thu, 25 May 2017 05:05:35 -0500 From: Keerthy To: , Date: Thu, 25 May 2017 15:35:25 +0530 Message-ID: <1495706725-5988-1-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Cc: t-kristo@ti.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH] power: pmic: tps65218: Fix tps65218_voltage_update function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently while setting the vsel value for dcdc1 and dcdc2 the driver is wrongly masking the entire 8 bits in the process clearing PFM (bit7) field as well. Hence describe an appropriate mask for vsel field and modify only those bits in the vsel mask. Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf Signed-off-by: Keerthy Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC") Reviewed-by: Tom Rini --- drivers/power/pmic/pmic_tps65218.c | 2 +- include/power/tps65218.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index f32fa40..c5e768a 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -101,7 +101,7 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) /* set voltage level */ if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, - TPS65218_MASK_ALL_BITS)) + TPS65218_DCDC_VSEL_MASK)) return 1; /* set GO bit to initiate voltage transition */ diff --git a/include/power/tps65218.h b/include/power/tps65218.h index 4d68faa..e3538e2 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -56,6 +56,8 @@ enum { #define TPS65218_MASK_ALL_BITS 0xFF +#define TPS65218_DCDC_VSEL_MASK 0x3F + #define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a #define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 #define TPS65218_DCDC_VOLT_SEL_1200MV 0x23