From patchwork Sat May 6 21:13:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 759378 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wL1zV1Jq7z9s8D for ; Sun, 7 May 2017 07:26:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E2C6FC21C93; Sat, 6 May 2017 21:22:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 32BA4C21C6B; Sat, 6 May 2017 21:18:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4077EC21C85; Sat, 6 May 2017 21:16:42 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id F3323C21C5D for ; Sat, 6 May 2017 21:16:38 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id b23so4919996pfc.0 for ; Sat, 06 May 2017 14:16:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s58ok9VV2kQbu322wlHscGli0B2RmxWqWwtJNifrcOI=; b=VFYuz4+Q76PV4km3v0LuEo3JBFzkWLAtRndB3Ec7WiMnP9THQl+MueGhJdzqQy6KcS sHYkNUdx/e7Fy8qDrit4skKNERcfAltXrK8Ylt7838AejfVF4xNcZG1Mb5cVCDqUPHrB K/GhqpGLDci5tAmGdSwLWPoTqR1f0AZT1JX+h+JlGc1pKyu30mB1JJ0lHSRoic3qsjZm nP/jV2J5y5KdvYxWhdf2yeorJx2+81wm8A1IBfrrg9UwlxOjhwF5I6jCuGlMvmKZfPUd r2SPgUQSJsoeAFuUfQ80GcKseYnFwv5+9SIgWYFJ3v4HvY7r5fSEWbkQIE2HSuBAWEOw PdrQ== X-Gm-Message-State: AN3rC/4CTzLtMKwHwqJI0A+Xpj+r2jnaIvaxBDk3akyG20HsGwD+xa5V W72mgtZ6UcOosg== X-Received: by 10.84.230.229 with SMTP id e92mr74034480plk.2.1494105397687; Sat, 06 May 2017 14:16:37 -0700 (PDT) Received: from localhost.localdomain ([117.247.27.104]) by smtp.gmail.com with ESMTPSA id m19sm3945078pgk.25.2017.05.06.14.16.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 06 May 2017 14:16:36 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Sun, 7 May 2017 02:43:07 +0530 Message-Id: <1494105195-25729-9-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494105195-25729-1-git-send-email-jagan@openedev.com> References: <1494105195-25729-1-git-send-email-jagan@openedev.com> Cc: u-boot@lists.denx.de, Matteo Lisi Subject: [U-Boot] [PATCH 08/16] icorem6: Use proper iomux_ddr_regs drive strength values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Usually the drive strength values for DQ and SDL are 0x30 and 0x28 respectively, update them accordingly. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6/icorem6.c | 58 ++++++++++++++++----------------- board/engicam/icorem6_rqs/icorem6_rqs.c | 58 ++++++++++++++++----------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 8c62f0e..8aaac40 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -369,29 +369,29 @@ int board_fit_config_name_match(const char *name) /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, + .dram_sdqs0 = 0x30, + .dram_sdqs1 = 0x30, + .dram_sdqs2 = 0x30, + .dram_sdqs3 = 0x30, + .dram_sdqs4 = 0x30, + .dram_sdqs5 = 0x30, + .dram_sdqs6 = 0x30, + .dram_sdqs7 = 0x30, + .dram_dqm0 = 0x30, + .dram_dqm1 = 0x30, + .dram_dqm2 = 0x30, + .dram_dqm3 = 0x30, + .dram_dqm4 = 0x30, + .dram_dqm5 = 0x30, + .dram_dqm6 = 0x30, + .dram_dqm7 = 0x30, .dram_cas = 0x30, .dram_ras = 0x30, .dram_sdclk_0 = 0x30, .dram_sdclk_1 = 0x30, .dram_reset = 0x30, - .dram_sdcke0 = 0x3000, - .dram_sdcke1 = 0x3000, + .dram_sdcke0 = 0x30, + .dram_sdcke1 = 0x30, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x30, .dram_sdodt1 = 0x30, @@ -417,16 +417,16 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x30, - .dram_sdcke1 = 0x30, + .dram_sdclk_0 = 0x28, + .dram_sdclk_1 = 0x28, + .dram_cas = 0x28, + .dram_ras = 0x28, + .dram_reset = 0x28, + .dram_sdcke0 = 0x28, + .dram_sdcke1 = 0x28, .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, + .dram_sdodt0 = 0x28, + .dram_sdodt1 = 0x28, .dram_sdqs0 = 0x28, .dram_sdqs1 = 0x28, .dram_sdqs2 = 0x28, @@ -450,8 +450,8 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, - .grp_addds = 0x30, - .grp_ctlds = 0x30, + .grp_addds = 0x28, + .grp_ctlds = 0x28, .grp_ddrmode = 0x00020000, .grp_b0ds = 0x28, .grp_b1ds = 0x28, diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index d6ca62d..24093bb 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -240,29 +240,29 @@ int board_fit_config_name_match(const char *name) /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, + .dram_sdqs0 = 0x30, + .dram_sdqs1 = 0x30, + .dram_sdqs2 = 0x30, + .dram_sdqs3 = 0x30, + .dram_sdqs4 = 0x30, + .dram_sdqs5 = 0x30, + .dram_sdqs6 = 0x30, + .dram_sdqs7 = 0x30, + .dram_dqm0 = 0x30, + .dram_dqm1 = 0x30, + .dram_dqm2 = 0x30, + .dram_dqm3 = 0x30, + .dram_dqm4 = 0x30, + .dram_dqm5 = 0x30, + .dram_dqm6 = 0x30, + .dram_dqm7 = 0x30, .dram_cas = 0x30, .dram_ras = 0x30, .dram_sdclk_0 = 0x30, .dram_sdclk_1 = 0x30, .dram_reset = 0x30, - .dram_sdcke0 = 0x3000, - .dram_sdcke1 = 0x3000, + .dram_sdcke0 = 0x30, + .dram_sdcke1 = 0x30, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x30, .dram_sdodt1 = 0x30, @@ -288,16 +288,16 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x30, - .dram_sdcke1 = 0x30, + .dram_sdclk_0 = 0x28, + .dram_sdclk_1 = 0x28, + .dram_cas = 0x28, + .dram_ras = 0x28, + .dram_reset = 0x28, + .dram_sdcke0 = 0x28, + .dram_sdcke1 = 0x28, .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, + .dram_sdodt0 = 0x28, + .dram_sdodt1 = 0x28, .dram_sdqs0 = 0x28, .dram_sdqs1 = 0x28, .dram_sdqs2 = 0x28, @@ -321,8 +321,8 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, - .grp_addds = 0x30, - .grp_ctlds = 0x30, + .grp_addds = 0x28, + .grp_ctlds = 0x28, .grp_ddrmode = 0x00020000, .grp_b0ds = 0x28, .grp_b1ds = 0x28,