From patchwork Sat May 6 21:13:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 759375 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wL1xV1Q8gz9s7y for ; Sun, 7 May 2017 07:24:45 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id AF316C21C94; Sat, 6 May 2017 21:21:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EFDF0C21C5D; Sat, 6 May 2017 21:18:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 58169C21C77; Sat, 6 May 2017 21:16:39 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id D6155C21C44 for ; Sat, 6 May 2017 21:16:35 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id b23so4919915pfc.0 for ; Sat, 06 May 2017 14:16:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=obyxuazV7pMRXeKu1/jmPzZnSCILJyCKlpTXpzS4U18=; b=jGCgNWTthLMDH3ky8DdUNqBh7YowTqZY3qH1wQTkHnwOBXZWWwTynioCtq93FaCkj9 EIxETgP+N5iL4KY6b9MLka4r9KR4HKA1KWHpYcXnIUOfgvkkficGyZG5nAvUxmaQb54e BrwKfiqrYkkCxV4MAwzIkhZcllGgRziLA4QTeMxPeqZ/zEJXO48qlRXPab6fokOd5NTo 2tpeJrtwG5ZXek45Q6IbazVlnajEpFnXZPnp0hsKghfol56fC3Bdpel06c0To6tZiaqW iWo1AjArNWwi2IXc01PyvoVdpQRm2qys4Rhkeca2gfqK4XA4FfEa1WKFDbbPc4o69zLW m3Rw== X-Gm-Message-State: AN3rC/7P+KFLmNDPB8LUThZOKoU3MMuqaB8/DYFMKbNZUyvEXLYGcWGh ikd9hHnMTEL6+dZu X-Received: by 10.98.110.195 with SMTP id j186mr24493552pfc.25.1494105394562; Sat, 06 May 2017 14:16:34 -0700 (PDT) Received: from localhost.localdomain ([117.247.27.104]) by smtp.gmail.com with ESMTPSA id m19sm3945078pgk.25.2017.05.06.14.16.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 06 May 2017 14:16:33 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Sun, 7 May 2017 02:43:06 +0530 Message-Id: <1494105195-25729-8-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494105195-25729-1-git-send-email-jagan@openedev.com> References: <1494105195-25729-1-git-send-email-jagan@openedev.com> Cc: u-boot@lists.denx.de, Matteo Lisi Subject: [U-Boot] [PATCH 07/16] engicam: Move uart mux init to SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Since, u-boot handle fdt through uart so move the UART code to SPL instead make it to global area. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/geam6ul/geam6ul.c | 27 ++++++++++----------------- board/engicam/icorem6/icorem6.c | 27 ++++++++++----------------- board/engicam/icorem6_rqs/icorem6_rqs.c | 27 ++++++++++----------------- board/engicam/isiotmx6ul/isiotmx6ul.c | 27 ++++++++++----------------- 4 files changed, 40 insertions(+), 68 deletions(-) diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c index eb0e533..c3d92ac 100644 --- a/board/engicam/geam6ul/geam6ul.c +++ b/board/engicam/geam6ul/geam6ul.c @@ -22,22 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - - return 0; -} - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) @@ -173,6 +157,15 @@ int dram_init(void) #include #include +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include @@ -341,7 +334,7 @@ void board_init_f(ulong dummy) ccgr_init(); /* iomux and setup of i2c */ - board_early_init_f(); + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); /* setup GP timer */ timer_init(); diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index c8aaad1..8c62f0e 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -23,15 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) @@ -199,13 +190,6 @@ static void setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ -int board_early_init_f(void) -{ - SETUP_IOMUX_PADS(uart4_pads); - - return 0; -} - #ifdef CONFIG_ENV_IS_IN_MMC static void mmc_late_init(void) { @@ -281,6 +265,15 @@ int dram_init(void) #include #include +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include @@ -617,7 +610,7 @@ void board_init_f(ulong dummy) gpr_init(); /* iomux */ - board_early_init_f(); + SETUP_IOMUX_PADS(uart4_pads); /* setup GP timer */ timer_init(); diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index 2027b28..d6ca62d 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -22,22 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -int board_early_init_f(void) -{ - SETUP_IOMUX_PADS(uart4_pads); - - return 0; -} - int board_init(void) { /* Address of boot parameters */ @@ -110,6 +94,15 @@ int dram_init(void) #include #include +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include @@ -488,7 +481,7 @@ void board_init_f(ulong dummy) gpr_init(); /* iomux */ - board_early_init_f(); + SETUP_IOMUX_PADS(uart4_pads); /* setup GP timer */ timer_init(); diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 5d1c693..008a7ae 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -22,22 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - - return 0; -} - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) @@ -185,6 +169,15 @@ int dram_init(void) #include #include +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include @@ -402,7 +395,7 @@ void board_init_f(ulong dummy) ccgr_init(); /* iomux and setup of i2c */ - board_early_init_f(); + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); /* setup GP timer */ timer_init();