From patchwork Thu May 4 15:11:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 758621 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wJdw75s8Rz9s2P for ; Fri, 5 May 2017 01:18:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 80C45C21C5C; Thu, 4 May 2017 15:17:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 41D8AC21C5F; Thu, 4 May 2017 15:17:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3D574C21C69; Thu, 4 May 2017 15:17:25 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 40D64C21C56 for ; Thu, 4 May 2017 15:17:21 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id i63so2684324pgd.2 for ; Thu, 04 May 2017 08:17:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jzzkekfwuulGNqAebtLDW0G2oQOZfJZ1mpprvzuT188=; b=nasQN9KWPYbvsdfBViohog0xYuxOHh1LThuohBM1LhN1l+zEVKFgSnH6ZoXl7gzE9A Hg71Pg1KQ7CLRxzhsqD9S8IFo8D82+YuKwFEVWwtbq41uV3B9IvbSD1UnyoTciEl6avN ncBHxJijMDtXOcNtcLMPjm5hVHGd0s7q9JQMJZIyIJfCHtGxp4IJklG5+rPqlY7vf043 zj1deDxJoqoIG7p8AIUwloTA+G8aJNIfps6ZSuC+2SlWv82f6to6EQ26blsHnOnZulSJ /WIcBsGo/q9lVPZR2VZ6vdp//RyR9wXyzPa076h6nYDxa3LiKsdz/uY1rEjnS7VCabPv f7TA== X-Gm-Message-State: AN3rC/4t+DpiS99YZYnRdfsn5DQGAjERL4DCT8sEsrcmN8bisWDqtAHW NDdq30mxHxzyivkS X-Received: by 10.98.201.197 with SMTP id l66mr3649696pfk.249.1493911039761; Thu, 04 May 2017 08:17:19 -0700 (PDT) Received: from localhost.localdomain ([59.95.76.120]) by smtp.gmail.com with ESMTPSA id d3sm6803661pgc.37.2017.05.04.08.17.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 May 2017 08:17:18 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Thu, 4 May 2017 20:41:11 +0530 Message-Id: <1493910702-6751-3-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493910702-6751-1-git-send-email-jagan@openedev.com> References: <1493910702-6751-1-git-send-email-jagan@openedev.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v5 02/33] ARM: dts: i.MX6: Add imx6qdl-sabresd.dtsi X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add common minimal dtsi file for i.MX6QDL Sabresd boards, - uart1 - usdhc2 - usdhc3 - usdhc4 Cc: Stefano Babic Cc: Fabio Estevam Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/dts/imx6qdl-sabresd.dtsi | 111 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi new file mode 100644 index 0000000..1846274 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -0,0 +1,111 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +};