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[58.96.121.164]) by smtp.gmail.com with ESMTPSA id 74sm803418pfn.102.2017.04.18.19.07.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Apr 2017 19:07:34 -0700 (PDT) From: James Balean To: U-Boot Mailing List Date: Tue, 18 Apr 2017 21:06:35 -0500 Message-Id: <1492567595-3556-1-git-send-email-james@balean.com.au> X-Mailer: git-send-email 2.7.4 Cc: James Balean Subject: [U-Boot] [PATCH v3] Add 16-bit single register pin controller support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enables the pinctrl-single driver to support 16-bit registers. Only 32-bit registers were supported previously. Reduced width registers are required for some platforms, such as OMAP. Signed-off-by: James Balean Cc: Felix Brack Cc: Simon Glass Reviewed-by: Felix Brack Tested-by: Felix Brack Reviewed-by: Simon Glass --- Changes for v3: - Fixes incorrect v2 submission. - Inline rather than separate read/write function calls. drivers/pinctrl/pinctrl-single.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d2dcec0..f19f779 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -47,27 +47,27 @@ static int single_configure_pins(struct udevice *dev, int n, reg; u32 val; - for (n = 0; n < count; n++) { + for (n = 0; n < count; n++, pins++) { reg = fdt32_to_cpu(pins->reg); if ((reg < 0) || (reg > pdata->offset)) { dev_dbg(dev, " invalid register offset 0x%08x\n", reg); - pins++; continue; } reg += pdata->base; + val = fdt32_to_cpu(pins->val) & pdata->mask; switch (pdata->width) { + case 16: + writew((readw(reg) & ~pdata->mask) | val, reg); + break; case 32: - val = readl(reg) & ~pdata->mask; - val |= fdt32_to_cpu(pins->val) & pdata->mask; - writel(val, reg); - dev_dbg(dev, " reg/val 0x%08x/0x%08x\n", - reg, val); + writel((readl(reg) & ~pdata->mask) | val, reg); break; default: dev_warn(dev, "unsupported register width %i\n", pdata->width); + continue; } - pins++; + dev_dbg(dev, " reg/val 0x%08x/0x%08x\n",reg, val); } return 0; }