From patchwork Mon Apr 3 13:53:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 746463 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vxYg412Hvz9s81 for ; Tue, 4 Apr 2017 00:01:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C4ADCC21C33; Mon, 3 Apr 2017 13:56:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 938D6C21C68; Mon, 3 Apr 2017 13:56:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 60B35C21C82; Mon, 3 Apr 2017 13:56:14 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 08C52C21CB5 for ; Mon, 3 Apr 2017 13:56:10 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id g2so30036258pge.2 for ; Mon, 03 Apr 2017 06:56:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/Hi5/ARwUWOVsKPtMc8lkE/PknyCIlVO+KLHrjwO+zw=; b=q0Np/6JDTuYg2H9uTtzODhDjWymoRagsW7I1YN1GZFGgl7dd4i6hxsfIBhRk8Zi6G2 BUFqUopVKTLqj4Ew6uM4UQj+XyqZnDOcUwgbz76kWd4bNtwqBhkzwCgt/ko5qCbt4PjK EWuEWIff6eIjFGCnXz36vVsgV27beF6cgJhCd89o2X08LKRCtjtnmswPTpB58O4yLUAy 71Cdh33Rpdfx9gQIeFVWJTJ3gN4v+D2lV5O3MUMJJgU3+y1gxx34+tHZZ5anClXMhVwc x4aMglLCs71l8pRsaF/80VB7vzkS1Xs8o/KnuKmesOdyHviYlv72k8N5duurjEWLvnE4 3sMQ== X-Gm-Message-State: AFeK/H0gwstjmmfTDDKzb1x0V5HCRCnqZBqfgtUXeqLEXAfRn09b6kqPfId8bjjXYD8kiw== X-Received: by 10.98.200.19 with SMTP id z19mr17099937pff.223.1491227768675; Mon, 03 Apr 2017 06:56:08 -0700 (PDT) Received: from localhost.localdomain ([117.254.76.151]) by smtp.gmail.com with ESMTPSA id 123sm26271368pgh.21.2017.04.03.06.56.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 06:56:07 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Mon, 3 Apr 2017 19:23:12 +0530 Message-Id: <1491227616-15042-6-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491227616-15042-1-git-send-email-jagan@openedev.com> References: <1491227616-15042-1-git-send-email-jagan@openedev.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 05/29] ARM: i.MX6Q: sabresd: Add initial devicetree support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add initial devicetree support for i.MX6 Quad Sabresd board. The configs item are copied from configs/mx6sabresd_spl_defconfig and added - CONFIG_OF_CONTROL=y - CONFIG_DM_GPIO=y - CONFIG_DM_MMC=y - CONFIG_BLK is not set - CONFIG_DM_MMC_OPS is not set - CONFIG_PINCTRL=y - CONFIG_PINCTRL_IMX6=y Cc: Stefano Babic Cc: Fabio Estevam Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/freescale/mx6sabresd/MAINTAINERS | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 122 +++++++++++++++++++++----------- configs/imx6q_sabresd_defconfig | 58 +++++++++++++++ include/configs/mx6sabresd.h | 4 ++ 4 files changed, 145 insertions(+), 40 deletions(-) create mode 100644 configs/imx6q_sabresd_defconfig diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS index add2314..434548a 100644 --- a/board/freescale/mx6sabresd/MAINTAINERS +++ b/board/freescale/mx6sabresd/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/mx6sabresd.h F: configs/mx6dlsabresd_defconfig F: configs/mx6qsabresd_defconfig F: configs/mx6sabresd_spl_defconfig +F: configs/imx6q_sabresd_defconfig diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 80a7789..db25dad 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -241,7 +241,7 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_OF_CONTROL) struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, {USDHC3_BASE_ADDR}, @@ -276,9 +276,9 @@ int board_mmc_getcd(struct mmc *mmc) return ret; } +#ifndef CONFIG_FSL_ESDHC int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD int ret; int i; @@ -321,46 +321,9 @@ int board_mmc_init(bd_t *bis) } return 0; -#else - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - } - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } #endif +#endif static int ar8031_phy_fixup(struct phy_device *phydev) { @@ -717,6 +680,85 @@ int checkboard(void) #include #include +#ifdef CONFIG_FSL_ESDHC + +#if defined(CONFIG_OF_CONTROL) && !defined(CONFIG_DM_MMC) +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} +#endif + +int board_mmc_init(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/configs/imx6q_sabresd_defconfig b/configs/imx6q_sabresd_defconfig new file mode 100644 index 0000000..c6d4462 --- /dev/null +++ b/configs/imx6q_sabresd_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_MX6SABRESD=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PCI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 598ab9a..9885a5c 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -11,6 +11,10 @@ #ifdef CONFIG_SPL #include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif #endif #define CONFIG_MACH_TYPE 3980