From patchwork Fri Feb 24 10:15:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 732061 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vV6qN2RF3z9s7x for ; Fri, 24 Feb 2017 21:32:16 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E63DB3981; Fri, 24 Feb 2017 11:32:14 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fEAkVkfMbB3A; Fri, 24 Feb 2017 11:32:14 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 57C93B3959; Fri, 24 Feb 2017 11:25:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4130CB38FD for ; Fri, 24 Feb 2017 11:18:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZwB3AMWHdy8w for ; Fri, 24 Feb 2017 11:18:30 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by theia.denx.de (Postfix) with ESMTPS id 28AB2B3905 for ; Fri, 24 Feb 2017 11:16:29 +0100 (CET) Received: by mail-pg0-f68.google.com with SMTP id 5so2638757pgj.0 for ; Fri, 24 Feb 2017 02:16:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p9qi5DfzbPjvsgZKc73da5molIqDU83eorzaiL2BsM4=; b=IblKrnad39/uPE5QnZ8vzsdKcP526Bq+XdmttsLPJILO4daP9hO2taM6kPvHW3Zwth z1bhmZR/jr9qo1zsjKaCHHfj4g0oPcgfUC+4rbnc2ohQ5UgJqkArPIi4yXQfMa8SGWbE Jbvk7G8sb86BgWLDaSAKqddZu7qbJBTJSEP27rvNUnAncwHTYzfT9gLvAMVCUqIC5vjD MRMAVQEaAP7cMocoUyI+WnE+9ESXVg7Fggj8GD8yJcpAxfY2Kv5GdO4NLczdf7+MMFzO qks5sXsS7TRWgEY6tV+b+UboGhHja/HoUevGr+Vw41pG6M5zyQwFC0KVXVleQIhZSCP9 Ct7g== X-Gm-Message-State: AMke39nqOfzeenD0uDbnBbMm4Thp3ZWFWaB+pYx01sQMXsg6+zOY/zRTERasaCbHiBohqQ== X-Received: by 10.84.213.137 with SMTP id g9mr2818522pli.114.1487931388076; Fri, 24 Feb 2017 02:16:28 -0800 (PST) Received: from localhost.localdomain ([106.220.148.189]) by smtp.gmail.com with ESMTPSA id u29sm14350288pfl.17.2017.02.24.02.16.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Feb 2017 02:16:27 -0800 (PST) From: Jagan Teki To: Stefano Babic Date: Fri, 24 Feb 2017 15:45:23 +0530 Message-Id: <1487931326-10199-13-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487931326-10199-1-git-send-email-jagan@openedev.com> References: <1487931326-10199-1-git-send-email-jagan@openedev.com> Cc: u-boot@lists.denx.de, Matteo Lisi Subject: [U-Boot] [PATCH v4 12/15] imx6: icorem6_rqs: Add eMMC boot support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Boot from eMMC: -------------- U-Boot SPL 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21) Trying to boot from MMC2 U-Boot 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21 +0100) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Net: No ethernet found. Hit any key to stop autoboot: 0 Booting from mmc ... switch to partitions #0, OK mmc1(part 0) is current device Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6_rqs/icorem6_rqs.c | 24 ++++++++++++++++++++++-- include/configs/imx6qdl_icore_rqs.h | 2 +- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index e3c520f..175bda5 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -77,8 +77,22 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1, 4}, + {USDHC4_BASE_ADDR, 1, 8}, }; int board_mmc_getcd(struct mmc *mmc) @@ -88,6 +102,7 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC3_BASE_ADDR: + case USDHC4_BASE_ADDR: ret = 1; break; } @@ -102,7 +117,8 @@ int board_mmc_init(bd_t *bis) /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) - * mmc0 USDHC3 + * mmc0 USDHC3 + * mmc1 USDHC4 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { @@ -110,6 +126,10 @@ int board_mmc_init(bd_t *bis) SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index 6f7195d..cd94c5f 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -124,7 +124,7 @@ /* MMC */ #ifdef CONFIG_FSL_USDHC # define CONFIG_SYS_MMC_ENV_DEV 0 -# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_USDHC_NUM 2 # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif