From patchwork Wed Jan 18 09:04:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siva Durga Prasad Paladugu X-Patchwork-Id: 716556 X-Patchwork-Delegate: jh80.chung@samsung.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3v3LyH1NPFz9t1B for ; Wed, 18 Jan 2017 20:19:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="o8elC29P"; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A1E4B3945; Wed, 18 Jan 2017 10:19:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WfpzAVu78dHh; Wed, 18 Jan 2017 10:19:15 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D197B393A; Wed, 18 Jan 2017 10:19:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1651BB3930 for ; Wed, 18 Jan 2017 10:19:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YyuO5wegj2Jw for ; Wed, 18 Jan 2017 10:19:11 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0043.outbound.protection.outlook.com [104.47.36.43]) by theia.denx.de (Postfix) with ESMTPS id 9622CB394A for ; Wed, 18 Jan 2017 10:19:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=7Lsaaxztf/n1zKgYXZiT059z0s7eaCv9VctKhMbHWyo=; b=o8elC29Pal31kiWH8qCB4Qf7NvUO7NtIjCSQ8jTmMmXlGwOO6+NfuQ9/saaJrjBYzxNOZ9w8FXSVEG9IZOIiClILJpJGGjcpz792eRxKaBjmVorMFhNXsDLV7YofZmQ5ViO/6A0mb6QIIOl3jwU0m1b6/UgNmmfKy2Nj69W7jfA= Received: from BY2PR02CA0112.namprd02.prod.outlook.com (10.163.44.166) by DM2PR02MB1388.namprd02.prod.outlook.com (10.161.143.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.860.13; Wed, 18 Jan 2017 09:04:42 +0000 Received: from SN1NAM02FT024.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::201) by BY2PR02CA0112.outlook.office365.com (2a01:111:e400:5261::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.860.13 via Frontend Transport; Wed, 18 Jan 2017 09:04:42 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by SN1NAM02FT024.mail.protection.outlook.com (10.152.72.127) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.803.8 via Frontend Transport; Wed, 18 Jan 2017 09:04:41 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:44939 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1cTmAb-0006fT-3d; Wed, 18 Jan 2017 01:04:41 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1cTmAa-0001K5-Vr; Wed, 18 Jan 2017 01:04:41 -0800 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id v0I94bB8022779; Wed, 18 Jan 2017 01:04:37 -0800 Received: from [172.23.37.99] (helo=xhdsivadur40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1cTmAX-0001Ej-0b; Wed, 18 Jan 2017 01:04:37 -0800 From: Siva Durga Prasad Paladugu To: Date: Wed, 18 Jan 2017 14:34:27 +0530 Message-ID: <1484730271-21944-9-git-send-email-sivadur@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484730271-21944-1-git-send-email-sivadur@xilinx.com> References: <1484730271-21944-1-git-send-email-sivadur@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22830.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(39410400002)(39850400002)(39840400002)(39450400003)(39860400002)(2980300002)(438002)(189002)(199003)(5003940100001)(38730400001)(2351001)(356003)(107886002)(50986999)(77096006)(33646002)(54906002)(39060400001)(76176999)(2950100002)(5660300001)(626004)(8676002)(305945005)(81156014)(6666003)(6916009)(110136003)(189998001)(81166006)(63266004)(4001430100002)(106466001)(47776003)(2906002)(36386004)(4326007)(48376002)(9786002)(8936002)(36756003)(50466002)(50226002)(92566002)(107986001)(5001870100001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR02MB1388; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; SN1NAM02FT024; 1:AiUo+09uUfiNJQgiKNH8Ns8cfEnjv5VRcAUQZJxJJlvhmYqjQukQNLgPO9oKx4KSjDFbbYI1sSAuMOWt3nFWyCSnwJ31s3j8aNqy6xLZSTFItKeXNqOMUHzetI3D1BLUyH9DMCsxH+gema87d3pjINbu9SVufzfgwpaN4+p1IAS+t5jmfRGVsoTeh1nHZGu83CzU/iOoRrMgQYlqNvkHhwB3x6nsiF+0QmN87rUgHbqYPU+g4bbOZVwPjK2iWla1iKknrqeC6gbBR7zV3HXdM3Y0iGd6z7PHpC+rSN/FSnhFEowcopPWQU4FIfe0dwPiQYQKTagvh+yMJXpoYaO9SxKus+fo4u99kltmS4084XJnO3zeE+PQJZsTEPEDRZK9p4neS5SNCxiL0hYV8OfNg6lvlilqT75WvLcLExoMNZMYZ/H6/s3EqM61udC8QMhyOrIA9AytMJwdjGuCzyw05DAhYnRy5iCd2pGES8iX4EwYGa4PdDgCQAW+42sX4k4hUOFdNsdwqL/lHFSDk/dObHYjQS6Qrr9tl+IR6Gl/ofY56R0ILo4VCyhA/bzMPOXxz9hmHisKu9QPJ80vDGJ5ow== MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 4788eb63-3f1f-4557-9274-08d43f8109f5 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(8251501002); SRVR:DM2PR02MB1388; X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 3:xST4j9gAZGky85I48fPXPwr7IUDx8U7/dBad0Yr6+aIWp0S4Z2XUTPY3fG7NdfFCQB9yhvRIbk/PgiSNoswNOyIdnMKWwW6vF2FlH7+AjTroJ3zmqNkKYIwoSopclreYCDb6Z7E6fj8XYcXNIsT1N3WUKEW+WfykZnOsolXznYINkWOL7ryoGNwBRWH6ZGL32h5xS8w0y4yhiUmJKFHUQjokISTwA2sRcLCXUBfLnBg8Zpw+VP398xLsIuR8AUgiTljd2O0OtxjOR63CW6htxj9uKURrsNd9Ff30izpqQCI3qe80x/K8YSFgumiZSalLeoRovjX9apGRt2Rxz2beRsURCGn6UhyqmbKHbmjY2OysIiwsp4zUJc/2VtkPF9eZm/Vk/KcYrPcfKPr5HJPf8A== X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 25:MS8AQA0AtHN66Bj3H0SeWOnDQ7xml230XIjSNuY81HvfAsxjPIxKJtoOjwEIoAK5b+VUpp4bFjIdj2m0XF0ptXFXjWQVOzhPhMUcFyyAevTiV16gXlhVmLXLjZFZFEZ6sWyr/SS8h+t+XJHyH/LwiF0IDOxrRKOUpnCSZEXzFjLw08sWHG7lT25GoL1Te+I+Z/RIEjw1BJbFkNzBtuC3vMq+L1xq77hmAhw75x94EY9AfhThmivB+k4GsOCVALIX/nH5iDWxiZQyxGU4QGBoZkrbZzIoxpPz1nuX4rJR7K0Q5hk4d2L9XNcK5kG0rEKQr45PDHTW2yo6iWk3pUGNMgperwWzWCrq19sj32eICPWd321g/yHY1JmmXw549K/0CaCD3kY09eKb2PUnzTKiw2FZ5Xx0k7B79vtCVY4E6NgPgayzjb12rDwVBtQSbWVGNPLUyt0FyqSZU91b0QT3+VE2mKtk7qH5ytcbX3UQEMqifCUHtLjcvVJFcb8ZikuHvAkeiRiAVF0dryrT8smUHaXZwl9PSs1uoLzFf7qfNGrFT/AcLmzNCVMcAmFedsi+kj98e0QLDXxUZ9z5KVfeyrpH6FPBkezjRFwMGMC3wKeC3CUvwFS/jForX4+M98orK/wnQte5TvR6ePnT+UO05DybJ0a9x+2Z6eVPrDCbANw/bzcu5f68tgPY/dus04DuZ571PzSJZxLr5X9/IYCWZMbJSjAA0VfMRVL8b9/raQjaKrvS4k0lH5Y/p293wLYlHO3Xy482cvAz9KtGV+7mA4AXKTIGIHDGFFMrdFUjapLh0Oy/py2ltYVux69Z7AfVLIEXqWItUi/pphpIlJxKfg== X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 31:Wke/TUMFZbwWHZjGhvnFGpjm8C/ougxAX4+0VikimKiLLRbVfLYeIOen0MBuk+gRKSMtB0yrlzqU51t/QIMkGw0MTotJylzyYyOFkxZtJToQ27BDRVsCMbOhrAEKYsclNfEuZJknQRZB5GNhPv5slz3UZW4M1mxyunaj+UNiksTrjRCoiDMvIrMecKD/hFlnwoPeIVIqj7UtgIT8Nc46r4MiRG2fZQY58Up+2lramdYMqY4KV5kyBABo9B6NC9ljgAwkPL/aJStcl4bNZtcHlnZdohRo5Es4gBd0ZX+u6QI=; 20:Kjn04y3e+FZcMCd1T9q/enm4wxP3V/cjV4OCs7jMWbsgKTapnsEsuB9s73OrsZcolu4fw3twblf1Mgdb493FaC7BG9RmY5YfS8rm7RNzyhEJbtsQvZWlU+wcUK131vmxvW2NvJi/S3EzpLaNQnlwxQScKh9ZIs0O9g+49Bs61TI+qlF11hzIxyVZY+1ABvTkuqK3uSGdVsBQzbOGC3oOlYk+cK9ks7Dgggs04W7eTmHL8YHRxPrzCfkxaI7LuRb9riNbwOZvrQVgvfT9Zh05UQMCDkN8EfMOp7PSQ2O0Q6UtZZzlDhBF18McqCPfXo4Ht0buAeAxIRxNAw5PTJiqiFLeinDJLdWraXckLj79zPqI/vY3QRBeESTb2JqI7vXWJm7Ax2gxhpb5QtcoAy1GoG4PC6JW5zRAD41AYfJj4xCQFmv/O/0tzGxHVS/HGcajojSp8KvRARRX1HlkUcHFMWpALxtJ1OSCSY5E/OKAmW2xOiR/BHfGSXmDR4cLhut+ X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040375)(601004)(2401047)(13015025)(13017025)(13018025)(13023025)(13024025)(8121501046)(5005006)(10201501046)(3002001)(6055026)(6041248)(20161123564025)(20161123555025)(20161123558021)(20161123560025)(20161123562025)(6072148); SRVR:DM2PR02MB1388; BCL:0; PCL:0; RULEID:; SRVR:DM2PR02MB1388; X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 4:I7ldVScs//PkQyBI2sTD7niYpdCpwxJKWG5XmcFOU5VN9z6+FQ7LeXSoy1zW3o+GKsEOzgmz1YRfJaobmb99fnBrvysOB6ocz6gtqZ8aDvxPbd+1evFtDUAn8bRtWuqzWF6v5nNMJwUkiSCq72tBvTsZCzUVM2B0YPY9k9fIml8VhMunJRDqJFgQZ9ea5PNuBTmTMsWR2qV2AZeXGbgkvu+7cXMHMBHTqyKQVdonVfEaX+4CfJ2qc/PKLH5lhLyP67ZRGrFwD84KoHsG0sz7Dkk1mcnwWGWgTenxCFOIHHRz3oFzgRMRG2eNR+FdzrX0lFlrAkczzLd2DLld37HgYlk53XvbvmnA3ZbEj8EUyoxkquJ2bldFrAS/zmvADLRydbznNw/PPgp3rW+TYG4gYSevKnrY0G/LmmEf9QGKXoBbicJ6OwjZ5T+INOl208nUVza3fKtJT/EnIU32VZKoRhEgdu/b/PfldS+Cc9t0UI4/QREeJUVVGkHCMOmiwoUugjLMgp7kZmAby3TpMRoBiyn1Z/HlBaMByBN8MGZZZN10/SfWSkHBZ6OtTFYe2LokDLRmC4a4wzB7na3ryX1qUoMQ7zg27F0K68Oha/ZWzy9N8nZ8wgCZlcj/r7F36AkuqgDbHOWwe1PtNBsgMCZNQxu1nwzJb87KlOARMudJPE0o+2VEphY2RKdYKGNtWLFhJCFq/FMirtvyuw1nKUgykdGpSvJhXTlyI1KKY9/ED+hZH53kNcLT57BsJZ50NIGPj7CTXDg5fKAs/nIegM0b9w== X-Forefront-PRVS: 01917B1794 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM2PR02MB1388; 23:03YCaPDX2lPz1MaIZUynkMIgcDJOHziRm8zEfu6ZM?= =?us-ascii?Q?wV/LN+lz2osiL2sCQ4+kNyBYiUB1VKuByjFRhGxVOYbGHJhc+onX+ref2Jgy?= =?us-ascii?Q?aioJuqtSsoV+WdagJi1JU7Z/HFReVq1VD3P36a4mOAQtqhkGh0zQ5x7Azc79?= =?us-ascii?Q?BJev1xw9Lg9oNkKW3Kk5L3Fcu35BJjY4mqUv9OTXKAXUX3gmSBFnfYsWiWvt?= =?us-ascii?Q?ch3Fbgl4DkqFDuJ3BizDeDwe6nPDrpLcMb4BRwbP8TtL1P/GPF79iNIw48fQ?= =?us-ascii?Q?4i1Hs8mBPp7tDgvthW3ieRkc24Lb6W/Jmfu3Zs0xQKauDCfmN6EDz3m5NC2K?= =?us-ascii?Q?I3sjoGo1HH2GeKRV26fr6AQEUIvTKPdYlnzXrh0fEEvWdKwdJQbhoJ89C5sY?= =?us-ascii?Q?TeBfuZlx8G9ysM3ATW74uIH6soAlQqImM5DZIo2TwKEPtLSmiPmjpx5XvZST?= =?us-ascii?Q?6ZqmILystcUSVB/IJqYtSstkgkv7qLB12RlfGZ4jne+YGzWZmpkoaTqoSOR9?= =?us-ascii?Q?TFtLgm+u6lrpvepuZHjl0uyhk35GtB27S/SiBuZmMbKZKsexwevcnrj7K6zS?= =?us-ascii?Q?ZTF6iU4e6S/uzxGO5d5BXSW1EhbR9Wj1VsMo3BQXI8ldKOnq1ROj2YTiEEdO?= =?us-ascii?Q?9dJdgmgGg0oopsZM2pgVyFLpJm7l0R0tzE3ahk/W2UOCHI6qf1cYJ+SR5sJ2?= =?us-ascii?Q?LsCHrcQjK2200M+McSJfwnyxss7Sqpam++zbVePLllg4PLERoE+sEwU5NV51?= =?us-ascii?Q?0mzLEPVVpEiPHiF8fTCrE/podGn4LUuBB54CUFxML13XsNrdv+w1c3ENJHmq?= =?us-ascii?Q?lkBOggH82lQWSxA7fmRNNy7XOKPSO4J/q1x1EIfRNHC78WoZAJYpLyP49MVM?= =?us-ascii?Q?v87mniq9XGTGdwre+tdhAyL46gAWlYBHAYAKZk6CsHlfrVvehP/bAt8Swi9t?= =?us-ascii?Q?cM9/Qx2gpCVn7iNJZ7R3A5Ad40pXaaSEWLm7BuS+FGehUoUkiDTiH9r/nBAD?= =?us-ascii?Q?5e59IwvXmu5ysQNjhVBrlCpmmJE5rngLgmSvUhUq7BL8WR57mvfXpaTzMvgm?= =?us-ascii?Q?9unBsr0K8FYBpOKy4ksLdPZu+IblILhxESp3y0mychGnUoEqv9b+U8F0n7Km?= =?us-ascii?Q?mFloPtRJ0EoVF38VXUFEMPWHZAOgr3yNm6EHN8myWx8SfqN3LMXaqQVnAWoR?= =?us-ascii?Q?tb1Q1hEc5cavdnIKBvvFqWyL0eW1x6nC2VH3AE0wxLp6sH9pUm4P48EHw=3D?= =?us-ascii?Q?=3D?= X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 6:2/65zWNVbodmQ416kcVMkWT9bAgnFcc4cvmUXh9tyGzaPy+/8Rkfnwuu35NHqMT/5nrGvoZJO9pwBUPV8AzIEYTkkXOskDsqvfWiWemP+FgA2SSr03FGLuGd3ufO2+/LxH1xpxxa7on7nuA4lYR+i4wyPI6SLF3pjcVAKCvwZT9Nl1WU6vHuSihxzp0rbXg4EgnHcsE5/Hyr1oHtuFL6Ug8SHEm+5XeN3exl7R8OFdFFauxm6B6aVRk0AHLjZcaBkUwt0ue6BRwZC6pOS2Kz6uS/K1x3+Mv+E8iI0szkQ6bHx2Z7kEySXzRjROOi9a8QGZDtoKB15z56AmQLyCwomtRdcjyLjMP6WKmuRuCcXUDFM8DxzwGZDYWlL5b4AZ997FA3UQQg+hEp0EP6x/030l0iIYmUB69Svtdqn9w/nullV7P4cFXGud65oVR8uxNGb0SNzNARaR7u879rStzo0A==; 5:GSg7AOUblks2GxmiVtU3AhzsKsLgzwo/pSugVZSnB5MFkYm4/34eqrOEm7MFaKNQvf/2we+TKoM47OYq/LyYqQOPAYikvurBFTiUINPgIKmQzdv40P+/F/fJjrAHr10x3mZE7migeffwK1pFUPjP4Q==; 24:tMgy/ja9skCNDssXsjlCljxw2AtovIin+gsy4YXfisogSQ6prmNJ2xaKaV8OI1bEMfWBZ0ao0ePBx0VoWW1rcDKjsU9wJxxpPpEULj+ssaU= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM2PR02MB1388; 7:+XXxENyp3PhQFGL5TTy18SEYpUTDJVB03YjL4n0/7hlXcfXWbOMoOSpotDJpknBW8serv6IGBzLCA9u8Y5hwP8AAOrZzr5V5S3ZkFGdSi7EwUd/uPi+yUFJhUXTQpkmAK4WDCHIaWofuHGOW0AI9e20pvFkfjH9LLzbxbw6fiMuY0uJwPCGIMexwBKEOqxJCmyRmR49CrESIDROPW5PLMt8hQ1BmksbCdtqDmD0TkjzcIGMawovArc28tJknOi+TL4d4bKrscg4aalE8TAvwRLyue0ik6+Ki1spFMhZBEPdLj25r95J66WAetk8hChm3mn+7/dktkhvrJtbnT0Ga76QpNoaxCra6yQBEXTse+xMQiCxBZYprYljRkrGP8rcvNUDnYpVkgx9hkh+cHFmjXe1n54aEX+hT7ouzlW23KfAWKYY9exJYZZ66T0uQc/+dOqZ0zhfsOZBKLe3Hy+K0MA== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2017 09:04:41.3846 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR02MB1388 Cc: afleming@gmail.com, michals@xilinx.com, Siva Durga Prasad Paladugu Subject: [U-Boot] [PATCH 08/12] mmc: sdhci: zynqmp: Add support of SD3.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add SD3.0 support for ZynqMP, this support needs a platform specific tuning and tap delays for UHS modes of SD3.0 and this patch takes care of it. Signed-off-by: Siva Durga Prasad Paladugu --- board/xilinx/zynqmp/Makefile | 1 + board/xilinx/zynqmp/tap_delays.c | 249 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/zynq_sdhci.c | 142 +++++++++++++++++++++- include/zynqmp_tap_delay.h | 20 ++++ 4 files changed, 411 insertions(+), 1 deletion(-) create mode 100644 board/xilinx/zynqmp/tap_delays.c create mode 100644 include/zynqmp_tap_delay.h diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 9d69d65..2bf0375 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -20,6 +20,7 @@ $(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/ endif endif +obj-$(CONFIG_ZYNQ_SDHCI) += tap_delays.o obj-$(CONFIG_SPL_BUILD) += $(init-objs) # Suppress "warning: function declaration isn't a prototype" diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c new file mode 100644 index 0000000..d57587e --- /dev/null +++ b/board/xilinx/zynqmp/tap_delays.c @@ -0,0 +1,249 @@ +/* + * Xilinx ZynqMP SoC Tap Delay Programming + * + * Copyright (C) 2016 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SD_DLL_CTRL 0xFF180358 +#define SD_ITAP_DLY 0xFF180314 +#define SD_OTAP_DLY 0xFF180318 +#define SD0_DLL_RST_MASK 0x00000004 +#define SD0_DLL_RST 0x00000004 +#define SD1_DLL_RST_MASK 0x00040000 +#define SD1_DLL_RST 0x00040000 +#define SD0_ITAPCHGWIN_MASK 0x00000200 +#define SD0_ITAPCHGWIN 0x00000200 +#define SD1_ITAPCHGWIN_MASK 0x02000000 +#define SD1_ITAPCHGWIN 0x02000000 +#define SD0_ITAPDLYENA_MASK 0x00000100 +#define SD0_ITAPDLYENA 0x00000100 +#define SD1_ITAPDLYENA_MASK 0x01000000 +#define SD1_ITAPDLYENA 0x01000000 +#define SD0_ITAPDLYSEL_MASK 0x000000FF +#define SD0_ITAPDLYSEL_HSD 0x00000015 +#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D +#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012 + +#define SD1_ITAPDLYSEL_MASK 0x00FF0000 +#define SD1_ITAPDLYSEL_HSD 0x00150000 +#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000 +#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000 + +#define SD0_OTAPDLYENA_MASK 0x00000040 +#define SD0_OTAPDLYENA 0x00000040 +#define SD1_OTAPDLYENA_MASK 0x00400000 +#define SD1_OTAPDLYENA 0x00400000 +#define SD0_OTAPDLYSEL_MASK 0x0000003F +#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006 +#define SD0_OTAPDLYSEL_SD_HSD 0x00000005 +#define SD0_OTAPDLYSEL_SDR50 0x00000003 +#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003 +#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002 +#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004 +#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006 + +#define SD1_OTAPDLYSEL_MASK 0x003F0000 +#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000 +#define SD1_OTAPDLYSEL_SD_HSD 0x00050000 +#define SD1_OTAPDLYSEL_SDR50 0x00030000 +#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000 +#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000 +#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000 +#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000 + +#define MMC_BANK2 0x2 + +#define MMC_TIMING_UHS_SDR25 1 +#define MMC_TIMING_UHS_SDR50 2 +#define MMC_TIMING_UHS_SDR104 3 +#define MMC_TIMING_UHS_DDR50 4 +#define MMC_TIMING_MMC_HS200 5 +#define MMC_TIMING_SD_HS 6 +#define MMC_TIMING_MMC_DDR52 7 +#define MMC_TIMING_MMC_HS 8 + +void zynqmp_dll_reset(u8 deviceid) +{ + /* Issue DLL Reset */ + if (deviceid == 0) + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, + SD0_DLL_RST); + else + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, + SD1_DLL_RST); + + mdelay(1); + + /* Release DLL Reset */ + if (deviceid == 0) + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); + else + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); +} + +static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank) +{ + if (deviceid == 0) { + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK, + SD0_OTAPDLYENA); + if (bank == MMC_BANK2) + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_SDR104_B2); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_SDR104_B0); + } else { + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK, + SD1_OTAPDLYENA); + if (bank == MMC_BANK2) + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_SDR104_B2); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_SDR104_B0); + } +} + +static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank) +{ + if (deviceid == 0) { + /* Program ITAP */ + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + SD0_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, + SD0_ITAPDLYENA); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, + SD0_ITAPDLYSEL_HSD); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK, + SD0_OTAPDLYENA); + if (timing == MMC_TIMING_MMC_HS) + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_MMC_HSD); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_SD_HSD); + } else { + /* Program ITAP */ + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + SD1_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, + SD1_ITAPDLYENA); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, + SD1_ITAPDLYSEL_HSD); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK, + SD1_OTAPDLYENA); + if (timing == MMC_TIMING_MMC_HS) + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_MMC_HSD); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_SD_HSD); + } +} + +static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank) +{ + if (deviceid == 0) { + /* Program ITAP */ + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, + SD0_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK, + SD0_ITAPDLYENA); + if (timing == MMC_TIMING_UHS_DDR50) + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, + SD0_ITAPDLYSEL_SD_DDR50); + else + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, + SD0_ITAPDLYSEL_MMC_DDR50); + zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0); + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK, + SD0_OTAPDLYENA); + if (timing == MMC_TIMING_UHS_DDR50) + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_SD_DDR50); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_MMC_DDR50); + } else { + /* Program ITAP */ + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, + SD1_ITAPCHGWIN); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK, + SD1_ITAPDLYENA); + if (timing == MMC_TIMING_UHS_DDR50) + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, + SD1_ITAPDLYSEL_SD_DDR50); + else + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK, + SD1_ITAPDLYSEL_MMC_DDR50); + zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0); + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK, + SD1_OTAPDLYENA); + if (timing == MMC_TIMING_UHS_DDR50) + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_SD_DDR50); + else + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_MMC_DDR50); + } +} + +static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank) +{ + if (deviceid == 0) { + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYENA_MASK, + SD0_OTAPDLYENA); + zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, + SD0_OTAPDLYSEL_SDR50); + } else { + /* Program OTAP */ + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYENA_MASK, + SD1_OTAPDLYENA); + zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, + SD1_OTAPDLYSEL_SDR50); + } +} + +void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank) +{ + if (deviceid == 0) + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, + SD0_DLL_RST); + else + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, + SD1_DLL_RST); + + switch (timing) { + case MMC_TIMING_UHS_SDR25: + arasan_zynqmp_tap_hs(deviceid, timing, bank); + break; + case MMC_TIMING_UHS_SDR50: + arasan_zynqmp_tap_sdr50(deviceid, timing, bank); + break; + case MMC_TIMING_UHS_SDR104: + arasan_zynqmp_tap_sdr104(deviceid, timing, bank); + break; + case MMC_TIMING_UHS_DDR50: + arasan_zynqmp_tap_ddr50(deviceid, timing, bank); + break; + } + + if (deviceid == 0) + zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0); + else + zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0); +} diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 2c1561c..e1377cd 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -12,11 +12,18 @@ #include #include #include +#include +#include +#include +#include +#include "mmc_private.h" #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 #endif +DECLARE_GLOBAL_DATA_PTR; + struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; @@ -24,8 +31,131 @@ struct arasan_sdhci_plat { struct arasan_sdhci_priv { struct sdhci_host *host; + u8 deviceid; + u8 bank; }; +#if defined(CONFIG_ARCH_ZYNQMP) +static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) +{ + u16 clk; + unsigned long timeout; + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~(SDHCI_CLOCK_CARD_EN); + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Issue DLL Reset */ + zynqmp_dll_reset(deviceid); + + /* Wait max 20 ms */ + timeout = 100; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + dev_err(mmc_dev(host->mmc), + ": Internal clock never stabilised.\n"); + return; + } + timeout--; + udelay(1000); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct mmc_cmd cmd; + struct mmc_data data; + u32 ctrl; + struct sdhci_host *host; + struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); + u8 tuning_loop_counter = 40; + u8 deviceid; + + debug("%s\n", __func__); + + host = priv->host; + deviceid = priv->deviceid; + + ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2); + ctrl |= SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2); + + mdelay(1); + + arasan_zynqmp_dll_reset(host, deviceid); + + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); + + do { + cmd.cmdidx = opcode; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + data.blocksize = 64; + data.blocks = 1; + data.flags = MMC_DATA_READ; + + if (tuning_loop_counter-- == 0) + break; + + if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 && + mmc->bus_width == 8) + data.blocksize = 128; + + sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, + data.blocksize), + SDHCI_BLOCK_SIZE); + sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT); + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); + + mmc_send_cmd(mmc, &cmd, NULL); + ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2); + + if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK) + udelay(1); + + } while (ctrl & SDHCI_CTRL_EXEC_TUNING); + + if (tuning_loop_counter < 0) { + ctrl &= ~SDHCI_CTRL_TUNED_CLK; + sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2); + } + + if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { + debug("%s:Tuning failed\n", __func__); + return -1; + } else { + udelay(1); + arasan_zynqmp_dll_reset(host, deviceid); + } + + /* Enable only interrupts served by the SD controller */ + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, + SDHCI_INT_ENABLE); + /* Mask all sdhci interrupt sources */ + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); + + return 0; +} + +static void arasan_sdhci_set_tapdelay(struct sdhci_host *host, u8 uhsmode) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); + + debug("%s, %d:%d, mode:%d\n", __func__, priv->deviceid, priv->bank, + uhsmode); + if ((uhsmode >= MMC_TIMING_UHS_SDR25) && + (uhsmode <= MMC_TIMING_UHS_DDR50)) + arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, + priv->bank); +} +#endif + static int arasan_sdhci_probe(struct udevice *dev) { struct arasan_sdhci_plat *plat = dev_get_platdata(dev); @@ -52,6 +182,11 @@ static int arasan_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; upriv->mmc = host->mmc; +#if defined(CONFIG_ARCH_ZYNQMP) + host->ops->set_delay = arasan_sdhci_set_tapdelay; + host->ops->platform_execute_tuning = arasan_sdhci_execute_tuning; +#endif + return sdhci_probe(dev); } @@ -66,6 +201,11 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->host->name = dev->name; priv->host->ioaddr = (void *)dev_get_addr(dev); + priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,device_id", -1); + priv->bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,mio_bank", -1); + return 0; } @@ -89,6 +229,6 @@ U_BOOT_DRIVER(arasan_sdhci_drv) = { .ops = &sdhci_ops, .bind = arasan_sdhci_bind, .probe = arasan_sdhci_probe, - .priv_auto_alloc_size = sizeof(struct sdhci_host), + .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv), .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), }; diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h new file mode 100644 index 0000000..14cff9d --- /dev/null +++ b/include/zynqmp_tap_delay.h @@ -0,0 +1,20 @@ +/* + * Xilinx ZynqMP SoC Tap Delay Programming + * + * Copyright (C) 2016 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ZYNQMP_TAP_DELAY_H__ +#define __ZYNQMP_TAP_DELAY_H__ + +#ifdef CONFIG_ARCH_ZYNQMP +void zynqmp_dll_reset(u8 deviceid); +void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank); +#else +inline void zynqmp_dll_reset(u8 deviceid) {} +inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {} +#endif + +#endif