From patchwork Tue Dec 13 16:56:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 705448 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tdQrz2c9Wz9sfH for ; Wed, 14 Dec 2016 03:58:43 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 00036A75F1; Tue, 13 Dec 2016 17:58:07 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3SwN7AfLHKrF; Tue, 13 Dec 2016 17:58:07 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 065E6B387C; Tue, 13 Dec 2016 17:57:42 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB511A75B4 for ; Tue, 13 Dec 2016 17:57:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9BirNhV7yodx for ; Tue, 13 Dec 2016 17:57:31 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wj0-f195.google.com (mail-wj0-f195.google.com [209.85.210.195]) by theia.denx.de (Postfix) with ESMTPS id 02CF6A75BF for ; Tue, 13 Dec 2016 17:57:23 +0100 (CET) Received: by mail-wj0-f195.google.com with SMTP id he10so17339895wjc.2 for ; Tue, 13 Dec 2016 08:57:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2XpnNluxohkQp1NFNR+4RSweKrth/Y8p5CWf1kMat0M=; b=i2HHSqAnKW0rwUHuoT+shM+6rXHGOnvW24KUJhmyJzXF3QEKKumgw+iGVW+ahVr3FS UOnhE7Y0VhNXnRSB1d+MWk9WNr/FQbgmVYdh695QSikpY/wRDLorvC400qqWiwM2/CT6 5MSnI5qu329xu5YUf2wmSdcqeEd+D1gVECoCfnDd3ItQUFh2wzZfB1g9/EPuIiTm1kRi TCBd8SyhLbD5vCBQgYGgrWzeOlwGS8AwiCr2d80wIduNwKR6rkzYuSG3dtmgc+E0HZYr cQ4gveThczDerk6gM4dx+RFGNWuVgufJI32AW36U9A30V6q0Pn8TFPkxuPRmEh9DInY1 vYRQ== X-Gm-Message-State: AKaTC000Hq51PhE0BTMMR8R9Ybr+pfOuKzYwQCfZYzD9gSYZUdPQEBKUZUYsLXI7w9+AJw== X-Received: by 10.194.157.3 with SMTP id wi3mr85212531wjb.0.1481648242785; Tue, 13 Dec 2016 08:57:22 -0800 (PST) Received: from jagan-XPS-13-9350.homenet.telecomitalia.it (host47-201-static.1-79-b.business.telecomitalia.it. [79.1.201.47]) by smtp.gmail.com with ESMTPSA id x5sm63053887wje.36.2016.12.13.08.57.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Dec 2016 08:57:21 -0800 (PST) From: Jagan Teki To: Stefano Babic Date: Tue, 13 Dec 2016 17:56:55 +0100 Message-Id: <1481648226-30773-6-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481648226-30773-1-git-send-email-jagan@openedev.com> References: <1481648226-30773-1-git-send-email-jagan@openedev.com> Cc: u-boot@lists.denx.de, Matteo Lisi Subject: [U-Boot] [PATCH v4 05/16] imx6: geam6ul: Add NAND support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add NAND support for Engicam GEAM6UL board. Boot Log: -------- U-Boot SPL 2016.11-g537fa5f (Nov 28 2016 - 11:42:28) Trying to boot from NAND NAND : 256 MiB U-Boot 2016.11-g537fa5f (Nov 28 2016 - 11:20:06 +0100) CPU: Freescale i.MX6UL rev1.1 69 MHz (running at 396 MHz) CPU: Automotive temperature grade (-40C to 125C) at 42C Reset cause: WDOG Model: Engicam GEAM6UL DRAM: 128 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 * Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/geam6ul/geam6ul.c | 71 ++++++++++++++++++++++++++++++++++++++ configs/imx6ul_geam_nand_defconfig | 34 ++++++++++++++++++ include/configs/imx6ul_geam.h | 24 ++++++++++++- 3 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 configs/imx6ul_geam_nand_defconfig diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c index 8530845..40f20a9 100644 --- a/board/engicam/geam6ul/geam6ul.c +++ b/board/engicam/geam6ul/geam6ul.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -36,11 +37,81 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_NAND_MXS + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif /* CONFIG_NAND_MXS */ + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; } diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig new file mode 100644 index 0000000..b7a44c7 --- /dev/null +++ b/configs/imx6ul_geam_nand_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_GEAM=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" +CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" +CONFIG_SYS_PROMPT="geam6ul> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NAND=y +CONFIG_CMD_CACHE=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_NAND_MXS=y +CONFIG_IMX_THERMAL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_DMA_SUPPORT=y diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 794a656..4fe130b 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -27,6 +27,10 @@ /* Environment in MMC */ # if defined(CONFIG_ENV_IS_IN_MMC) # define CONFIG_ENV_OFFSET 0x100000 +/* Environment in NAND */ +# elif defined(CONFIG_ENV_IS_IN_NAND) +# define CONFIG_ENV_OFFSET 0x400000 +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -111,9 +115,27 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #endif +/* NAND */ +#ifdef CONFIG_NAND_MXS +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 +# define CONFIG_SYS_NAND_5_ADDR_CYCLE +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +# define CONFIG_APBH_DMA +# define CONFIG_APBH_DMA_BURST +# define CONFIG_APBH_DMA_BURST8 +#endif + /* SPL */ #ifdef CONFIG_SPL -# define CONFIG_SPL_MMC_SUPPORT +# ifdef CONFIG_NAND_MXS +# define CONFIG_SPL_NAND_SUPPORT +# else +# define CONFIG_SPL_MMC_SUPPORT +# endif # include "imx6_spl.h" # ifdef CONFIG_SPL_BUILD