From patchwork Fri Nov 25 18:56:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Breno Matheus Lima X-Patchwork-Id: 699359 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tQR1q0KsVz9t1d for ; Sat, 26 Nov 2016 06:28:13 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E19244B99D; Fri, 25 Nov 2016 20:28:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7F85ktDJgdrK; Fri, 25 Nov 2016 20:28:09 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 63DF44BA29; Fri, 25 Nov 2016 20:28:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A39404BA29 for ; Fri, 25 Nov 2016 20:28:04 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fT5--wPKKkQC for ; Fri, 25 Nov 2016 20:28:04 +0100 (CET) X-Greylist: delayed 1110 seconds by postgrey-1.34 at theia; Fri, 25 Nov 2016 20:27:59 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0089.outbound.protection.outlook.com [104.47.37.89]) by theia.denx.de (Postfix) with ESMTPS id AE7E24B99D for ; Fri, 25 Nov 2016 20:27:59 +0100 (CET) Received: from BN6PR03CA0030.namprd03.prod.outlook.com (10.175.124.16) by CY1PR0301MB0746.namprd03.prod.outlook.com (10.160.159.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.734.8; Fri, 25 Nov 2016 18:55:17 +0000 Received: from BN1BFFO11FD002.protection.gbl (2a01:111:f400:7c10::1:103) by BN6PR03CA0030.outlook.office365.com (2603:10b6:404:10c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.747.13 via Frontend Transport; Fri, 25 Nov 2016 18:55:16 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD002.mail.protection.outlook.com (10.58.144.65) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.734.4 via Frontend Transport; Fri, 25 Nov 2016 18:55:16 +0000 X-IncomingTopHeaderMarker: OriginalChecksum:; UpperCasedChecksum:; SizeAsReceived:663; Count:8 Received: from b58964-3.am.freescale.net (b58964-3.am.freescale.net [10.29.244.171]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id uAPItCbM028957; Fri, 25 Nov 2016 11:55:13 -0700 From: Breno Lima To: Date: Fri, 25 Nov 2016 16:56:57 -0200 Message-ID: <1480100217-853-1-git-send-email-breno.lima@nxp.com> X-Mailer: git-send-email 2.7.4 X-IncomingHeaderCount: 8 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131245737166684234; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(2980300002)(1110001)(1109001)(336004)(339900001)(199003)(189002)(85426001)(8666005)(4326007)(626004)(5003940100001)(50466002)(575784001)(97736004)(39060400001)(38730400001)(356003)(8676002)(33646002)(36756003)(2906002)(7846002)(86362001)(305945005)(81156014)(8936002)(81166006)(189998001)(47776003)(110136003)(48376002)(6666003)(50226002)(5660300001)(92566002)(6916009)(68736007)(105606002)(104016004)(2351001)(106466001)(50986999)(77096006)(7059030)(32563001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0301MB0746; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD002; 1:d/zngS0KInACANkLB/Waa1FsjL63vAqF93trCBeIK+IoNTkiprdgbzD+P7t5OkAT+CngEjU0Lzc7Lmgo7wqzwH5q63GJgFC9XYOF6EsE6nP8YEy4IsgccjuFXXJ1kTQlxZUwnqIZQVDMeACRHdPFEo4DMoBH1jSVk9WlvckffWbWUBqFg1hf1IPjDEiZ1CtzsxmyxBMlOg1dL8rhFrFUQRB16vVWRoB4ZsWS9LTW6gmGdcge+86ECAIj20uzgSjf2jD794aMaQFptQJs5OhMq1HR+EwEqoJUt4Vm3kQPMK13GOGO8VMpOLOV3VwzSXnJVcxMblGcWd8j1091gr3+nMkl6rDTwJ3qeAFSGD2ka6LXURUPWa0NEio3zEZY8I7TpjtSbvQTU6FOHyXhxftn8xYlox7OBto38F24juEK9uKXSOtQKq0Vsw2fwrzKSa0TEjJLfywRQwodq0J4VYFHtNU0DLDjbrJnnmU8PRuL6MCm5HQao1VDxxGRqqE0yhxshO+I+bwSe8UqmluA560/MnIXmcePx4vVGHEC6HUtC/S7cAWAS0KTWVd9xwZRAwHAfqNNLNNDDcaceYrEk58liwhjIyPQTdok/YZM+JzKi2VM0dmjE5Z/xvFm2S0IlJ5io/fgd1iW00KUltrzT9WeYdsKmyWpQXcfo1X9SNiAAKER1WodkrbYjVtEn/RMFK1zbQoFBCPHVKcoy7yH3IFeeMTxUtqlcGp9/i32f2V8jG0= MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 2:XNHE3ItWZfrp3nx9XIT1Q1cbvnkwGq7H9YTvjsLwcE1xGUnzfNrC7mQjSlBXrJrUm8ccDosX/JieLzOwkEGr/tas/WM3er1+V/ZOyCnHtjCL7txsDwHpHigfUYyRXzIWILolam51ROFY0nQlfqGAHojNs0mahCE0K5vpWNHiUDA=; 3:JrRz7+lgeOP1CEICiE1qUYkFNXPPeED5K1eRHwTLyLZtnyDHpHtnYXeBAs5SgAGe/lcZppR/W+VcxDb5grYhRHJswAHos6sntuwvCAwPWZxojKlSxiDo/rXAHianP41kSjGBqM1c8LavZ9yRMP+05+hcPjmaqc6Vh6/ipuh8jMQm4mmwEA18s3smr9zaQP8caOWNaKVdlGcFhmtGiEh6TwJjZUYUc0Rzk0+0i2GaMIaJjBS0gbaV/hjoPEqnDakwgrZZz5HIGnJSrN/G2kEqWg== X-MS-Office365-Filtering-Correlation-Id: ed2bbe9d-fdb5-4237-53e1-08d41564987c X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:CY1PR0301MB0746; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 25:iWR82jW/64COFT0zI19dRcz6r6jcFDiWW0FubP/H6DWzZSmR7O50yNFf0To1JOjmXgZQIxH+4H0kZWchITsE+r7N+lD4d8gA0BME4HGu7omCPaewKtgj46cS54kNHlsfzVfwD6hl18Dq3ouvIwkYx3CDFNSKkyDXBq4YELhly9srvHzUmFjvqSece4Kt0EgtTE3fJXnr7ExO3f4azceYoiWg96hCpRm/kdg55r/rH0DFK4pzySw00JhiER700o9bIEYrmVsf+rfGdUkDEMA5gfDwvrN7d6ES/vqXq2W9plMNpLHP0DRfKQ0c04LxfXy/FGl3S2IOqL7iuSWWYYt336Zkc6OnMIUseWBWy3ui/e5MQ+lZNQgsfPwzlEj8H57Yl2GgwtwJBEgupkpnQ4vDFyXALk9X9opLUU+Clb52doVIIWfHJ0IddW6+p1ETQtgSmUs+34o/VKyrgxCsE5R/GOzPmZTksBPtrny8gTa0085kqTB9QZFHXs6IFUGiY6xpeZQPhL9kLTB3jx9l5IyB1qxdmIbgNv9Dic4Gc3SiZntpJsBULUScmYLHbuBM0jymJR7nVjJUpOcmR6FMNpt1uGk0SlZOcbt4vzVIVbeRp+4cbqN9A3njQ1SaN6WzXx3Ajs3c1Ds5Joas+eXhhazQ5kQIKRnqTsUai1R8RJV5CGbuc6kLIlU2Ix2vnoDqkdzLwiGFOjICKtQb05Lgc4yhaV5zyllgtkUbc06AQkCr9LDOzaClGlnz0mOnzaJ/o+ououH8rzpd7v/l5W67IkbbQ589Zjp9STfvpDITEDryRhsjCSmoEoX/L+4f/AWZKIVniDsnYIDh5eNt4AqxwcGKOZwC6H3Ks4tuxx2/CG47aw84o4Snqka5t8/ccv82eNJPlFQm9a9ZrzcKng2dBG/uqy4IqTSC6mSQBaZQUoEaosk= X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 31:FqrjDYZQpNmLHLR+c3A6hvcTLTx5J+IsY1rgz3aTbImRirM/ZoUmGqADDUzOCOCtcJmh4cJo+QjXlSdAOcE6479UN+16IyZC7LveBFR6Lb+83jfPgzIwS8oHS9HMOkHO51JQWScecxYE1udtMV+vMLfx4KIt46dPIhSTpm9erEbaNaX/B9Gom3H8Yp0RmicKKpwHTWzIv1QEOc2pcSh/R6GTkOtInS3Y4QOnVAvIWlmw1VyPcQI6h8pJYg2Lfp+7wfcwFJoiMs2G72f9Mj7ehA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(166708455590820)(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095060)(601004)(2401047)(8121501046)(13017025)(13018025)(13023025)(5005006)(13024025)(13015025)(3002001)(10201501046)(6055026)(6096035)(20161123556025)(20161123561025)(20161123565025)(20161123559025)(20161123563025); SRVR:CY1PR0301MB0746; BCL:0; PCL:0; RULEID:(400006); SRVR:CY1PR0301MB0746; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 4:AUH9VEuIu4SZCCJnK6xp5ifzC4HdTZsfv8sOXXsEbH2AZa7f11JfZ6yGOynFDF4k4POi0lP165mgifZNOMiFxdfvbhSgEXoGeFfK7fPJDuQSwUUVScdWa9Qu+8eKTN7f1SNM7zN6kAFVfUMOqlQbR00p8Blqu2fGK2Tp4IEUlHnZFXguXufGCiw+K3fInAgxIbcxpoHW9er8iaJDdYDoWJ6JNrkXEt0ooqHM1BfSj68XC5QU1XvFaKvLi+VA+Q5Txl+syrNNqlu8Ym7WBk3PTb4XLZ2We92dVGJrKNnmMQW07qbobkudH7goRQma48V5gYVWgNkwS5VFr3NEqcf6CM7TwI+MWMRF20IYl65EouU43Kb2p4F78LJGwomQDwX6jbMIwqJ/BbBuZ1ZQlb6lqRwyX07jtwrg9cQwhAaYG4UlDwl3fJYiRhRG2NG8QTGl+7gDYyNAdvF0Lm0hKrNzQDNEgXvUagyoaE0s0+pKxGk5Ouk+6bjGn0ewecGRdz8c0kd8weKXZ3XO4Ek4EWWVTKqGMIJKjECl1qNIh1+ITekHSVJc/2A6VyJn5+TYKBZxZG3DvVvOrarcLI47FpasWcnURkhbvFH80T8bDEx9sas0TrHkU+A6PlvalWkXgOQkK3814ec26CfsTuBMkLe9bH2krWWoHg/Vxnr/G5WtsF3YDzA1YUN7t07+7Q3LxbbcAZzqxlmAPuXkZEHkxUbivBMI6JnKwe0icxYUi3vIvu40ZJNNIoF6peWaUu0pCZG55/N+ggSpLOx3BVTsGqaOzw== X-Forefront-PRVS: 01371B902F X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR0301MB0746; 23:zEsCx5sc9SmRHIVGpqonxBs9+zISeayNwhDdntb?= =?us-ascii?Q?aWb5b0774qhCNSy4Cy3WBjvIxI8eWZHPEZ4Jja8DCZJo2q40xveoCWE8VvRJ?= =?us-ascii?Q?3KYJvEoAEVESTsd0UHSSGOpg0PCcBf83rtqqOHrkIo4vcD6RLIQbHFdtAtFo?= =?us-ascii?Q?bSfAiqiAsZQpl7GyltZQCgc2HCE4+Am+oNBYpdu/7cMN6NQ+txTxXbDV4Abn?= =?us-ascii?Q?1JPpsAnKimpCTjl4Ev/wudkRn80TLOyJkKabO0PiYr/68Y0or3aVuLqdXgVF?= =?us-ascii?Q?j+24wc9q3W1iRApGHPqyM8Uf4t4rkGASxwCyAodXm8E8NOg4vDW7xhwZM1mT?= =?us-ascii?Q?IC0FCCGtaOX3G41W0+2Rv2AZsr3xsctJWmaWPx/OZLZInIRPw6o0jRcRl3Hl?= =?us-ascii?Q?7CnFl9v3U9SZJOBcMbC3C+rOIYkUBmu2BWl7LcUk/tICRTu/wcj863cYnJov?= =?us-ascii?Q?UjeRhBynhdlfF8ylXWSKAl9PxFRCjreCGNTLTdjlCpSWJLTRa/I1yigKQAGk?= =?us-ascii?Q?FxxGtIWm+CPvIIiC/mpmGIMGgnrwL4dCeD8uOdT2hdV5TRufnvShN3d2tTVa?= =?us-ascii?Q?JRNJ+vM7sOu34iDfIxP+/SUCaInGYH2hE7Ax95fHc4NNNuZfSpc/Xz32rdSm?= =?us-ascii?Q?dgJADpYpPYNXwkQ5lw6nSpZjlNBoc+d81xwop6XXGyMtiHetNnMfMC0HvwKS?= =?us-ascii?Q?qbD5PRkVMzhxTF0TEiXcpWF4uHauN2yToYg/UXaOHnOdE6cs38ePbcteQF5+?= =?us-ascii?Q?TIslB8sZ4wnsyt0HTlUNkqNuz41FD2LChwiitbAg0N+rPePVf5JLo6BVInrY?= =?us-ascii?Q?/vBqgdGQ+PTxGW+Gh2G5RP0cLPD8CxtwswrdOFN0DaKddRIYoRFi1P1EPmOv?= =?us-ascii?Q?5Kb8FMjdtlL0Ova+pawQRriz0+3/ZQ/6wVwIcYe9cgI8myLK6oKXPjRjBVhG?= =?us-ascii?Q?NVrNgGMNw8bvSO1tK2cKfglE/qXVg4BlzKPhWQcafO+pcK7uhfm2OOJex587?= =?us-ascii?Q?PLTCqPcMCGye9sM0YUAtrFA2Qd6cPEALk8f4IC6Fjj6jGpKkuGCvTm4Z4wPr?= =?us-ascii?Q?rrvcUm+dA1yHm3Plpo+dZ7azEIXKNQHABBp95UJoLvP5GhbVoyEAY0bVmqRu?= =?us-ascii?Q?vrXN7uAP5gNZhZlQKoH0IcmItLSSyQo5m?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 6:TyzGf3fhkQEa90g4sovP8T/v63dnOsqfFx8t3Cw9VXtqsx5g1gHGworhwhrmIZyZpUAsThPZ5u2YGFhOdjh+u+0+qm0z7arKGxpKVXPRiWcRLjs5wgjJwrZfWpWDRd8h2S6NVxcvCEX202Avuo0wm9NjBIZ9i/LVPZNefjma2KaaOmgEKwTVShKsZ1HOUTY9cCBXXuD2YZ2+tCZ6hVVw4LOdw1Zn8ES+hBRTlkZIx2w52hMaixUYJVIsrpzMBEtUTZJgV3DNYSh8m/A3zEbaK9iyZ1O+Pv4aoPe3CtWmXPpTI7J5B08WuLd1Ar5caThLXkGTisZ1n4KNF/dqNL53Sg==; 5:0osOmy0aRH5r4pUba/Hb6Youg65p/jjbuBPl2+eXTPC4fjXCKTNkS4TptFCJe25gpshBUGDv4Kk6P/X284ehoOfNuteY2Ct6/0dDbos0eypvT4FPv3H0GTWmMt/89Szq8PIY4Patm+SihuTD1vmOMpHKLje8H0xH+TQu+OnnLokM7a1JnuU2H8fh+czF+uF8; 24:963cB0sHsKwyVGexnJhXhBFPPQTlS2HLT/NxBBFXEhQkwVNptG8hTqdE0hT6YoddToHEjhsfxBrg9ridz0c+i5UDgLz1REwdBsu0W2LxmAw= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0746; 7:oS3rUEnX0RCH3HkAsWdoEYc8Mqf/GywZ/MvVDwap4VgfBkW0GeJlf8mA/uBdjAvZAK/HWz6DiobXaCdz+WBEBo6KpOHvHMNyxTLfzu/HFRMOomU38jxk6qehqONCNLhkjaXIc66ZXLUT6gNmix/sb8NbR+/9jqUsXE5Yuz4FyxYt4BXeZncddoUzyra+ZL4LAAZbIejmiIIjbGJTnWkHAB0s0aHmJVSKsnoZZOA++xrFim7+TodHaUr1uetmLGtNR24pNockwi1rmUAFwvVdZPTdePRZJUoHlRDtHvK9DGt2zM3Gp+ymR3HM/4AOZQXgv9yChrf4S/q690JrB920L4h6b0NKCuwV590B4iL6E7U= X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2016 18:55:16.3564 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0746 Cc: u-boot@lists.denx.de, Breno Lima , fabio.estevam@nxp.com, francesco.montefoschi@udoo.org, francesco.monte@gmail.com, brenomatheus@gmail.com Subject: [U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi : https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/udoo/neo/Kconfig | 12 ++ board/udoo/neo/MAINTAINERS | 7 + board/udoo/neo/Makefile | 6 + board/udoo/neo/neo.c | 441 +++++++++++++++++++++++++++++++++++++++++ configs/udoo_neo_defconfig | 30 +++ include/configs/udoo_neo.h | 94 +++++++++ 7 files changed, 595 insertions(+) create mode 100644 board/udoo/neo/Kconfig create mode 100644 board/udoo/neo/MAINTAINERS create mode 100644 board/udoo/neo/Makefile create mode 100644 board/udoo/neo/neo.c create mode 100644 configs/udoo_neo_defconfig create mode 100644 include/configs/udoo_neo.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..ea8b693 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -192,6 +192,10 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL +config TARGET_UDOO_NEO + bool "UDOO Neo" + select SUPPORT_SPL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -253,6 +257,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig new file mode 100644 index 0000000..8f474df --- /dev/null +++ b/board/udoo/neo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO_NEO + +config SYS_VENDOR + default "udoo" + +config SYS_BOARD + default "neo" + +config SYS_CONFIG_NAME + default "udoo_neo" + +endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS new file mode 100644 index 0000000..743fe33 --- /dev/null +++ b/board/udoo/neo/MAINTAINERS @@ -0,0 +1,7 @@ +UDOO NEO BOARD +M: Breno Lima +M: Francesco Montefoschi +S: Maintained +F: board/udoo/neo/ +F: include/configs/udoo_neo.h +F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile new file mode 100644 index 0000000..150cbc1 --- /dev/null +++ b/board/udoo/neo/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 UDOO Team +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c new file mode 100644 index 0000000..7f17469 --- /dev/null +++ b/board/udoo/neo/neo.c @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) Jasbir Matharu + * Copyright (C) UDOO Team + * + * Author: Breno Lima + * Author: Francesco Montefoschi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + UDOO_NEO_TYPE_BASIC, + UDOO_NEO_TYPE_BASIC_KS, + UDOO_NEO_TYPE_FULL, + UDOO_NEO_TYPE_EXTENDED, +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ + MUX_MODE_SION) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD pin */ + MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const board_recognition_pads[] = { + /*Connected to R184*/ + MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, + /*Connected to R185*/ + MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + /* Configured for WLAN */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static int get_board_value(void) +{ + int r184, r185; + + imx_iomux_v3_setup_multiple_pads(board_recognition_pads, + ARRAY_SIZE(board_recognition_pads)); + + gpio_direction_input(IMX_GPIO_NR(4, 13)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); + r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); + + /* + * Machine selection - + * Machine r184, r185 + * --------------------------------- + * Basic 0 0 + * Basic Ks 0 1 + * Full 1 0 + * Extended 1 1 + */ + + return (r184 << 1) + r185; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) +#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\ + (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning:\ + failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +char *board_string(void) +{ + switch (get_board_value()) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + +int checkboard(void) +{ + printf("Board: UDOO Neo %s\n", board_string()); + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", board_string()); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#include +#include + +static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration neo_mmcd_calib = { + .p0_mpwldectrl0 = 0x000E000B, + .p0_mpwldectrl1 = 0x000E0010, + .p0_mpdgctrl0 = 0x41600158, + .p0_mpdgctrl1 = 0x01500140, + .p0_mprddlctl = 0x3A383E3E, + .p0_mpwrdlctl = 0x3A383C38, +}; + +static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { + .p0_mpwldectrl0 = 0x001E0022, + .p0_mpwldectrl1 = 0x001C0019, + .p0_mpdgctrl0 = 0x41540150, + .p0_mpdgctrl1 = 0x01440138, + .p0_mprddlctl = 0x403E4644, + .p0_mpwrdlctl = 0x3C3A4038, +}; + +/* MT41K256M16 */ +static struct mx6_ddr3_cfg neo_mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16 */ +static struct mx6_ddr3_cfg neo_basic_mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + int board = get_board_value(); + + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 1, /* width of data bus: 1 = 32 bits */ + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) + mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, + &neo_basic_mem_ddr); + else + mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig new file mode 100644 index 0000000..3304afb --- /dev/null +++ b/configs/udoo_neo_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_UDOO_NEO=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h new file mode 100644 index 0000000..81e0481 --- /dev/null +++ b/include/configs/udoo_neo.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_UART + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ + +/* Linux only */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "mmcautodetect=no\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdt_file = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#endif /* __CONFIG_H */