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[U-Boot,RFC,2/9] mx6memcal: zero values for MPWRDLCTL cause read DQS calibration errors

Message ID 1478031230-7263-3-git-send-email-eric@nelint.com
State RFC
Delegated to: Stefano Babic
Headers show

Commit Message

Eric Nelson Nov. 1, 2016, 8:13 p.m. UTC 
Signed-off-by: Eric Nelson <eric@nelint.com>
---
 board/freescale/mx6memcal/spl.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c
index 90e240f..4e63e34 100644
--- a/board/freescale/mx6memcal/spl.c
+++ b/board/freescale/mx6memcal/spl.c
@@ -400,6 +400,10 @@  void board_init_f(ulong dummy)
 
 	memset((void *)gd, 0, sizeof(struct global_data));
 
+	/* write leveling calibration defaults */
+	calibration.p0_mpwrdlctl = 0x40404040;
+	calibration.p1_mpwrdlctl = 0x40404040;
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();