From patchwork Sun Oct 30 19:20:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 689032 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t6S7C6bqNz9t15 for ; Mon, 31 Oct 2016 06:22:31 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E49A4B99D; Sun, 30 Oct 2016 20:22:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ENNhiJU8Q2TF; Sun, 30 Oct 2016 20:22:29 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8F5F14B71E; Sun, 30 Oct 2016 20:22:28 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F01BA4B71E for ; Sun, 30 Oct 2016 20:22:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZoHWPbqj8kTN for ; Sun, 30 Oct 2016 20:22:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fed1rmfepo202.cox.net (fed1rmfepo202.cox.net [68.230.241.147]) by theia.denx.de (Postfix) with ESMTP id 3FB174B68A for ; Sun, 30 Oct 2016 20:22:20 +0100 (CET) Received: from fed1rmimpo209.cox.net ([68.230.241.160]) by fed1rmfepo202.cox.net (InterMail vM.8.01.05.28 201-2260-151-171-20160122) with ESMTP id <20161030192219.NCTD3827.fed1rmfepo202.cox.net@fed1rmimpo209.cox.net> for ; Sun, 30 Oct 2016 15:22:19 -0400 Received: from localhost.localdomain ([98.165.102.90]) by fed1rmimpo209.cox.net with cox id 1vNJ1u0091x1f0q01vNJbf; Sun, 30 Oct 2016 15:22:18 -0400 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A090203.5816486B.000D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=2.1 cv=cKFAygqN c=1 sm=1 tr=0 a=i7nT0dqFxmwB8XGI+JTv/g==:117 a=i7nT0dqFxmwB8XGI+JTv/g==:17 a=L9H7d07YOLsA:10 a=9cW_t1CCXrUA:10 a=s5jvgZ67dGcA:10 a=9_1hYV8uAAAA:8 a=qHPe0rPGWA6c0KuuskkA:9 a=FKwbt-OhbrkoYuZlCyy7:22 X-CM-Score: 0.00 Authentication-Results: cox.net; auth=pass (CRAM-MD5) smtp.auth=eric.a.nelson@cox.net From: Eric Nelson To: u-boot@lists.denx.de Date: Sun, 30 Oct 2016 12:20:17 -0700 Message-Id: <1477855217-8046-1-git-send-email-eric@nelint.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477847942-20347-4-git-send-email-eric@nelint.com> References: <1477847942-20347-4-git-send-email-eric@nelint.com> Cc: marex@denx.de, albert.aribaud@3adev.fr, fabio.estevam@nxp.com Subject: [U-Boot] [PATCH] ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson --- arch/arm/cpu/armv7/mx6/Kconfig | 5 +++++ arch/arm/cpu/armv7/mx6/ddr.c | 3 +-- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +- configs/novena_defconfig | 1 + 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..32536c0 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -35,6 +35,11 @@ config MX6ULL bool select MX6UL +config MX6_DDRCAL + bool "Include dynamic DDR calibration routines" + depends on SPL + default n + choice prompt "MX6 board select" optional diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index b12fb64..0cf391e 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -14,8 +14,7 @@ #include #include -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) - +#if defined(CONFIG_MX6_DDRCAL) static void reset_read_data_fifos(void) { struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 12454fa..2a8d443 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -458,7 +458,7 @@ void mx6sl_dram_iocfg(unsigned width, const struct mx6sl_iomux_ddr_regs *, const struct mx6sl_iomux_grp_regs *); -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#if defined(CONFIG_MX6_DDRCAL) int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo); int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo); void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo, diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 1ffdddc..9d47d5b 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_KOSAGI_NOVENA=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y