From patchwork Sun Oct 30 18:23:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 689023 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t6Qvz1sxjz9t0H for ; Mon, 31 Oct 2016 05:27:43 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA0B5B385E; Sun, 30 Oct 2016 19:26:38 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SuOPklKAjGsz; Sun, 30 Oct 2016 19:26:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 35F4FB383F; Sun, 30 Oct 2016 19:26:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 01472B3838 for ; Sun, 30 Oct 2016 19:26:05 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3DCdDdBTDKMw for ; Sun, 30 Oct 2016 19:26:04 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by theia.denx.de (Postfix) with ESMTPS id ACB91A7600 for ; Sun, 30 Oct 2016 19:25:39 +0100 (CET) Received: by mail-pf0-f195.google.com with SMTP id a136so3260089pfa.0 for ; Sun, 30 Oct 2016 11:25:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MUeSAHyR3EBjFEX7A9TjSLnFEC/V/xcE4jdeq1T+O9I=; b=b8Se/DAMjc1y4yYCoD8Lr7//YseaDAJwMiJdfBYA+HCmjxivvbsYgwyr/ga9T4tD5/ A59dxMevaJAWY3YqN3dnbezzS8KeeA+xiIu/okux7Rr0K5aeSMlV4AhMdGNQakTSC5KH MhatYNC+IqxAhiPkUTcC5e2Sc9s5i6ivG+80I1yHlAWwoqUiPmyEL1QF+Db/GSmNa+48 4bE/3P6pEV+1c0EK6N1UTjjZ+dyO22G2UawQruOq/R3CcG8qzOFG615Y4Xn4b3zK93Tk MjwDBDuMF+/AM4bmf8I5QMbNQzYTf68LrXAEpf2K7vLv26kBEkh6ZN00lp68QKezu5nO UF3A== X-Gm-Message-State: ABUngvcL2usiLxuwUf9ipSnnWIoVKmdyDZ+nPlBIN+cdqs79ZQdmAE62Q/8sigkfmx9QHA== X-Received: by 10.98.79.27 with SMTP id d27mr42674396pfb.165.1477851937852; Sun, 30 Oct 2016 11:25:37 -0700 (PDT) Received: from Mr.J ([49.204.230.134]) by smtp.gmail.com with ESMTPSA id k7sm31357901pan.8.2016.10.30.11.25.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 30 Oct 2016 11:25:36 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Sun, 30 Oct 2016 23:53:48 +0530 Message-Id: <1477851833-23960-17-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477851833-23960-1-git-send-email-jagan@openedev.com> References: <1477851833-23960-1-git-send-email-jagan@openedev.com> Cc: Tom Rini , Stefan Roese , Jagan Teki Subject: [U-Boot] [PATCH v9 16/21] mtd: spi-nor: Add 4-byte addresswidth support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add 4-byte address supports, so-that SPI-NOR chips has > 16MiB should accessible. Signed-off-by: Jagan Teki --- drivers/mtd/spi-nor/m25p80.c | 1 + drivers/mtd/spi-nor/spi-nor.c | 36 ++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 6 +++++- 3 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c index 740d3f6..285fae5 100644 --- a/drivers/mtd/spi-nor/m25p80.c +++ b/drivers/mtd/spi-nor/m25p80.c @@ -31,6 +31,7 @@ static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd) cmd[1] = addr >> (nor->addr_width * 8 - 8); cmd[2] = addr >> (nor->addr_width * 8 - 16); cmd[3] = addr >> (nor->addr_width * 8 - 24); + cmd[4] = addr >> (nor->addr_width * 8 - 32); } static int m25p_cmdsz(struct spi_nor *nor) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 12e7cfe..103b68b 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -378,6 +378,36 @@ static int sst_write_bp(struct udevice *dev, loff_t to, size_t len, } #endif +/* Enable/disable 4-byte addressing mode. */ +static int set_4byte(struct spi_nor *nor, const struct spi_nor_info *info, + int enable) +{ + int status; + bool need_wren = false; + u8 cmd; + + switch (JEDEC_MFR(info)) { + case SNOR_MFR_MICRON: + /* Some Micron need WREN command; all will accept it */ + need_wren = true; + case SNOR_MFR_MACRONIX: + case SNOR_MFR_WINBOND: + if (need_wren) + write_enable(nor); + + cmd = enable ? SNOR_OP_EN4B : SNOR_OP_EX4B; + status = nor->write_reg(nor, cmd, NULL, 0); + if (need_wren) + write_disable(nor); + + return status; + default: + /* Spansion style */ + nor->cmd_buf[0] = enable << 7; + return nor->write_reg(nor, SNOR_OP_BRWR, nor->cmd_buf, 1); + } +} + #ifdef CONFIG_SPI_NOR_MACRONIX static int macronix_quad_enable(struct spi_nor *nor) { @@ -613,6 +643,12 @@ int spi_nor_scan(struct udevice *dev) } nor->addr_width = 3; + if (mtd->size > SNOR_16MB_BOUN) { + nor->addr_width = 4; + ret = set_4byte(nor, info, true); + if (ret) + return ret; + } /* Dummy cycles for read */ switch (nor->read_opcode) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4e5b3ba..ad573db 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -62,6 +62,10 @@ #define SNOR_OP_BP 0x02 /* Byte program */ #define SNOR_OP_AAI_WP 0xad /* Auto addr increment word program */ +/* Used for Macronix and Winbond flashes. */ +#define SNOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SNOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ + /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ #define SR_WEL BIT(1) /* Write enable latch */ @@ -83,7 +87,7 @@ /* Flash timeout values */ #define SNOR_READY_WAIT_PROG (2 * CONFIG_SYS_HZ) #define SNOR_READY_WAIT_ERASE (5 * CONFIG_SYS_HZ) -#define SNOR_MAX_CMD_SIZE 4 +#define SNOR_MAX_CMD_SIZE 6 #define SNOR_16MB_BOUN 0x1000000 enum snor_option_flags {