From patchwork Sun Oct 30 17:46:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 688997 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t6Q445MK4z9s9N for ; Mon, 31 Oct 2016 04:49:40 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A2BAFA75BC; Sun, 30 Oct 2016 18:48:48 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1G_rfXKbxGZF; Sun, 30 Oct 2016 18:48:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9EB85B3824; Sun, 30 Oct 2016 18:48:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B10DA75FD for ; Sun, 30 Oct 2016 18:48:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cCXLK41gVK-H for ; Sun, 30 Oct 2016 18:48:02 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by theia.denx.de (Postfix) with ESMTPS id C4D2FA75CC for ; Sun, 30 Oct 2016 18:47:50 +0100 (CET) Received: by mail-pf0-f196.google.com with SMTP id n85so6594857pfi.3 for ; Sun, 30 Oct 2016 10:47:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h3g3wGjwpMo2ifWHuGCaMagi03WnwIga1TfSF9wBt6I=; b=ZAmbYpCa0QJadv9NrJEl5t4ehpPqwnt96dcJcmIQ9zM/iFGvCRVbl75tDaATIEG56L AoF11yAfy2PZwPYyHrKgPad7f+l+mLFPjfIX6DFzk/oo5MwXa5LjGioi6H2hASoHk+86 5vDOkv8y0PhsAW3sOaCZMokTDwtJrh6ljqIYt/mSdlYwszKilx/we5WvM58giBZbPVlO yxAl5Wsj8QLCDQD9Z0lvVOC76REP4aglLcTEgzDNKkLPnz3kiDk+TauDHiFHdhERtIcx NpS3UspTunSXMFAgRt9GaO66iiSsSeK5EXEx7Gm4dmyJfJk8vphr0cAi6ApbJkh/ppvI n/2w== X-Gm-Message-State: ABUngvdE93QSj0aW+8kEYCcMJNq2k2H3XE8mzBKCINTHxec+toE22UBXDD+FyGEQsJ5w/g== X-Received: by 10.99.192.69 with SMTP id z5mr30608496pgi.169.1477849669326; Sun, 30 Oct 2016 10:47:49 -0700 (PDT) Received: from Mr.J ([49.204.230.134]) by smtp.gmail.com with ESMTPSA id s7sm4138882pfg.32.2016.10.30.10.47.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 30 Oct 2016 10:47:48 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Sun, 30 Oct 2016 23:16:22 +0530 Message-Id: <1477849590-11954-14-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477849590-11954-1-git-send-email-jagan@openedev.com> References: <1477849590-11954-1-git-send-email-jagan@openedev.com> Cc: Michal Simek , Siva Durga Prasad Paladugu , Jagan Teki Subject: [U-Boot] [PATCH v5 13/21] sf: Rename sf_params.c to spi_flash_ids X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" spi_flash_ids.c is more meaningful name as the flash_info table structure spi_flash_info has spi_flash_ids instance. Cc: Simon Glass Cc: Bin Meng Cc: York Sun Cc: Vignesh R Cc: Mugunthan V N Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki --- drivers/mtd/spi/Makefile | 2 +- drivers/mtd/spi/spi_flash_ids.c | 176 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/spi/spi_flash_ids.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index f3dc409..fcda023 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif -obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o +obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c new file mode 100644 index 0000000..3648608 --- /dev/null +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -0,0 +1,176 @@ +/* + * SPI Flash ID's. + * + * Copyright (C) 2016 Jagan Teki + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "sf_internal.h" + +/* Used when the "_ext_id" is two bytes at most */ +#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .id = { \ + ((_jedec_id) >> 16) & 0xff, \ + ((_jedec_id) >> 8) & 0xff, \ + (_jedec_id) & 0xff, \ + ((_ext_id) >> 8) & 0xff, \ + (_ext_id) & 0xff, \ + }, \ + .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ + .sector_size = (_sector_size), \ + .n_sectors = (_n_sectors), \ + .page_size = 256, \ + .flags = (_flags), + +#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .id = { \ + ((_jedec_id) >> 16) & 0xff, \ + ((_jedec_id) >> 8) & 0xff, \ + (_jedec_id) & 0xff, \ + ((_ext_id) >> 16) & 0xff, \ + ((_ext_id) >> 8) & 0xff, \ + (_ext_id) & 0xff, \ + }, \ + .id_len = 6, \ + .sector_size = (_sector_size), \ + .n_sectors = (_n_sectors), \ + .page_size = 256, \ + .flags = (_flags), + +const struct spi_flash_info spi_flash_ids[] = { +#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ + {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, + {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, + {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, + {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, + {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, + {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, + {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT25DF321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, + {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, +#endif +#ifdef CONFIG_SPI_FLASH_EON /* EON */ + {"EN25Q32B", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, + {"EN25Q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"EN25Q128B", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, + {"EN25S64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, +#endif +#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"GD25Q64B", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"GD25LQ32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, +#endif +#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ + {"IS25LP032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {"IS25LP064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {"IS25LP128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, +#endif +#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ + {"MX25L2006E", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, + {"MX25L4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, + {"MX25L8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, + {"MX25L1605D", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, + {"MX25L3205D", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, + {"MX25L6405D", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, + {"MX25L12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"MX25L25635F", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {"MX25L51235F", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {"MX25L12855E", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, +#endif +#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ + {"S25FL008A", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, + {"S25FL016A", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, + {"S25FL032A", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, + {"S25FL064A", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, + {"S25FL116K", INFO(0x014015, 0x0, 64 * 1024, 128, 0) }, + {"S25FL164K", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, + {"S25FL128P_256K", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL128P_64K", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL032P", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL064P", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {"S25FL128S_64K", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, + {"S25FL256S_64K", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {"S25FS256S_64K", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"S25FS512S", INFO(0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP) }, + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {"S25FL512S_64K", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {"S25FL512S_512K", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ + {"M25P10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, + {"M25P20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, + {"M25P40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, + {"M25P80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, + {"M25P16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, + {"M25PE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, + {"M25PX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, + {"M25P32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, + {"M25P64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, + {"M25P128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, + {"M25PX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, + {"N25Q016A", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, + {"N25Q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q32A", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q64A", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"N25Q128A", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"N25Q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q256A", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"N25Q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q512A", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"N25Q1024A", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, +#endif +#ifdef CONFIG_SPI_FLASH_SST /* SST */ + {"SST25VF040B", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {"SST25VF080B", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {"SST25VF016B", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, + {"SST25VF032B", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, + {"SST25VF064C", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, + {"SST25WF512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, + {"SST25WF010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, + {"SST25WF020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, + {"SST25WF040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {"SST25WF040B", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, + {"SST25WF080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, +#endif +#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ + {"W25P80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, + {"W25P16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, + {"W25P32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, + {"W25X40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, + {"W25X16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, + {"W25X32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, + {"W25X64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"W25Q80BL", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q16CL", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q32BV", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q64CV", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q128BV", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q80BW", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q16DW", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q32DW", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q64DW", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {"W25Q128FW", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, +#endif + {}, /* Empty entry to terminate the list */ + /* + * Note: + * Below paired flash devices has similar spi_flash params. + * (S25FL129P_64K, S25FL128S_64K) + * (W25Q80BL, W25Q80BV) + * (W25Q16CL, W25Q16DV) + * (W25Q32BV, W25Q32FV_SPI) + * (W25Q64CV, W25Q64FV_SPI) + * (W25Q128BV, W25Q128FV_SPI) + * (W25Q32DW, W25Q32FV_QPI) + * (W25Q64DW, W25Q64FV_QPI) + * (W25Q128FW, W25Q128FV_QPI) + */ +};