From patchwork Sun Oct 30 17:19:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 688979 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t6PRY0LbXz9t1b for ; Mon, 31 Oct 2016 04:21:27 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A7B44B98B; Sun, 30 Oct 2016 18:21:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ti4Va7bIocii; Sun, 30 Oct 2016 18:21:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 008DE4B71E; Sun, 30 Oct 2016 18:21:24 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BACB54B98A for ; Sun, 30 Oct 2016 18:21:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qmrogho1w4fy for ; Sun, 30 Oct 2016 18:21:21 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fed1rmfepo103.cox.net (fed1rmfepo103.cox.net [68.230.241.145]) by theia.denx.de (Postfix) with ESMTP id 0B83A4B68A for ; Sun, 30 Oct 2016 18:21:17 +0100 (CET) Received: from fed1rmimpo210.cox.net ([68.230.241.161]) by fed1rmfepo103.cox.net (InterMail vM.8.01.05.28 201-2260-151-171-20160122) with ESMTP id <20161030172115.NUXS4001.fed1rmfepo103.cox.net@fed1rmimpo210.cox.net> for ; Sun, 30 Oct 2016 13:21:15 -0400 Received: from localhost.localdomain ([98.165.102.90]) by fed1rmimpo210.cox.net with cox id 1tME1u0011x1f0q01tMFey; Sun, 30 Oct 2016 13:21:15 -0400 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A090203.58162C0B.0053, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=2.1 cv=T9osN6+Q c=1 sm=1 tr=0 a=i7nT0dqFxmwB8XGI+JTv/g==:117 a=i7nT0dqFxmwB8XGI+JTv/g==:17 a=L9H7d07YOLsA:10 a=9cW_t1CCXrUA:10 a=s5jvgZ67dGcA:10 a=9_1hYV8uAAAA:8 a=Ici1tZE1IR7V1p13Z_QA:9 a=FKwbt-OhbrkoYuZlCyy7:22 X-CM-Score: 0.00 Authentication-Results: cox.net; auth=pass (CRAM-MD5) smtp.auth=eric.a.nelson@cox.net From: Eric Nelson To: u-boot@lists.denx.de Date: Sun, 30 Oct 2016 10:19:00 -0700 Message-Id: <1477847942-20347-2-git-send-email-eric@nelint.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477847942-20347-1-git-send-email-eric@nelint.com> References: <1477847942-20347-1-git-send-email-eric@nelint.com> Cc: marex@denx.de, albert.u.boot@aribaud.net, fabio.estevam@nxp.com Subject: [U-Boot] [PATCH 1/3] mx6: ddr: allow 32 cycles for DQS gating calibration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson Reviewed-by: Marek Vasut --- arch/arm/cpu/armv7/mx6/ddr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 7beb7ea..b15f376 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -347,6 +347,8 @@ int mmdc_do_dqs_calibration(void) * 16 before comparing read data. */ setbits_le32(&mmdc0->mpdgctrl0, 1 << 30); + if (sysinfo->dsize == 2) + setbits_le32(&mmdc1->mpdgctrl0, 1 << 30); /* Set bit 28 to start automatic read DQS gating calibration */ setbits_le32(&mmdc0->mpdgctrl0, 5 << 28); @@ -365,6 +367,11 @@ int mmdc_do_dqs_calibration(void) if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000)) errors |= 2; + /* now disable mpdgctrl0[DG_CMP_CYC] */ + clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30); + if (sysinfo->dsize == 2) + clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30); + /* * DQS gating absolute offset should be modified from * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to