From patchwork Fri Oct 28 16:19:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 688515 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t58Qj59Hhz9s65 for ; Sat, 29 Oct 2016 03:31:24 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DC2714BA81; Fri, 28 Oct 2016 18:31:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PI-B1JsxrXqa; Fri, 28 Oct 2016 18:31:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D661C4B71E; Fri, 28 Oct 2016 18:31:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 96DBC4B71E for ; Fri, 28 Oct 2016 18:30:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 12Exttt8ql7t for ; Fri, 28 Oct 2016 18:30:48 +0200 (CEST) X-Greylist: delayed 567 seconds by postgrey-1.34 at theia; Fri, 28 Oct 2016 18:30:40 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fed1rmfepi207.cox.net (fed1rmfepi207.cox.net [68.230.241.152]) by theia.denx.de (Postfix) with ESMTP id 115334B656 for ; Fri, 28 Oct 2016 18:30:39 +0200 (CEST) Received: from fed1rmimpo209.cox.net ([68.230.241.160]) by fed1rmfepo103.cox.net (InterMail vM.8.01.05.28 201-2260-151-171-20160122) with ESMTP id <20161028162112.MNWS4001.fed1rmfepo103.cox.net@fed1rmimpo209.cox.net> for ; Fri, 28 Oct 2016 12:21:12 -0400 Received: from localhost.localdomain ([98.165.102.90]) by fed1rmimpo209.cox.net with cox id 14MB1u0011x1f0q014MBxg; Fri, 28 Oct 2016 12:21:11 -0400 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A090206.58137AF8.0046, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=2.1 cv=cKFAygqN c=1 sm=1 tr=0 a=i7nT0dqFxmwB8XGI+JTv/g==:117 a=i7nT0dqFxmwB8XGI+JTv/g==:17 a=L9H7d07YOLsA:10 a=9cW_t1CCXrUA:10 a=s5jvgZ67dGcA:10 a=9_1hYV8uAAAA:8 a=wZcdMnwd9BOAPKHhMkIA:9 a=FKwbt-OhbrkoYuZlCyy7:22 X-CM-Score: 0.00 Authentication-Results: cox.net; auth=pass (CRAM-MD5) smtp.auth=eric.a.nelson@cox.net From: Eric Nelson To: u-boot@lists.denx.de Date: Fri, 28 Oct 2016 09:19:09 -0700 Message-Id: <1477671549-32552-1-git-send-email-eric@nelint.com> X-Mailer: git-send-email 2.7.4 Cc: albert.u.boot@aribaud.net Subject: [U-Boot] [PATCH 01/13] imx: mx6sl: ddr: add IOM_GRP registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add IOM_GRP register definitions for i.MX6SL to allow them to be named in DDR configuration (.cfg) files. Signed-off-by: Eric Nelson --- arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h index c3c4d69..98a259e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h @@ -42,4 +42,17 @@ #define MX6_IOM_DRAM_SDWE_B 0x020e0354 +#define MX6_IOM_GRP_ADDDS 0x020e05ac +#define MX6_IOM_GRP_DDRMODE_CTL 0x020e05b0 +#define MX6_IOM_GRP_DDRPKE 0x020e05b4 +#define MX6_IOM_GRP_DDRPK 0x020e05b8 +#define MX6_IOM_GRP_DDRHYS 0x020e05bc +#define MX6_IOM_GRP_DDRMODE 0x020e05c0 +#define MX6_IOM_GRP_B0DS 0x020e05c4 +#define MX6_IOM_GRP_CTLDS 0x020e05c8 +#define MX6_IOM_GRP_B1DS 0x020e05cc +#define MX6_IOM_GRP_DDR_TYPE 0x020e05d0 +#define MX6_IOM_GRP_B2DS 0x020e05d4 +#define MX6_IOM_GRP_B3DS 0x020e05d8 + #endif /*__ASM_ARCH_MX6SL_DDR_H__ */