From patchwork Fri Oct 28 13:57:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 688408 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t552m1PkTz9t0H for ; Sat, 29 Oct 2016 00:58:56 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A1A4BA75AB; Fri, 28 Oct 2016 15:58:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sWLvsi5_Srlo; Fri, 28 Oct 2016 15:58:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9817EA7594; Fri, 28 Oct 2016 15:58:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27DA1A759A for ; Fri, 28 Oct 2016 15:58:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8ZyJH3_n_3JX for ; Fri, 28 Oct 2016 15:58:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by theia.denx.de (Postfix) with ESMTPS id 1022BA752D for ; Fri, 28 Oct 2016 15:58:39 +0200 (CEST) Received: by mail-pf0-f194.google.com with SMTP id n85so1379889pfi.3 for ; Fri, 28 Oct 2016 06:58:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VRA34innUdUKAXrWOwm+e7dwpZQcqbkWVtvssWo0RKM=; b=l4p3XSax7vuepf9biw710VWYb8tQB6q2akuY9LCYkZcAx36oW77PHo5tCvOGLLZW5/ I6dSxK0dbAWOAAg9fWOwp7ZWaPLZi/DYEKtC4SG7vDzDusabAy3uKq9vd+YxAqcfeN69 qycfDeugJdTkSDXED/ZaETAtaPCTUMF/ll7kEMep5kuN2ezm9ICeJCrUT5bUhuSSc9ku 5KbgSVZBnvxzmZurUUF4kG17wHdS03onanpgkA3zcDatlzzoPBmHO7b1kgLGJyTLebIN 1nvsD2G812NX4Zu4IBZUMQbmUBCZ8DjI/hsCKqExaWf0XASk9u3+yUbpB2GtJsEBfXST zjhw== X-Gm-Message-State: ABUngvfGeiIf4tARcHBZe9ZfAs5O+bdpe6uMxnVk8biyjn8WY5H3QmKNbH5TFstz41pQLA== X-Received: by 10.99.170.13 with SMTP id e13mr20765484pgf.68.1477663118369; Fri, 28 Oct 2016 06:58:38 -0700 (PDT) Received: from Mr.J ([49.204.230.134]) by smtp.gmail.com with ESMTPSA id l187sm19357417pfc.0.2016.10.28.06.58.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Oct 2016 06:58:37 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Fri, 28 Oct 2016 19:27:42 +0530 Message-Id: <1477663067-20911-3-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477663067-20911-1-git-send-email-jagan@openedev.com> References: <1477663067-20911-1-git-send-email-jagan@openedev.com> Cc: u-boot@lists.denx.de, Matteo Lisi Subject: [U-Boot] [PATCH v2 2/7] imx6: icorem6: Add framebuffer support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board. Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- board/engicam/icorem6/icorem6.c | 113 +++++++++++++++++++++++++++++++++++ configs/imx6qdl_icore_mmc_defconfig | 2 + configs/imx6qdl_icore_nand_defconfig | 2 + include/configs/imx6qdl_icore.h | 12 ++++ 4 files changed, 129 insertions(+) diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 587775e..3b25757 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -90,6 +91,113 @@ static void setup_gpmi_nand(void) } #endif +#if defined(CONFIG_VIDEO) +static iomux_v3_cfg_t const rgb_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), +}; + +static void enable_rgb(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(rgb_pads); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "Amp-WD", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30000, + .left_margin = 30, + .right_margin = 30, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 64, + .vsync_len = 20, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO */ + int board_early_init_f(void) { SETUP_IOMUX_PADS(uart4_pads); @@ -105,6 +213,11 @@ int board_init(void) #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif + +#ifdef CONFIG_VIDEO + setup_display(); +#endif + return 0; } diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 31f40b4..e530fad 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -33,6 +33,8 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 3410e4c..e50b4c4 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -29,6 +29,8 @@ CONFIG_IMX_THERMAL=y # CONFIG_DM_MMC_OPS is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index f8a1263..e2b286c 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -149,6 +149,18 @@ # define CONFIG_PHY_SMSC #endif +/* Framebuffer */ +#ifdef CONFIG_VIDEO +# define CONFIG_IPUV3_CLK 260000000 +# define CONFIG_IMX_VIDEO_SKIP + +# define CONFIG_SPLASH_SCREEN +# define CONFIG_BMP_16BPP +# define CONFIG_VIDEO_BMP_RLE8 +# define CONFIG_VIDEO_LOGO +# define CONFIG_VIDEO_BMP_LOGO +#endif + /* SPL */ #ifdef CONFIG_SPL # ifdef CONFIG_NAND_MXS