From patchwork Mon Oct 24 11:57:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 685780 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t2ZbT3WJ7z9t0Z for ; Mon, 24 Oct 2016 23:00:05 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 88EE6A761E; Mon, 24 Oct 2016 13:59:57 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IYzjRmXY9t4u; Mon, 24 Oct 2016 13:59:57 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 153E1A7574; Mon, 24 Oct 2016 13:59:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DDD7AA7574 for ; Mon, 24 Oct 2016 13:59:53 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sCFUXK8zzMzV for ; Mon, 24 Oct 2016 13:59:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by theia.denx.de (Postfix) with ESMTPS id 3FD8AA7537 for ; Mon, 24 Oct 2016 13:59:51 +0200 (CEST) Received: by mail-pf0-f193.google.com with SMTP id r16so16419424pfg.3 for ; Mon, 24 Oct 2016 04:59:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PTbkWzNv74ZC0WFj9ZZOtxyehMw1NA9x1v8oalab65Q=; b=FaJ3R2wk5CYrVwrLh1sijji8frjMXPkapNAdSkQfBh+EnC3J3knRdH/gR36f/HFtao fBaqRWBzXtL/Sllp6icsMv6uW/6DRTpCzgaTP/R+pWfx13e0eglORyviveKcqekEy8+V Q9pY2zIUBPlfDy3H1HVJL5UtuWkGXUAciBfdXUlDh2gclG4VChaAV34J0Ens9mxJ1lPt zBRMTsYrcUqDNeu6g5GDKB2tMhYdh2iSAbtnJ7zQy8CrZMstUigVMC+poOC+187ZYy/j AAl6jvG9tfM/i2DSeE3MPcNoZoi9aP1hv2Uk05zgDq7E1VSxCDdhhmp1j5tBCSx144uW 07ig== X-Gm-Message-State: ABUngvcMa7ZUzjD/o/SrcEP/oFKa7EzthHFeKkV1Cnqd3DU/wJ4BC10WahOMclYujd1aQA== X-Received: by 10.98.157.218 with SMTP id a87mr28346538pfk.1.1477310390335; Mon, 24 Oct 2016 04:59:50 -0700 (PDT) Received: from Mr.J ([106.220.97.179]) by smtp.gmail.com with ESMTPSA id fi6sm25032538pac.20.2016.10.24.04.59.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 24 Oct 2016 04:59:49 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Mon, 24 Oct 2016 17:27:27 +0530 Message-Id: <1477310262-17841-9-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477310262-17841-1-git-send-email-jteki@openedev.com> References: <1477310262-17841-1-git-send-email-jteki@openedev.com> Cc: Matteo Lisi , u-boot@lists.denx.de, Fabio Estevam Subject: [U-Boot] [PATCH v8 08/23] arm: dts: Add devicetree for i.MX6DL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add i.MX6DL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/dts/imx6dl.dtsi | 133 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/arm/dts/imx6dl.dtsi diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi new file mode 100644 index 0000000..9a4c22c --- /dev/null +++ b/arch/arm/dts/imx6dl.dtsi @@ -0,0 +1,133 @@ + +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include "imx6dl-pinfunc.h" +#include "imx6qdl.dtsi" + +/ { + aliases { + i2c3 = &i2c4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + soc { + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + aips1: aips-bus@02000000 { + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6dl-iomuxc"; + }; + + pxp: pxp@020f0000 { + reg = <0x020f0000 0x4000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + epdc: epdc@020f4000 { + reg = <0x020f4000 0x4000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + }; + + lcdif: lcdif@020f8000 { + reg = <0x020f8000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + aips2: aips-bus@02100000 { + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6DL_CLK_I2C4>; + status = "disabled"; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>; + }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>; + }; +}; + +&gpt { + compatible = "fsl,imx6dl-gpt"; +}; + +&hdmi { + compatible = "fsl,imx6dl-hdmi"; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; +}; + +&vpu { + compatible = "fsl,imx6dl-vpu", "cnm,coda960"; +};