From patchwork Mon Oct 24 11:57:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 685788 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t2Zf401y4z9t0Z for ; Mon, 24 Oct 2016 23:02:20 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A41D6A7661; Mon, 24 Oct 2016 14:01:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J8EvB8cCvf6a; Mon, 24 Oct 2016 14:01:29 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 40768B3849; Mon, 24 Oct 2016 14:01:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C3B46B3854 for ; Mon, 24 Oct 2016 14:01:22 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0XINKNqeQr6X for ; Mon, 24 Oct 2016 14:01:22 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by theia.denx.de (Postfix) with ESMTPS id EE1CAA7657 for ; Mon, 24 Oct 2016 14:01:11 +0200 (CEST) Received: by mail-pf0-f195.google.com with SMTP id 128so16460448pfz.1 for ; Mon, 24 Oct 2016 05:01:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G9kjufDOW/dvqumxe6MZamum7gjZMgRohpN2f+Vf86A=; b=VLXn44brOgqOupnvl0A2CSKRaW18CWPdD/dtYG7HJvHzg8+Lq+/OM+usWKIe+YtFBN CkCJozBntzcV6WEkywoc/oP6KwBHwFRn42q/hdo1hx38XBt7R4OcDekwiVuZQkdFpfwd lCs9Uf0yUmuS7u9Lj+xf+xXKWzYEgAjBCcOFl/uCQvuWgOVzA9wEn8XAjJeQcSkDqzxl Uze0gmnC3r+RuDzvMVw8GEJ0/6WJv5NdaN+njZULgsxJnzw7j9QIiiXsx/GvP5jaY5ac tY3jF0qDbYoxy5zXAJS/7G0aPC1tx3MUggWhzYqTcUPjmMSFeyXCHD9Efp/epn6RLfXU XfWg== X-Gm-Message-State: ABUngvfYpsmOLS5KJ4Oi3/bKvQFIORM39SwTeILBcqpQQehOzQw4rG3AU4YP3Jxwj0Q2GQ== X-Received: by 10.98.202.156 with SMTP id y28mr28444489pfk.130.1477310470509; Mon, 24 Oct 2016 05:01:10 -0700 (PDT) Received: from Mr.J ([106.220.97.179]) by smtp.gmail.com with ESMTPSA id fi6sm25032538pac.20.2016.10.24.05.01.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 24 Oct 2016 05:01:09 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Mon, 24 Oct 2016 17:27:35 +0530 Message-Id: <1477310262-17841-17-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477310262-17841-1-git-send-email-jteki@openedev.com> References: <1477310262-17841-1-git-send-email-jteki@openedev.com> Cc: Matteo Lisi , u-boot@lists.denx.de, Fabio Estevam Subject: [U-Boot] [PATCH v8 16/23] engicam: icorem6: Add DM_GPIO, DM_MMC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/cpu/armv7/mx6/Kconfig | 2 + board/engicam/icorem6/icorem6.c | 142 ++++++++++++++++++++-------------------- include/configs/imx6qdl_icore.h | 4 ++ 3 files changed, 78 insertions(+), 70 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index e2431a8..762a581 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -100,6 +100,8 @@ config TARGET_MX6Q_ICORE select MX6QDL select OF_CONTROL select DM + select DM_GPIO + select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index a23cb7e..a370c8b 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -7,8 +7,6 @@ */ #include -#include -#include #include #include @@ -29,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -55,70 +49,6 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ -}; - -#ifdef CONFIG_FSL_ESDHC -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) - -struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc1_pads); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} -#endif - #ifdef CONFIG_FEC_MXC #define ENET_PHY_RST IMX_GPIO_NR(7, 12) static int setup_fec(void) @@ -200,6 +130,78 @@ int dram_init(void) #include #include +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include +#include + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + /* * Driving strength: * 0x30 == 40 Ohm diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index ad4c5f2..6b58447 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -127,6 +127,10 @@ #ifdef CONFIG_SPL # define CONFIG_SPL_MMC_SUPPORT # include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif #endif #endif /* __IMX6QLD_ICORE_CONFIG_H */