diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 8c0927c..23fa609 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -12,18 +12,19 @@
 #include <dm.h>
 #include <malloc.h>
 #include <memalign.h>
+#include <miiphy.h>
 #include <net.h>
 #include <netdev.h>
-#include <miiphy.h>
 #include "fec_mxc.h"
 
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <linux/compiler.h>
 
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/sys_proto.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -80,11 +81,9 @@ static void swap_packet(uint32_t *packet, int length)
 }
 #endif
 
-/*
- * MII-interface related functions
- */
-static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
-		uint8_t regAddr)
+/* MII-interface related functions */
+static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
+		uint8_t regaddr)
 {
 	uint32_t reg;		/* convenient holder for the PHY register */
 	uint32_t phy;		/* convenient holder for the PHY */
@@ -96,15 +95,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
 	 * programming the FEC's MII data register.
 	 */
 	writel(FEC_IEVENT_MII, &eth->ievent);
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
+	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
 
 	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
 			phy | reg, &eth->mii_data);
 
-	/*
-	 * wait for the related interrupt
-	 */
+	/* wait for the related interrupt */
 	start = get_timer(0);
 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
 		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
@@ -113,17 +110,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
 		}
 	}
 
-	/*
-	 * clear mii interrupt bit
-	 */
+	/* clear mii interrupt bit */
 	writel(FEC_IEVENT_MII, &eth->ievent);
 
-	/*
-	 * it's now safe to read the PHY's register
-	 */
+	/* it's now safe to read the PHY's register */
 	val = (unsigned short)readl(&eth->mii_data);
-	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
-			regAddr, val);
+	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
+	      regaddr, val);
 	return val;
 }
 
@@ -154,22 +147,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
 	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
 }
 
-static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
-		uint8_t regAddr, uint16_t data)
+static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
+		uint8_t regaddr, uint16_t data)
 {
 	uint32_t reg;		/* convenient holder for the PHY register */
 	uint32_t phy;		/* convenient holder for the PHY */
 	uint32_t start;
 
-	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
-	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
+	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
 
 	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
 		FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
 
-	/*
-	 * wait for the MII interrupt
-	 */
+	/* wait for the MII interrupt */
 	start = get_timer(0);
 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
 		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
@@ -178,26 +169,24 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
 		}
 	}
 
-	/*
-	 * clear MII interrupt bit
-	 */
+	/* clear MII interrupt bit */
 	writel(FEC_IEVENT_MII, &eth->ievent);
-	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
-			regAddr, data);
+	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
+	      regaddr, data);
 
 	return 0;
 }
 
-static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
-			int regAddr)
+static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
+			int regaddr)
 {
-	return fec_mdio_read(bus->priv, phyAddr, regAddr);
+	return fec_mdio_read(bus->priv, phyaddr, regaddr);
 }
 
-static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
-			 int regAddr, u16 data)
+static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
+			 int regaddr, u16 data)
 {
-	return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
+	return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
 }
 
 #ifndef CONFIG_PHYLIB
@@ -218,14 +207,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
 	udelay(1000);
 
-	/*
-	 * Set the auto-negotiation advertisement register bits
-	 */
+	/* Set the auto-negotiation advertisement register bits */
 	fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
-			LPA_100FULL | LPA_100HALF | LPA_10FULL |
-			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
+		       LPA_100FULL | LPA_100HALF | LPA_10FULL |
+		       LPA_10HALF | PHY_ANLPAR_PSB_802_3);
 	fec_mdio_write(eth, fec->phy_id, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
+		       BMCR_ANENABLE | BMCR_ANRESTART);
 
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
@@ -242,9 +229,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	struct ethernet_regs *eth = fec->bus->priv;
 
-	/*
-	 * Wait for AN completion
-	 */
+	/* Wait for AN completion */
 	start = get_timer(0);
 	do {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
@@ -255,7 +240,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
 		status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
 		if (status < 0) {
 			printf("%s: Autonegotiation failed. status: %d\n",
-					dev->name, status);
+			       dev->name, status);
 			return -1;
 		}
 	} while (!(status & BMSR_LSTATUS));
@@ -352,15 +337,15 @@ static void fec_tbd_init(struct fec_priv *fec)
 /**
  * Mark the given read buffer descriptor as free
  * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
- * @param[in] pRbd buffer descriptor to mark free again
+ * @param[in] prbd buffer descriptor to mark free again
  */
-static void fec_rbd_clean(int last, struct fec_bd *pRbd)
+static void fec_rbd_clean(int last, struct fec_bd *prbd)
 {
 	unsigned short flags = FEC_RBD_EMPTY;
 	if (last)
 		flags |= FEC_RBD_WRAP;
-	writew(flags, &pRbd->status);
-	writew(0, &pRbd->data_length);
+	writew(flags, &prbd->status);
+	writew(0, &prbd->data_length);
 }
 
 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
@@ -376,37 +361,26 @@ static int _fec_set_hwaddr(struct fec_priv *fec, uchar *mac)
 	writel(0, &fec->eth->gaddr1);
 	writel(0, &fec->eth->gaddr2);
 
-	/*
-	 * Set physical address
-	 */
+	/* Set physical address */
 	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
-			&fec->eth->paddr1);
+	       &fec->eth->paddr1);
 	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
 
 	return 0;
 }
 
-/*
- * Do initial configuration of the FEC registers
- */
+/* Do initial configuration of the FEC registers */
 static void fec_reg_setup(struct fec_priv *fec)
 {
 	uint32_t rcntrl;
 
-	/*
-	 * Set interrupt mask register
-	 */
+	/* Set interrupt mask register */
 	writel(0x00000000, &fec->eth->imask);
 
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
+	/* Clear FEC-Lite interrupt event register(IEVENT) */
 	writel(0xffffffff, &fec->eth->ievent);
 
-
-	/*
-	 * Set FEC-Lite receive control register(R_CNTRL):
-	 */
+	/* Set FEC-Lite receive control register(R_CNTRL): */
 
 	/* Start with frame length = 1518, common for all modes. */
 	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
@@ -449,22 +423,19 @@ static int fec_open(struct fec_priv *fec)
 #ifdef FEC_QUIRK_ENET_MAC
 	/* Enable ENET HW endian SWAP */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
-		&fec->eth->ecntrl);
+	       &fec->eth->ecntrl);
 	/* Enable ENET store and forward mode */
 	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
-		&fec->eth->x_wmrk);
+	       &fec->eth->x_wmrk);
 #endif
-	/*
-	 * Enable FEC-Lite controller
-	 */
+	/* Enable FEC-Lite controller */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
-		&fec->eth->ecntrl);
+	       &fec->eth->ecntrl);
+
 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	udelay(100);
-	/*
-	 * setup the MII gasket for RMII mode
-	 */
 
+	/* setup the MII gasket for RMII mode */
 	/* disable the gasket */
 	writew(0, &fec->eth->miigsk_enr);
 
@@ -522,9 +493,7 @@ static int fec_open(struct fec_priv *fec)
 #endif
 	debug("%s:Speed=%i\n", __func__, speed);
 
-	/*
-	 * Enable SmartDMA receive task
-	 */
+	/* Enable SmartDMA receive task */
 	fec_rx_task_enable(fec);
 
 	udelay(100000);
@@ -539,9 +508,7 @@ static int _fec_init(struct fec_priv *fec, uchar *mac)
 	/* Initialize MAC address */
 	_fec_set_hwaddr(fec, mac);
 
-	/*
-	 * Setup transmit descriptors, there are two in total.
-	 */
+	/* Setup transmit descriptors, there are two in total. */
 	fec_tbd_init(fec);
 
 	/* Setup receive descriptors. */
@@ -552,18 +519,14 @@ static int _fec_init(struct fec_priv *fec, uchar *mac)
 	if (fec->xcv_type != SEVENWIRE)
 		fec_mii_setspeed(fec->bus->priv);
 
-	/*
-	 * Set Opcode/Pause Duration Register
-	 */
+	/* Set Opcode/Pause Duration Register */
 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
 	writel(0x2, &fec->eth->x_wmrk);
-	/*
-	 * Set multicast address filter
-	 */
+
+	/* Set multicast address filter */
 	writel(0x00000000, &fec->eth->gaddr1);
 	writel(0x00000000, &fec->eth->gaddr2);
 
-
 	/* Do not access reserved register for i.MX6UL */
 	if (!is_mx6ul()) {
 		/* clear MIB RAM */
@@ -595,22 +558,16 @@ static void _fec_halt(struct fec_priv *fec)
 {
 	int counter = 0xffff;
 
-	/*
-	 * issue graceful stop command to the FEC transmitter if necessary
-	 */
+	/* issue graceful stop command to the FEC transmitter if necessary */
 	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
-			&fec->eth->x_cntrl);
+	       &fec->eth->x_cntrl);
 
 	debug("eth_halt: wait for stop regs\n");
-	/*
-	 * wait for graceful stop to register
-	 */
+	/* wait for graceful stop to register */
 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
 		udelay(1);
 
-	/*
-	 * Disable SmartDMA tasks
-	 */
+	/* Disable SmartDMA tasks */
 	fec_tx_task_disable(fec);
 	fec_rx_task_disable(fec);
 
@@ -619,7 +576,7 @@ static void _fec_halt(struct fec_priv *fec)
 	 * Note: this will also reset the BD index counter!
 	 */
 	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
-			&fec->eth->ecntrl);
+	       &fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	debug("eth_halt: done\n");
@@ -712,9 +669,7 @@ static int _fec_send(struct fec_priv *fec, void *packet, int length)
 	 */
 	readl(addr + size - 4);
 
-	/*
-	 * Enable SmartDMA transmit task
-	 */
+	/* Enable SmartDMA transmit task */
 	fec_tx_task_enable(fec);
 
 	/*
@@ -759,8 +714,8 @@ static int _fec_send(struct fec_priv *fec, void *packet, int length)
 
 out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
-			readw(&fec->tbd_base[fec->tbd_index].status),
-			fec->tbd_index, ret);
+	      readw(&fec->tbd_base[fec->tbd_index].status),
+	      fec->tbd_index, ret);
 	/* for next transmission use the other buffer */
 	if (fec->tbd_index)
 		fec->tbd_index = 0;
@@ -786,9 +741,7 @@ static int _fec_recv(struct fec_priv *fec, uchar *mac)
 	int i;
 	ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
 
-	/*
-	 * Check if any critical events have happened
-	 */
+	/* Check if any critical events have happened */
 	ievent = readl(&fec->eth->ievent);
 	writel(ievent, &fec->eth->ievent);
 	debug("fec_recv: ievent 0x%lx\n", ievent);
@@ -801,14 +754,14 @@ static int _fec_recv(struct fec_priv *fec, uchar *mac)
 	if (ievent & FEC_IEVENT_HBERR) {
 		/* Heartbeat error */
 		writel(0x00000001 | readl(&fec->eth->x_cntrl),
-				&fec->eth->x_cntrl);
+		       &fec->eth->x_cntrl);
 	}
 	if (ievent & FEC_IEVENT_GRA) {
 		/* Graceful stop complete */
 		if (readl(&fec->eth->x_cntrl) & 0x00000001) {
 			_fec_halt(fec);
 			writel(~0x00000001 & readl(&fec->eth->x_cntrl),
-					&fec->eth->x_cntrl);
+			       &fec->eth->x_cntrl);
 			_fec_init(fec, mac);
 		}
 	}
@@ -836,22 +789,16 @@ static int _fec_recv(struct fec_priv *fec, uchar *mac)
 
 	if (!(bd_status & FEC_RBD_EMPTY)) {
 		if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
-			((readw(&rbd->data_length) - 4) > 14)) {
-			/*
-			 * Get buffer address and size
-			 */
+		    ((readw(&rbd->data_length) - 4) > 14)) {
+			/* Get buffer address and size */
 			addr = readl(&rbd->data_pointer);
 			frame_length = readw(&rbd->data_length) - 4;
-			/*
-			 * Invalidate data cache over the buffer
-			 */
+			/* Invalidate data cache over the buffer */
 			end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
 			addr &= ~(ARCH_DMA_MINALIGN - 1);
 			invalidate_dcache_range(addr, end);
 
-			/*
-			 *  Fill the buffer and pass it to upper layers
-			 */
+			/* Fill the buffer and pass it to upper layers */
 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
 			swap_packet((uint32_t *)addr, frame_length);
 #endif
@@ -879,7 +826,7 @@ static int _fec_recv(struct fec_priv *fec, uchar *mac)
 					      &fec->rbd_base[i]);
 			}
 			flush_dcache_range(addr,
-				addr + ARCH_DMA_MINALIGN);
+					   addr + ARCH_DMA_MINALIGN);
 		}
 
 		fec_rx_task_enable(fec);
@@ -1277,7 +1224,8 @@ static int fecmxc_probe(struct udevice *dev)
 		goto err_phy;
 
 	/* Reset chip. */
-	writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl);
+	writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
+	       &priv->eth->ecntrl);
 	start = get_timer(0);
 	while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 9fc6153..43a7d7b 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -14,21 +14,14 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-
 #ifndef __FEC_MXC_H
 #define __FEC_MXC_H
 
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
-/**
- * Layout description of the FEC
- */
+/* Layout description of the FEC */
 struct ethernet_regs {
+	/* [10:2]addr = 00 */
 
-/* [10:2]addr = 00 */
-
-/*  Control and status Registers (offset 000-1FF) */
-
+	/*  Control and status Registers (offset 000-1FF) */
 	uint32_t res0[1];		/* MBAR_ETH + 0x000 */
 	uint32_t ievent;		/* MBAR_ETH + 0x004 */
 	uint32_t imask;			/* MBAR_ETH + 0x008 */
@@ -71,8 +64,7 @@ struct ethernet_regs {
 	uint32_t emrbr;			/* MBAR_ETH + 0x188 */
 	uint32_t res12[29];		/* MBAR_ETH + 0x18C-1FC */
 
-/*  MIB COUNTERS (Offset 200-2FF) */
-
+	/*  MIB COUNTERS (Offset 200-2FF) */
 	uint32_t rmon_t_drop;		/* MBAR_ETH + 0x200 */
 	uint32_t rmon_t_packets;	/* MBAR_ETH + 0x204 */
 	uint32_t rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
@@ -174,7 +166,6 @@ struct ethernet_regs {
 #define FEC_IMASKT_RL			0x00100000
 #define FEC_IMASK_UN			0x00080000
 
-
 #define FEC_RCNTRL_MAX_FL_SHIFT		16
 #define FEC_RCNTRL_LOOP			0x00000001
 #define FEC_RCNTRL_DRT			0x00000002
@@ -233,9 +224,7 @@ struct fec_bd {
 	uint32_t data_pointer;		/* payload's buffer address */
 };
 
-/**
- * Supported phy types on this platform
- */
+/* Supported phy types on this platform */
 enum xceiver_type {
 	SEVENWIRE,	/* 7-wire       */
 	MII10,		/* MII 10Mbps   */
@@ -244,9 +233,7 @@ enum xceiver_type {
 	RGMII,		/* RGMII */
 };
 
-/**
- * @brief i.MX27-FEC private structure
- */
+/* @brief i.MX27-FEC private structure */
 struct fec_priv {
 	struct ethernet_regs *eth;	/* pointer to register'S base */
 	enum xceiver_type xcv_type;	/* transceiver type */
@@ -270,6 +257,8 @@ struct fec_priv {
 #endif
 };
 
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
 /**
  * @brief Numbers of buffer descriptors for receiving
  *
