From patchwork Sat Oct 8 12:30:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 679874 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3srm3z4q1tz9s36 for ; Sat, 8 Oct 2016 23:32:15 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE0FCA7581; Sat, 8 Oct 2016 14:31:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fQO0QvUu36Yo; Sat, 8 Oct 2016 14:31:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2723BA7594; Sat, 8 Oct 2016 14:31:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8FFFEA7594 for ; Sat, 8 Oct 2016 14:31:46 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 38Th0cS384a4 for ; Sat, 8 Oct 2016 14:31:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by theia.denx.de (Postfix) with ESMTPS id 3DAC7A75F8 for ; Sat, 8 Oct 2016 14:31:36 +0200 (CEST) Received: by mail-pf0-f195.google.com with SMTP id i85so4374916pfa.0 for ; Sat, 08 Oct 2016 05:31:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Uminz/wZV0Vkc0aEIuCbA6980Bc3rRR00ijT+rOD5ws=; b=LOF/NSkMSUvwffQStSDOO/5zEf1sWgMNEqY1IX4w5USHlcr7V7vHoQlkr4+r9J8S+7 GZj2xy4UGfIeaiyA1X8rW5GSKm49kWGkTSJElvcOypiZd7WOevYsEXTcUZ0jlUq/4RnR 2/Pzlhd7dcBb5wam8RqUSDeDGEJ26TRVa0aC4kfB1ht05BlnWKInZhcyhNdWvP6ejRYV g08MuOaNgU+DrqOj9l57x6723opn7zTlAO+Y9i0AAnnJnA6jF9+tEBt8iptgeDizlGHL jXlY0GtSArLWoHDFcaSOW1LJFEDQqENzpW+H2hrgfuWpltAycU+ozBrYpzLpsgaEISvX KKgA== X-Gm-Message-State: AA6/9RnkHhSmrjQ/kP0yVcvmx22DBNe/L9OIMwkbuAYWVjFKvgJ3J4mZVDNtisWEOmLDrw== X-Received: by 10.98.129.132 with SMTP id t126mr36693772pfd.59.1475929895499; Sat, 08 Oct 2016 05:31:35 -0700 (PDT) Received: from Mr.J ([106.220.134.136]) by smtp.gmail.com with ESMTPSA id x66sm21126054pfb.86.2016.10.08.05.31.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 08 Oct 2016 05:31:34 -0700 (PDT) From: Jagan Teki To: Stefano Babic Date: Sat, 8 Oct 2016 18:00:13 +0530 Message-Id: <1475929828-14898-7-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1475929828-14898-1-git-send-email-jteki@openedev.com> References: <1475929828-14898-1-git-send-email-jteki@openedev.com> Cc: Matteo Lisi , Joe Hershberger , u-boot@lists.denx.de, Jagan Teki , Fabio Estevam Subject: [U-Boot] [PATCH v7 06/21] imx6: icorem6: Add ENET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add enet support for engicam icorem6 qdl starter kit. - Add pinmux settings - Add board_eth_init TFTP log: -------- Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> tftpboot {fdt_addr} imx6dl-icore.dtb Using FEC device TFTP from server 192.168.2.96; our IP address is 192.168.2.75 Filename 'imx6dl-icore.dtb'. Load address: 0x0 Loading: ###### 1.3 MiB/s done Bytes transferred = 28976 (7130 hex) CACHE: Misaligned operation at range [00000000, 00007130] icorem6qdl> Cc: Joe Hershberger Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki Acked-by: Joe Hershberger --- board/engicam/icorem6/icorem6.c | 72 +++++++++++++++++++++++++++++++++++++ configs/imx6qdl_icore_mmc_defconfig | 4 +++ include/configs/imx6qdl_icore.h | 12 +++++++ 3 files changed, 88 insertions(+) diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 1856972..a23cb7e 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -9,12 +9,15 @@ #include #include #include +#include +#include #include #include #include #include +#include #include #include #include @@ -30,11 +33,28 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + static iomux_v3_cfg_t const uart4_pads[] = { IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)), + IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const usdhc1_pads[] = { IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -99,6 +119,58 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_FEC_MXC +#define ENET_PHY_RST IMX_GPIO_NR(7, 12) +static int setup_fec(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + s32 timeout = 100000; + u32 reg = 0; + int ret; + + /* Enable fec clock */ + setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK); + + /* use 50MHz */ + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + /* Enable PLLs */ + reg = readl(&anatop->pll_enet); + reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; + writel(reg, &anatop->pll_enet); + reg = readl(&anatop->pll_enet); + reg |= BM_ANADIG_PLL_SYS_ENABLE; + while (timeout--) { + if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK) + break; + } + if (timeout <= 0) + return -EIO; + reg &= ~BM_ANADIG_PLL_SYS_BYPASS; + writel(reg, &anatop->pll_enet); + + /* reset the phy */ + gpio_direction_output(ENET_PHY_RST, 0); + udelay(10000); + gpio_set_value(ENET_PHY_RST, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + SETUP_IOMUX_PADS(enet_pads); + setup_fec(); + + return ret = cpu_eth_init(bis); +} +#endif + int board_early_init_f(void) { SETUP_IOMUX_PADS(uart4_pads); diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index ced6b10..c2c2fe8 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMLS is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y @@ -23,7 +25,9 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y CONFIG_MXC_UART=y +CONFIG_NETDEVICES=y CONFIG_IMX_THERMAL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 0bd0f23..ad4c5f2 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -111,6 +111,18 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #endif +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +# define IMX_FEC_BASE ENET_BASE_ADDR +# define CONFIG_FEC_MXC_PHYADDR 0 +# define CONFIG_FEC_XCV_TYPE RMII +# define CONFIG_ETHPRIME "FEC" + +# define CONFIG_MII +# define CONFIG_PHYLIB +# define CONFIG_PHY_SMSC +#endif + /* SPL */ #ifdef CONFIG_SPL # define CONFIG_SPL_MMC_SUPPORT