From patchwork Thu Sep 22 15:24:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 673485 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sg0kr47xxz9ryT for ; Fri, 23 Sep 2016 01:28:36 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=AXDJ+F4t; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F073CA7664; Thu, 22 Sep 2016 17:26:35 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KtbyfgR5IQd1; Thu, 22 Sep 2016 17:26:35 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 64C60B387D; Thu, 22 Sep 2016 17:26:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4126BB38A6 for ; Thu, 22 Sep 2016 17:25:58 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ij4xdc2YhqL6 for ; Thu, 22 Sep 2016 17:25:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f67.google.com (mail-pa0-f67.google.com [209.85.220.67]) by theia.denx.de (Postfix) with ESMTPS id D0E33B3878 for ; Thu, 22 Sep 2016 17:25:42 +0200 (CEST) Received: by mail-pa0-f67.google.com with SMTP id oz2so3810100pac.0 for ; Thu, 22 Sep 2016 08:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GXFW+jLMhduQ4OXRNoINLylhzjOOUOf4qffqhWHpmjQ=; b=AXDJ+F4tJPY8qF57JXOfrBY/UBeVNOuW3F6NToa3aEAgO3gNvvH1zqE/MXI7BJuCSx JYts0Aw6AyCiAmCBKIFLmgUivu+FFh+2P40Cap62bJ7ymiwJ/j7/tWYgGPdhxSybJ0CZ Ubtv7gR7CX+BfkZwxvr29ro3C2WHDhiSiNJNRe5hWpdZ3MflGzEdg3VdmkFfJTjIs7cX 6JrQMm8J0pV1kPPdFITkxJJU3wr2YKJIUV+T8mk87rlKmJpTbk5BNSTBlhsRY5WjNaYf xoHG8NnrNCo8y5LxXfoDprBsYWMe6FuL7eAYpfDoafF663sLmIXyYGR/3ltOCKgKSDmp WUOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GXFW+jLMhduQ4OXRNoINLylhzjOOUOf4qffqhWHpmjQ=; b=j8NC/dqFx8erxi9INePe3y7+Da8hT/74CVG9oC27arAojIISYN9fTsj2WazWeGa9Zv 6nNUcshDUKlosr2h6lXffbkFZ3Fq/ry5PR267tZd062w8aRPd69AkSIJ93t5HV8wtbaO /nH2BX1i76X/zBlKyXix7LjPblDEIqz6HWGAW42FWCJA7BoW4Ng0iZAUnTDAiieMXbH2 Lczeq8IOtlhxmlENoVHHWOw2L8wiin/kSkUeYlSPUounhLJWgBiMZXhO3X++v3Be343W Qd200v6pnlFXi5p/DVUDWBQQTHsxM2ULu8AJMgL/1FV5yJDwQ0/QgoXqpiehAlkvjpRK ie7g== X-Gm-Message-State: AE9vXwMDbKA3vkyWzkhNGrU4H57FssGNQe9G6US9re1WywdprlTX+0svs+HTfGLiPQ4Img== X-Received: by 10.66.158.233 with SMTP id wx9mr4237456pab.2.1474557940968; Thu, 22 Sep 2016 08:25:40 -0700 (PDT) Received: from Mr.J ([49.204.230.134]) by smtp.gmail.com with ESMTPSA id y184sm4929708pfg.94.2016.09.22.08.25.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Sep 2016 08:25:39 -0700 (PDT) From: Jagan Teki X-Google-Original-From: Jagan Teki To: u-boot@lists.denx.de Date: Thu, 22 Sep 2016 20:54:17 +0530 Message-Id: <1474557860-13218-13-git-send-email-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474557860-13218-1-git-send-email-jagan@amarulasolutions.com> References: <1474557860-13218-1-git-send-email-jagan@amarulasolutions.com> Cc: Matteo Lisi , Jagan Teki , Fabio Estevam Subject: [U-Boot] [PATCH v3 13/16] engicam: icorem6: Add DM_GPIO, DM_MMC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/cpu/armv7/mx6/Kconfig | 2 + board/engicam/icorem6/icorem6.c | 142 ++++++++++++++++++++-------------------- include/configs/imx6qdl_icore.h | 4 ++ 3 files changed, 78 insertions(+), 70 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index e2431a8..762a581 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -100,6 +100,8 @@ config TARGET_MX6Q_ICORE select MX6QDL select OF_CONTROL select DM + select DM_GPIO + select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index a23cb7e..a370c8b 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -7,8 +7,6 @@ */ #include -#include -#include #include #include @@ -29,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -55,70 +49,6 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ -}; - -#ifdef CONFIG_FSL_ESDHC -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) - -struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc1_pads); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} -#endif - #ifdef CONFIG_FEC_MXC #define ENET_PHY_RST IMX_GPIO_NR(7, 12) static int setup_fec(void) @@ -200,6 +130,78 @@ int dram_init(void) #include #include +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include +#include + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + /* * Driving strength: * 0x30 == 40 Ohm diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index b5ad865..0dcf173 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -122,6 +122,10 @@ #define CONFIG_SPL_MMC_SUPPORT #endif #include "imx6_spl.h" +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_GPIO +#undef CONFIG_DM_MMC +#endif #endif #endif /* __IMX6QLD_ICORE_CONFIG_H */