From patchwork Fri Sep 16 20:48:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 671155 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sbSCH6xVJz9sDG for ; Sat, 17 Sep 2016 06:52:27 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=rB7jqUAB; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37F05A7607; Fri, 16 Sep 2016 22:51:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UPelu2emT6Eo; Fri, 16 Sep 2016 22:51:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E560A7577; Fri, 16 Sep 2016 22:50:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 000CEA75C9 for ; Fri, 16 Sep 2016 22:50:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vVbZxen6pRTk for ; Fri, 16 Sep 2016 22:50:29 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by theia.denx.de (Postfix) with ESMTPS id 1952AA7549 for ; Fri, 16 Sep 2016 22:50:16 +0200 (CEST) Received: by mail-pf0-f196.google.com with SMTP id n24so4021826pfb.3 for ; Fri, 16 Sep 2016 13:50:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O1J9g3yhnRh/Xr+6BZv3Pdcy7X2U/RKY8d8uVOPmDQA=; b=rB7jqUABLuRkvvP7zq+OegIkcb2s7Q8FCmSmxTLL6WdhfDzUN+8DuJjU1+A9oITvu6 JkySiec44mR3rxQcg20ljNkpH53afoUw7JglOfTkG25BmAXr2OoPYu3A2hDFzDeCzmPa pa5KSaQUmSBvaoW6Hna/FKW3zo8fzIF6BEoH1ktc/h5u/ka5yx0nGmfuSFY3VV+6ifyz UamvJLMLdVe11T+StV7KdU9FYTutLw10xBxNXRC2xcjqk6liNiITykSeJHuQUlusb1d8 Iv6AZMGuZWHFFXDglvfKYMxfOUO0gZxIGr9OO2jI6ibv6ftPDJ5fN/lp5N18sONLyLGw rs9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O1J9g3yhnRh/Xr+6BZv3Pdcy7X2U/RKY8d8uVOPmDQA=; b=dJLKKONqPQbt4oEhQX5dkDfx1WXGHj48SycPbJ+HoNAgFFHGYqY22UaszC6MHgDCBs /aKkLkFtXtotfHdWd4F/Bsfn7BqvEBduVXuGjMkuJN+oj/BAfhMW3uT+eDavtxp34QpT u+1br6rKoCfxoUWqeuHSgtsDXIs0Wb9cthn+UdZRK5WOLYL4rMxxDQsDSWL6iPlp8Zec 0VbiJnbzG18K+bpWm7q5dZv34eCDFp6P4N8ZICATqLGIis5jheYqTrRGd4LpjE0v0k8G acU8yKmHfyeDKZaaXXCl++YXcORijyhRGudwv9IwvMUR4BRLlnjRx9y4EyaLwR8VsKp+ Sf5w== X-Gm-Message-State: AE9vXwOmuTh1jPuggx89uWyjEmHeiK+2wRw43RarnI2RBR9L7hMoJM62icsbMVMMLt9mvQ== X-Received: by 10.98.88.131 with SMTP id m125mr25680183pfb.63.1474059015456; Fri, 16 Sep 2016 13:50:15 -0700 (PDT) Received: from Mr.J ([49.204.230.134]) by smtp.gmail.com with ESMTPSA id g10sm54190693pfc.57.2016.09.16.13.50.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Sep 2016 13:50:14 -0700 (PDT) From: Jagan Teki X-Google-Original-From: Jagan Teki To: Stefano Babic Date: Sat, 17 Sep 2016 02:18:47 +0530 Message-Id: <1474058929-17637-16-git-send-email-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474058929-17637-1-git-send-email-jagan@amarulasolutions.com> References: <1474058929-17637-1-git-send-email-jagan@amarulasolutions.com> Cc: Matteo Lisi , u-boot@lists.denx.de, Jagan Teki , Fabio Estevam Subject: [U-Boot] [PATCH v2 15/17] arm: dts: Add devicetree for i.MX6Q X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add i.MX6Q dtsi support from Linux. Cc: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/dts/imx6q.dtsi | 300 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 arch/arm/dts/imx6q.dtsi diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi new file mode 100644 index 0000000..c30c836 --- /dev/null +++ b/arch/arm/dts/imx6q.dtsi @@ -0,0 +1,300 @@ + +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include "imx6q-pinfunc.h" +#include "imx6qdl.dtsi" + +/ { + aliases { + ipu1 = &ipu2; + spi4 = &ecspi5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + soc { + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x40000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + aips-bus@02000000 { /* AIPS1 */ + spba-bus@02000000 { + ecspi5: ecspi@02018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6Q_CLK_ECSPI5>, + <&clks IMX6Q_CLK_ECSPI5>; + clock-names = "ipg", "per"; + dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6q-iomuxc"; + }; + }; + + sata: sata@02200000 { + compatible = "fsl,imx6q-ahci"; + reg = <0x02200000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_SATA>, + <&clks IMX6QDL_CLK_SATA_REF_100M>, + <&clks IMX6QDL_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + gpu_vg: gpu@02204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + power-domains = <&gpc 1>; + }; + + ipu2: ipu@02800000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ipu"; + reg = <0x02800000 0x400000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, + <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "bus", "di0", "di1"; + resets = <&src 4>; + + ipu2_csi0: port@0 { + reg = <0>; + }; + + ipu2_csi1: port@1 { + reg = <1>; + }; + + ipu2_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu2_di0_disp0: disp0-endpoint { + }; + + ipu2_di0_hdmi: hdmi-endpoint { + remote-endpoint = <&hdmi_mux_2>; + }; + + ipu2_di0_mipi: mipi-endpoint { + remote-endpoint = <&mipi_mux_2>; + }; + + ipu2_di0_lvds0: lvds0-endpoint { + remote-endpoint = <&lvds0_mux_2>; + }; + + ipu2_di0_lvds1: lvds1-endpoint { + remote-endpoint = <&lvds1_mux_2>; + }; + }; + + ipu2_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu2_di1_hdmi: hdmi-endpoint { + remote-endpoint = <&hdmi_mux_3>; + }; + + ipu2_di1_mipi: mipi-endpoint { + remote-endpoint = <&mipi_mux_3>; + }; + + ipu2_di1_lvds0: lvds0-endpoint { + remote-endpoint = <&lvds0_mux_3>; + }; + + ipu2_di1_lvds1: lvds1-endpoint { + remote-endpoint = <&lvds1_mux_3>; + }; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; + }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; + }; +}; + +&hdmi { + compatible = "fsl,imx6q-hdmi"; + + port@2 { + reg = <2>; + + hdmi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_hdmi>; + }; + }; + + port@3 { + reg = <3>; + + hdmi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_hdmi>; + }; + }; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; + + lvds-channel@0 { + port@2 { + reg = <2>; + + lvds0_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds0>; + }; + }; + + port@3 { + reg = <3>; + + lvds0_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + port@2 { + reg = <2>; + + lvds1_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_lvds1>; + }; + }; + + port@3 { + reg = <3>; + + lvds1_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_lvds1>; + }; + }; + }; +}; + +&mipi_dsi { + ports { + port@2 { + reg = <2>; + + mipi_mux_2: endpoint { + remote-endpoint = <&ipu2_di0_mipi>; + }; + }; + + port@3 { + reg = <3>; + + mipi_mux_3: endpoint { + remote-endpoint = <&ipu2_di1_mipi>; + }; + }; + }; +}; + +&vpu { + compatible = "fsl,imx6q-vpu", "cnm,coda960"; +};