From patchwork Wed Sep 14 05:13:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keerthy X-Patchwork-Id: 669719 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sYqWR2MFMz9ssP for ; Wed, 14 Sep 2016 15:15:47 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D445DA7544; Wed, 14 Sep 2016 07:15:11 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0dPHOK7DYoII; Wed, 14 Sep 2016 07:15:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B7173A75CD; Wed, 14 Sep 2016 07:14:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2B19A756B for ; Wed, 14 Sep 2016 07:14:46 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IaJqCkMOgQ-Z for ; Wed, 14 Sep 2016 07:14:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [198.47.19.12]) by theia.denx.de (Postfix) with ESMTPS id 6CDC6A7573 for ; Wed, 14 Sep 2016 07:14:40 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8E5EZSx002519; Wed, 14 Sep 2016 00:14:35 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5EZTI001131; Wed, 14 Sep 2016 00:14:35 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Wed, 14 Sep 2016 00:14:34 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5EDKV010820; Wed, 14 Sep 2016 00:14:32 -0500 From: Keerthy To: , Date: Wed, 14 Sep 2016 10:43:33 +0530 Message-ID: <1473830013-16480-7-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1473830013-16480-1-git-send-email-j-keerthy@ti.com> References: <1473830013-16480-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Cc: marex@denx.de, u-boot@lists.denx.de, t-kristo@ti.com, joe.hershberger@ni.com, beagleboard-x15@googlegroups.com Subject: [U-Boot] [PATCH 6/6] ARM: OMAP5+: Override switch_to_hypervisor function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode. Based on the work done by Jonathan Bergsagel jbergsagel@ti.com. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 66a3b3d..8ce12c8 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -24,6 +24,30 @@ ENTRY(save_boot_params) str r0, [r1] b save_boot_params_ret ENDPROC(save_boot_params) + +#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) +ENTRY(switch_to_hypervisor) + +/* + * Switch to hypervisor mode + */ + adr r0, save_sp + str sp, [r0] + adr r1, restore_from_hyp + ldr r0, =0x102 + b omap_smc1 +restore_from_hyp: + adr r0, save_sp + ldr sp, [r0] + MRC p15, 4, R0, c1, c0, 0 + ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + orr r0, r0, r1 + MCR p15, 4, R0, c1, c0, 0 + b switch_to_hypervisor_ret +save_sp: + .word 0x0 +ENDPROC(switch_to_hypervisor) +#endif #endif ENTRY(omap_smc1)