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Tue, 19 Jul 2016 03:19:26 -0700 Received: from [172.23.37.99] (helo=xhdsivadur40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1bPS7a-0006zk-5A; Tue, 19 Jul 2016 03:19:26 -0700 From: Siva Durga Prasad Paladugu To: Date: Tue, 19 Jul 2016 21:18:33 +0530 Message-ID: <1468943314-18468-9-git-send-email-sivadur@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468943314-18468-1-git-send-email-sivadur@xilinx.com> References: <1468943314-18468-1-git-send-email-sivadur@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22460.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(199003)(189002)(36756003)(86362001)(4326007)(63266004)(11100500001)(8936002)(50226002)(356003)(77096005)(110136002)(2950100001)(92566002)(107886002)(2906002)(8676002)(586003)(36386004)(7846002)(15650500001)(50986999)(76176999)(19580405001)(4001430100002)(19580395003)(7696003)(5003600100003)(106466001)(87936001)(305945005)(229853001)(33646002)(50466002)(5003940100001)(81156014)(81166006)(9786002)(47776003)(189998001)(2351001)(48376002)(107986001)(5001870100001); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1NAM02HT123; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 670bc77f-a3b4-47e6-474f-08d3afbe3031 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:SN1NAM02HT123; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(13018025)(13023025)(13024025)(13015025)(8121501046)(13017025)(5005006)(10201501046)(3002001)(6055026); SRVR:SN1NAM02HT123; BCL:0; PCL:0; RULEID:; SRVR:SN1NAM02HT123; X-Forefront-PRVS: 000800954F X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2016 10:19:36.7960 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT123 Cc: michals@xilinx.com, Siva Durga Prasad Paladugu Subject: [U-Boot] [PATCH v2 8/9] spi: spi_flash: Fix Bank selection calculation for Dual parallel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In Dual parallel connection the bank selection calculation should be performed using offset and not the calculated address Signed-off-by: Siva Durga Prasad Paladugu --- drivers/mtd/spi/spi_flash.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 404533b..293b47b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -340,7 +340,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size, erase_addr; + u32 erase_size, erase_addr, bank_addr; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -361,13 +361,16 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = flash->erase_cmd; while (len) { erase_addr = offset; + bank_addr = offset; #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual(flash, &erase_addr); + if (flash->dual_flash == SF_DUAL_STACKED_FLASH) + bank_addr = erase_addr; #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bar(flash, erase_addr); + ret = spi_flash_write_bar(flash, bank_addr); if (ret < 0) return ret; #endif @@ -394,7 +397,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; - u32 write_addr; + u32 write_addr, bank_addr; size_t chunk_len, actual; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -412,13 +415,16 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { write_addr = offset; + bank_addr = offset; #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual(flash, &write_addr); + if (flash->dual_flash == SF_DUAL_STACKED_FLASH) + bank_addr = write_addr; #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bar(flash, write_addr); + ret = spi_flash_write_bar(flash, bank_addr); if (ret < 0) return ret; #endif @@ -488,7 +494,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; u8 *cmd, cmdsz; - u32 remain_len, read_len, read_addr; + u32 remain_len, read_len, read_addr, bank_addr; int bank_sel = 0; int ret = -1; @@ -516,13 +522,16 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->read_cmd; while (len) { read_addr = offset; + bank_addr = offset; #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual(flash, &read_addr); + if (flash->dual_flash == SF_DUAL_STACKED_FLASH) + bank_addr = read_addr; #endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_write_bar(flash, read_addr); + ret = spi_flash_write_bar(flash, bank_addr); if (ret < 0) return ret; bank_sel = flash->bank_curr;