From patchwork Tue Jul 12 18:28:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 647541 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rpr9Q6yYNz9s6r for ; Wed, 13 Jul 2016 04:30:02 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9CB6CA7517; Tue, 12 Jul 2016 20:29:39 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9CpeJ8gXpE-v; Tue, 12 Jul 2016 20:29:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 28C25A75D6; Tue, 12 Jul 2016 20:29:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E52DEA7560 for ; Tue, 12 Jul 2016 20:29:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PtKsGXiM5XFh for ; Tue, 12 Jul 2016 20:29:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from cvs.linux-mips.org (eddie.linux-mips.org [148.251.95.138]) by theia.denx.de (Postfix) with ESMTP id 605EDA7518 for ; Tue, 12 Jul 2016 20:29:03 +0200 (CEST) Received: (from localhost user: 'ladis' uid#1021 fake: STDIN (ladis@eddie.linux-mips.org)) by eddie.linux-mips.org id S23993499AbcGLS3DO2a6j for ; Tue, 12 Jul 2016 20:29:03 +0200 From: Ladislav Michl To: u-boot@lists.denx.de Date: Tue, 12 Jul 2016 20:28:15 +0200 Message-Id: <1468348114-11442-8-git-send-email-ladis@linux-mips.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1468348114-11442-1-git-send-email-ladis@linux-mips.org> References: <1468348114-11442-1-git-send-email-ladis@linux-mips.org> Cc: Tom Rini , Richard Weinberger , Scott Wood , Enric Balletbo i Serra Subject: [U-Boot] [PATCH v5 07/26] armv7: add reset timeout to identify_nand_chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" identify_nand_chip hangs forever in loop when NAND is not present. As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout to let function fail gracefully allowing caller to know NAND is not present. On NAND equipped board, reset succeeds on first read, so 1000 loops seems to be safe timeout. Signed-off-by: Ladislav Michl --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/armv7/omap3/spl_id_nand.c | 32 +++++++++++++---------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c index db6de09..26d3aa4 100644 --- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -20,29 +20,16 @@ static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; -/* nand_command: Send a flash command to the flash chip */ -static void nand_command(u8 command) -{ - writeb(command, &gpmc_config->cs[0].nand_cmd); - - if (command == NAND_CMD_RESET) { - unsigned char ret_val; - writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); - do { - /* Wait until ready */ - ret_val = readl(&gpmc_config->cs[0].nand_dat); - } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); - } -} - /* * Many boards will want to know the results of the NAND_CMD_READID command * in order to decide what to do about DDR initialization. This function * allows us to do that very early and to pass those results back to the * board so it can make whatever decisions need to be made. */ -void identify_nand_chip(int *mfr, int *id) +int identify_nand_chip(int *mfr, int *id) { + int loops = 1000; + /* Make sure that we have setup GPMC for NAND correctly. */ writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); @@ -62,8 +49,15 @@ void identify_nand_chip(int *mfr, int *id) sdelay(2000); /* Issue a RESET and then READID */ - nand_command(NAND_CMD_RESET); - nand_command(NAND_CMD_READID); + writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); + while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + sdelay(100); + if (--loops == 0) + return 1; + } + writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd); /* Set the address to read to 0x0 */ writeb(0x0, &gpmc_config->cs[0].nand_adr); @@ -71,4 +65,6 @@ void identify_nand_chip(int *mfr, int *id) /* Read off the manufacturer and device id. */ *mfr = readb(&gpmc_config->cs[0].nand_dat); *id = readb(&gpmc_config->cs[0].nand_dat); + + return 0; } diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 24563c0..1be2b15 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,7 +40,7 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(struct board_sdrc_timings *timings); -void identify_nand_chip(int *mfr, int *id); +int identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,