From patchwork Tue Jul 12 18:28:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 647544 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rprB44clpz9sCy for ; Wed, 13 Jul 2016 04:30:36 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B43C0A75E6; Tue, 12 Jul 2016 20:30:00 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KmEwaup-Cdat; Tue, 12 Jul 2016 20:30:00 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8678EA7607; Tue, 12 Jul 2016 20:29:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 41ADFA759C for ; Tue, 12 Jul 2016 20:29:16 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aK56dUJzNjMe for ; Tue, 12 Jul 2016 20:29:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from cvs.linux-mips.org (eddie.linux-mips.org [148.251.95.138]) by theia.denx.de (Postfix) with ESMTP id 1F021A7517 for ; Tue, 12 Jul 2016 20:29:08 +0200 (CEST) Received: (from localhost user: 'ladis' uid#1021 fake: STDIN (ladis@eddie.linux-mips.org)) by eddie.linux-mips.org id S23993565AbcGLS3H5Hvij for ; Tue, 12 Jul 2016 20:29:07 +0200 From: Ladislav Michl To: u-boot@lists.denx.de Date: Tue, 12 Jul 2016 20:28:18 +0200 Message-Id: <1468348114-11442-11-git-send-email-ladis@linux-mips.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1468348114-11442-1-git-send-email-ladis@linux-mips.org> References: <1468348114-11442-1-git-send-email-ladis@linux-mips.org> Cc: Tom Rini , Richard Weinberger , Scott Wood , Enric Balletbo i Serra Subject: [U-Boot] [PATCH v5 10/26] armv7: simplify identify_nand_chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use newly introduced function Signed-off-by: Ladislav Michl --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/armv7/omap3/spl_id_nand.c | 35 +++++++++++----------------------- 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c index 26d3aa4..0e2f0a2 100644 --- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -13,13 +13,13 @@ */ #include +#include #include +#include #include #include #include -static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; - /* * Many boards will want to know the results of the NAND_CMD_READID command * in order to decide what to do about DDR initialization. This function @@ -31,40 +31,27 @@ int identify_nand_chip(int *mfr, int *id) int loops = 1000; /* Make sure that we have setup GPMC for NAND correctly. */ - writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); - writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); - writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); - writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); - writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); - writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); - - /* - * Enable the config. The CS size goes in bits 11:8. We set - * bit 6 to enable the CS and the base address goes into bits 5:0. - */ - writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | - ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), - &gpmc_config->cs[0].config7); + set_gpmc_cs0(MTD_DEV_TYPE_NAND); sdelay(2000); /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); - while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { sdelay(100); if (--loops == 0) return 1; } - writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd); + writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); /* Set the address to read to 0x0 */ - writeb(0x0, &gpmc_config->cs[0].nand_adr); + writeb(0x0, &gpmc_cfg->cs[0].nand_adr); /* Read off the manufacturer and device id. */ - *mfr = readb(&gpmc_config->cs[0].nand_dat); - *id = readb(&gpmc_config->cs[0].nand_dat); + *mfr = readb(&gpmc_cfg->cs[0].nand_dat); + *id = readb(&gpmc_cfg->cs[0].nand_dat); return 0; }