From patchwork Tue Mar 22 07:38:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 600473 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qTlKY35Zmz9s5Q for ; Tue, 22 Mar 2016 18:52:33 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9E05CA7498; Tue, 22 Mar 2016 08:46:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id biy5EjIyZqDY; Tue, 22 Mar 2016 08:46:16 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 45321A78FC; Tue, 22 Mar 2016 08:45:55 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A0BF3A7611 for ; Tue, 22 Mar 2016 08:44:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q09duLZ0QDck for ; Tue, 22 Mar 2016 08:44:30 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by theia.denx.de (Postfix) with ESMTPS id 71E2DA7781 for ; Tue, 22 Mar 2016 08:44:08 +0100 (CET) Received: by mail-pf0-f195.google.com with SMTP id x3so34315122pfb.0 for ; Tue, 22 Mar 2016 00:44:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4tgJjueizBpWNC+rNdXuSw935buTW9/8XhCNUUxo0k0=; b=fY5uaklSljWKf3YRtbrHBcq4+jjna2K81F+9NTg/CKq+GoneWWyyUGiPqGDsIxjvgT sRZHxwDz84DqkgTnmDMLOUsimf2c9dG+7bG9kQlvU1xwlCZln4CPoV+vs8QBUBa/Yd13 Jdt7YuBD8OXrmWiUZzMmcFTtl6xU8eCArK/9ncpuxb10/TwMH//pQCK4MxkxV/Fnj/WD XPRmqjhdSVh+tHg9adS/1teLzybJO/sbBm90r5nibkwr2zf05mp428I4uYKvI9hUkiGU 9F61mDZ/xJjZrelWYTd3x0H/QiG27n72zE5tUS8S/dI51Wh1++23qZx4lOZhwdto1uH/ rA8A== X-Gm-Message-State: AD7BkJKwkXJ1cypKgkDA46a89Fdx3r8UdYcFphTN/6SNTURalFcQlT6Kxqazl37LsnZLSw== X-Received: by 10.66.54.78 with SMTP id h14mr51608482pap.95.1458632646797; Tue, 22 Mar 2016 00:44:06 -0700 (PDT) Received: from jteki-Latitude-E7450.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id ko9sm45814957pab.37.2016.03.22.00.44.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 00:44:05 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Tue, 22 Mar 2016 13:08:20 +0530 Message-Id: <1458632319-24866-68-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458632319-24866-1-git-send-email-jteki@openedev.com> References: <1458632319-24866-1-git-send-email-jteki@openedev.com> Cc: Michal Simek , Siva Durga Prasad Paladugu , Jagan Teki Subject: [U-Boot] [PATCH v7 68/87] spi: Drop mode_rx X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" mp2580 will take care of tx and rx mode's so there is no need to differentiate these into spi layer level hence replaced all mode_rx macros with mode. Cc: Simon Glass Cc: Bin Meng Cc: Mugunthan V N Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Jagan Teki --- drivers/mtd/spi-nor/m25p80.c | 19 +++++-------------- drivers/spi/ich.c | 6 ++---- drivers/spi/spi-uclass.c | 11 ++++------- drivers/spi/ti_qspi.c | 6 +++--- include/spi.h | 14 ++++---------- 5 files changed, 18 insertions(+), 38 deletions(-) diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c index 429d710..bf9fe02 100644 --- a/drivers/mtd/spi-nor/m25p80.c +++ b/drivers/mtd/spi-nor/m25p80.c @@ -187,26 +187,17 @@ static int m25p80_spi_nor(struct spi_nor *nor) return ret; } - switch (spi->mode_rx) { - case SPI_RX_SLOW: + if (spi->mode & SPI_RX_SLOW) nor->read_mode = SNOR_READ; - break; - case SPI_RX_DUAL: + else if (spi->mode & SPI_RX_DUAL) nor->read_mode = SNOR_READ_1_1_2; - break; - case SPI_RX_QUAD: + else if (spi->mode & SPI_RX_QUAD) nor->read_mode = SNOR_READ_1_1_4; - break; - } - switch (spi->mode) { - case SPI_TX_BYTE: + if (spi->mode & SPI_TX_BYTE) nor->mode = SNOR_WRITE_1_1_BYTE; - break; - case SPI_TX_QUAD: + else if (spi->mode & SPI_TX_QUAD) nor->mode = SNOR_WRITE_1_1_4; - break; - } nor->memory_map = spi->memory_map; nor->max_write_size = spi->max_write_size; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 00b2fed..a89f859 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -649,10 +649,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */ - if (plat->ich_version == ICHV_7) { - slave->mode_rx = SPI_RX_SLOW; - slave->mode = SPI_TX_BYTE; - } + if (plat->ich_version == ICHV_7) + slave->mode = SPI_TX_BYTE | SPI_RX_SLOW; return 0; } diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 7ef2496..0e52ac8 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -181,7 +181,6 @@ static int spi_child_pre_probe(struct udevice *dev) slave->max_hz = plat->max_hz; slave->mode = plat->mode; - slave->mode_rx = plat->mode_rx; slave->wordlen = SPI_DEFAULT_WORDLEN; return 0; @@ -394,7 +393,7 @@ void spi_free_slave(struct spi_slave *slave) int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { - int mode = 0, mode_rx = 0; + int mode = 0; int value; plat->cs = fdtdec_get_int(blob, node, "reg", -1); @@ -426,24 +425,22 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, break; } - plat->mode = mode; - value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); switch (value) { case 1: break; case 2: - mode_rx |= SPI_RX_DUAL; + mode |= SPI_RX_DUAL; break; case 4: - mode_rx |= SPI_RX_QUAD; + mode |= SPI_RX_QUAD; break; default: error("spi-rx-bus-width %d not supported\n", value); break; } - plat->mode_rx = mode_rx; + plat->mode = mode; return 0; } diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index e69ec0d..de687d1 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -338,7 +338,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS); - slave->mode_rx = SPI_RX_QUAD; + slave->mode |= SPI_RX_QUAD; #else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | @@ -422,7 +422,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, bool enable) { u32 memval; - u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); + u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); if (!enable) { writel(0, &priv->base->setup0); @@ -436,7 +436,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, memval |= QSPI_CMD_READ_QUAD; memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; memval |= QSPI_SETUP0_READ_QUAD; - slave->mode_rx = SPI_RX_QUAD; + slave->mode |= SPI_RX_QUAD; break; case SPI_RX_DUAL: memval |= QSPI_CMD_READ_DUAL; diff --git a/include/spi.h b/include/spi.h index dd0b11b..61fefa4 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,12 +26,10 @@ #define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ #define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ #define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */ - -/* SPI mode_rx flags */ -#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ -#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */ -#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */ -#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */ +#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */ +#define SPI_RX_FAST BIT(12) /* receive with 1 wire fast */ +#define SPI_RX_DUAL BIT(13) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(14) /* receive with 4 wires */ /* SPI bus connection options - see enum spi_dual_flash */ #define SPI_CONN_DUAL_SHARED (1 << 0) @@ -61,13 +59,11 @@ struct dm_spi_bus { * @cs: Chip select number (0..n-1) * @max_hz: Maximum bus speed that this slave can tolerate * @mode: SPI mode to use for this device (see SPI mode flags) - * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) */ struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode; - u8 mode_rx; }; #endif /* CONFIG_DM_SPI */ @@ -94,7 +90,6 @@ struct dm_spi_slave_platdata { * bus (bus->seq) so does not need to be stored * @cs: ID of the chip select connected to the slave. * @mode: SPI mode to use for this slave (see SPI mode flags) - * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags) * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. @@ -112,7 +107,6 @@ struct spi_slave { unsigned int cs; #endif uint mode; - u8 mode_rx; unsigned int wordlen; unsigned int max_write_size; void *memory_map;