From patchwork Sat Feb 27 18:19:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 589427 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1059214029E for ; Sun, 28 Feb 2016 05:22:07 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 434F1A78DD; Sat, 27 Feb 2016 19:20:53 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CPPMlTmefDmY; Sat, 27 Feb 2016 19:20:53 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 48FCFA7866; Sat, 27 Feb 2016 19:20:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 90963A7883 for ; Sat, 27 Feb 2016 19:20:43 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M_q54RBvnvpT for ; Sat, 27 Feb 2016 19:20:43 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gagarine.paulk.fr (gagarine.paulk.fr [109.190.93.129]) by theia.denx.de (Postfix) with ESMTPS id 46336A78DF for ; Sat, 27 Feb 2016 19:20:34 +0100 (CET) Received: by gagarine.paulk.fr (Postfix, from userid 65534) id 22C1E20330; Sat, 27 Feb 2016 19:20:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on gagarine.paulk.fr X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from armstrong.paulk.fr (armstrong.paulk.fr [82.233.88.171]) by gagarine.paulk.fr (Postfix) with ESMTPS id A0C3720401; Sat, 27 Feb 2016 19:19:15 +0100 (CET) Received: from localhost.localdomain (aldrin [192.168.0.128]) by armstrong.paulk.fr (Postfix) with ESMTP id 58703378F3; Sat, 27 Feb 2016 19:19:12 +0100 (CET) From: Paul Kocialkowski To: u-boot@lists.denx.de Date: Sat, 27 Feb 2016 19:19:02 +0100 Message-Id: <1456597155-10711-15-git-send-email-contact@paulk.fr> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1456597155-10711-1-git-send-email-contact@paulk.fr> References: <1456597155-10711-1-git-send-email-contact@paulk.fr> Cc: Marek Vasut , Tom Rini , Hashcode Subject: [U-Boot] [PATCH 14/27] omap4: Properly enable USB PHY clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski --- arch/arm/cpu/armv7/omap4/hw_data.c | 4 ++++ arch/arm/cpu/armv7/omap4/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap4/clock.h | 5 ++++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 1cc2072..02c06c1 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -380,6 +380,10 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + /* Enable 32 KHz clock for USB PHY */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index a09581e..2f0e1e8 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -129,6 +129,7 @@ struct prcm_regs const omap4_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, /* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index f3a682a..a408c0c 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -134,8 +134,11 @@ /* CM_DSS_DSS_CLKCTRL */ #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) + /* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24