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[202.36.163.2]) by smtp.gmail.com with ESMTPSA id qz9sm12414935pab.39.2016.01.14.20.22.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jan 2016 20:22:14 -0800 (PST) From: Chris Packham To: u-boot@lists.denx.de, Scott Wood , Prafulla Wadaskar , Luka Perkov Date: Fri, 15 Jan 2016 17:22:03 +1300 Message-Id: <1452831723-22081-1-git-send-email-judge.packham@gmail.com> X-Mailer: git-send-email 2.7.0 Cc: Chris Packham Subject: [U-Boot] [RFC PATCH v1] kirkwood_nand: claim MPP pins on the fly X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson Signed-off-by: Chris Packham --- I haven't wrapped this with a configuration option because I think it should be safe to enable by default. It will either re-apply the same MPP configuration that has already been done in the board init or put the MPP pins into the correct mode to access NAND. I've only got access to one kirkwood based board with NAND flash so I'd appreciate some feedback from someone with access to a few different boards. From the datasheets I have access to it looks like there is only one possible MPP configuration for NF_IO[0-7] so that is what I've implemented. I'm not aware of anything using this driver that needs a different MPP config. drivers/mtd/nand/kirkwood_nand.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 4fc34d6..ff81212 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -9,6 +9,7 @@ #include #include #include +#include #include /* NAND Flash Soc registers */ @@ -22,6 +23,8 @@ struct kwnandf_registers { static struct kwnandf_registers *nf_reg = (struct kwnandf_registers *)KW_NANDF_BASE; +static u32 nand_mpp_backup[9] = { 0 }; + /* * hardware specific access to control-lines/bits */ @@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, void kw_nand_select_chip(struct mtd_info *mtd, int chip) { u32 data; + u32 nand_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP18_NF_IO0, + MPP19_NF_IO1, + 0 + }; + + if (chip >= 0) + kirkwood_mpp_conf(nand_config, nand_mpp_backup); + else + kirkwood_mpp_conf(nand_mpp_backup, NULL); data = readl(&nf_reg->ctrl); data |= NAND_ACTCEBOOT_BIT;