From patchwork Mon Jan 4 14:00:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Purna Chandra Mandal X-Patchwork-Id: 562394 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 040AB1402C4 for ; Tue, 5 Jan 2016 01:02:51 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 728AD4B8A9; Mon, 4 Jan 2016 15:02:18 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SliS-6CeExPE; Mon, 4 Jan 2016 15:02:18 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 132624B849; Mon, 4 Jan 2016 15:02:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A4E3E4B8B4 for ; Mon, 4 Jan 2016 15:02:14 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hKdajMw6oVXf for ; Mon, 4 Jan 2016 15:02:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from email.microchip.com (exsmtp01.microchip.com [198.175.253.37]) by theia.denx.de (Postfix) with ESMTPS id 8F1964B8B8 for ; Mon, 4 Jan 2016 15:02:08 +0100 (CET) Received: from centos7pc (10.10.76.4) by CHN-SV-EXCH01.mchp-main.com (10.10.76.37) with Microsoft SMTP Server id 14.3.181.6; Mon, 4 Jan 2016 07:02:07 -0700 Message-ID: <1451916058.27601.120.camel@microchip.com> From: Purna Chandra Mandal To: Date: Mon, 4 Jan 2016 19:30:58 +0530 Organization: Microchip India Technology Pvt Ltd X-Mailer: Evolution 3.12.11 (3.12.11-15.el7) MIME-Version: 1.0 Cc: purna.mandal@microchip.com Subject: [U-Boot] [PATCH v2 04/13] drivers: serial: add driver for Microchip PIC32 UART controller. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Paul Thacker Signed-off-by: Purna Chandra Mandal --- Changes in v2: - fix missing or corrupted chars during baud rate change - remove loop until any new char is available in _getc() .../serial/microchip,pic32-uart.txt | 5 + drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 230 +++++++++++++++++++++ 4 files changed, 249 insertions(+) create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt create mode 100644 drivers/serial/serial_pic32.c diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt new file mode 100644 index 0000000..f00e215 --- /dev/null +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt @@ -0,0 +1,5 @@ +* Microchip PIC32 serial UART + +Required properties: +- compatible: must be "microchip,pic32mzda-uart". +- reg: exactly one register range. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..9763ea1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_PIC32 + bool "Microchip PIC32" + help + Select this to enable a debug UART using the serial_pic32 driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + + endchoice config DEBUG_UART_BASE @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. +config PIC32_SERIAL + bool "Support for Microchip PIC32 on-chip UART" + help + Support for the UART found on Microchip PIC32 SoC's. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..57cd38b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000..3eddb57 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,230 @@ +/* + * (c) 2015 Paul Thacker + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* UART Control Registers */ +#define U_MOD 0x00 +#define U_MODCLR (U_MOD + _CLR_OFFSET) +#define U_MODSET (U_MOD + _SET_OFFSET) +#define U_STA 0x10 +#define U_STACLR (U_STA + _CLR_OFFSET) +#define U_STASET (U_STA + _SET_OFFSET) +#define U_TXR 0x20 +#define U_RXR 0x30 +#define U_BRG 0x40 + +/* U_MOD bits */ +#define UART_ENABLE BIT(15) + +/* U_STA bits */ +#define UART_RX_ENABLE BIT(12) +#define UART_TX_BRK BIT(11) +#define UART_TX_ENABLE BIT(10) +#define UART_TX_FULL BIT(9) +#define UART_TX_EMPTY BIT(8) +#define UART_RX_OERR BIT(1) +#define UART_RX_DATA_AVAIL BIT(0) + +struct pic32_uart_priv { + void __iomem *base; + ulong uartclk; +}; + +static void pic32_serial_setbrg(void __iomem *base, ulong uart_clk, u32 baud) +{ + writel(0, base + U_BRG); + writel((uart_clk / baud / 16) - 1, base + U_BRG); +} + +/* + * Initialize the serial port with the given baudrate. + * The settings are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{ + /* wait for TX FIFO to empty */ + wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY, + true, CONFIG_SYS_HZ, false); + + /* send break */ + writel(UART_TX_BRK, base + U_STASET); + + /* disable and clear mode */ + writel(0, base + U_MOD); + writel(0, base + U_STA); + + /* set baud rate generator */ + pic32_serial_setbrg(base, clk, baudrate); + + /* enable the UART for TX and RX */ + writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET); + + /* enable the UART */ + writel(UART_ENABLE, base + U_MODSET); + return 0; +} + +/* Output a single byte to the serial port */ +static void pic32_serial_putc(void __iomem *base, const char c) +{ + /* if \n, then add a \r */ + if (c == '\n') + pic32_serial_putc(base, '\r'); + + /* Wait for Tx FIFO not full */ + wait_for_bit(__func__, base + U_STA, UART_TX_FULL, + false, CONFIG_SYS_HZ, false); + + /* stuff the tx buffer with the character */ + writel(c, base + U_TXR); +} + +/* Check number of characters in RX fifo */ +static int pic32_serial_tstc(void __iomem *base) +{ + /* check if rx buffer overrun error has occurred */ + if (readl(base + U_STA) & UART_RX_OERR) { + readl(base + U_RXR); + + /* clear OERR to keep receiving */ + writel(UART_RX_OERR, base + U_STACLR); + } + + return readl(base + U_STA) & UART_RX_DATA_AVAIL; +} + +/* + * Read a single byte from rx fifo. + * Blocking: waits until a character is received, then returns. + * Return the character read directly from the UART's receive register. + */ +static int pic32_serial_getc(void __iomem *base) +{ + /* return error until data is available */ + if (!pic32_serial_tstc(base)) + return -EAGAIN; + + /* read the character from rx buffer */ + return readl(base + U_RXR) & 0xff; +} + +static int pic32_uart_pending(struct udevice *dev, bool input) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + if (input) + return pic32_serial_tstc(priv->base); + + return !(readl(priv->base + U_STA) & UART_TX_EMPTY); +} + +static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->base, priv->uartclk, baudrate); + return 0; +} + +static int pic32_uart_putc(struct udevice *dev, const char ch) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_putc(priv->base, ch); + return 0; +} + +static int pic32_uart_getc(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + return pic32_serial_getc(priv->base); +} + +static int pic32_uart_probe(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); + return 0; +} + +static int pic32_uart_ofdata_to_platdata(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + struct udevice *clkdev; + fdt_addr_t addr; + int ret; + + /* get address */ + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = pic32_ioremap(addr); + + /* get clock rate */ + ret = uclass_get_device(UCLASS_CLK, 0, &clkdev); + if (ret) { + printf("clk class not found, %d\n", ret); + return ret; + } + + priv->uartclk = clk_get_periph_rate(clkdev, PB2CLK); + + return 0; +} + +static const struct dm_serial_ops pic32_uart_ops = { + .putc = pic32_uart_putc, + .pending = pic32_uart_pending, + .getc = pic32_uart_getc, + .setbrg = pic32_uart_setbrg, +}; + +static const struct udevice_id pic32_uart_ids[] = { + { .compatible = "microchip,pic32mzda-uart" }, + {} +}; + +U_BOOT_DRIVER(pic32_serial) = { + .name = "pic32-uart", + .id = UCLASS_SERIAL, + .of_match = pic32_uart_ids, + .probe = pic32_uart_probe, + .ops = &pic32_uart_ops, + .flags = DM_FLAG_PRE_RELOC, + .ofdata_to_platdata = pic32_uart_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct pic32_uart_priv), +}; + +#ifdef CONFIG_DEBUG_UART_PIC32 +#include + +static inline void _debug_uart_init(void) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); +} + +DEBUG_UART_FUNCS +#endif