From patchwork Thu Nov 19 13:48:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Chou X-Patchwork-Id: 546471 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4F7FB141466 for ; Fri, 20 Nov 2015 00:50:36 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 004434B71E; Thu, 19 Nov 2015 14:49:56 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s8IKOL5f0pj5; Thu, 19 Nov 2015 14:49:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61CFC4B721; Thu, 19 Nov 2015 14:49:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B80EE4B656 for ; Thu, 19 Nov 2015 14:49:07 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pKrZsYddZfI0 for ; Thu, 19 Nov 2015 14:49:07 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from www.wytron.com.tw (220-134-43-68.HINET-IP.hinet.net [220.134.43.68]) by theia.denx.de (Postfix) with ESMTP id BFFDE4B65D for ; Thu, 19 Nov 2015 14:49:06 +0100 (CET) Received: from localhost.localdomain (unknown [192.168.1.250]) by www.wytron.com.tw (Postfix) with ESMTP id 07594D00377; Thu, 19 Nov 2015 21:49:00 +0800 (CST) From: Thomas Chou To: u-boot@lists.denx.de Date: Thu, 19 Nov 2015 21:48:08 +0800 Message-Id: <1447940895-7763-7-git-send-email-thomas@wytron.com.tw> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1447940895-7763-1-git-send-email-thomas@wytron.com.tw> References: <1447684616-10297-1-git-send-email-thomas@wytron.com.tw> <1447940895-7763-1-git-send-email-thomas@wytron.com.tw> Cc: Marek Vasut , Tom Rini , clsee@altera.com, Tom Warren , lftan@altera.com Subject: [U-Boot] [PATCH v3 06/13] ns16550: unify serial_rockchip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Unify serial_rockchip, and use the generic binding. Signed-off-by: Thomas Chou Reviewed-by: Tom Rini Tested-by: Ariel D'Alessandro Acked-by: Simon Glass --- arch/arm/dts/rk3288.dtsi | 5 +++++ arch/arm/mach-rockchip/Kconfig | 3 --- drivers/serial/Kconfig | 11 +--------- drivers/serial/Makefile | 1 - drivers/serial/serial_rockchip.c | 43 ---------------------------------------- 5 files changed, 6 insertions(+), 57 deletions(-) delete mode 100644 drivers/serial/serial_rockchip.c diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 0f49709..ac367f8 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -324,6 +324,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -337,6 +338,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -350,6 +352,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -362,6 +365,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -375,6 +379,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ab50f4e..3f7dc8e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -33,9 +33,6 @@ config DM_I2C config DM_GPIO default y -config ROCKCHIP_SERIAL - default y - source "arch/arm/mach-rockchip/rk3288/Kconfig" endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b41f508..1239416 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -186,19 +186,10 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. -config ROCKCHIP_SERIAL - bool "Rockchip on-chip UART support" - depends on ARCH_ROCKCHIP && DM_SERIAL - help - Select this to enable a debug UART for Rockchip devices. This uses - the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in - your board config header. The clock input is automatically set to - use the oscillator (24MHz). - config NS16550_SERIAL bool "NS16550 UART or compatible" depends on DM_SERIAL - default y if X86 || PPC + default y if X86 || PPC || ARCH_ROCKCHIP help Support NS16550 UART or compatible with driver model. This can be enabled in the device tree with the correct input clock frequency. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 9f61113..debc175 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o -obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c deleted file mode 100644 index 0e7bbfc..0000000 --- a/drivers/serial/serial_rockchip.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -static const struct udevice_id rockchip_serial_ids[] = { - { .compatible = "rockchip,rk3288-uart" }, - { } -}; - -static int rockchip_serial_ofdata_to_platdata(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = ns16550_serial_ofdata_to_platdata(dev); - if (ret) - return ret; - - /* Do all Rockchip parts use 24MHz? */ - plat->clock = 24 * 1000000; - - return 0; -} - -U_BOOT_DRIVER(serial_ns16550) = { - .name = "serial_rockchip", - .id = UCLASS_SERIAL, - .of_match = rockchip_serial_ids, - .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), - .priv_auto_alloc_size = sizeof(struct NS16550), - .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -};