From patchwork Thu Sep 3 14:55:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 514125 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6EEEA14010F for ; Fri, 4 Sep 2015 00:56:09 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AED954B785; Thu, 3 Sep 2015 16:56:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wcAtAxDXHCAi; Thu, 3 Sep 2015 16:56:05 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C09A4B768; Thu, 3 Sep 2015 16:56:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 41D314B768 for ; Thu, 3 Sep 2015 16:56:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BBscQ99J7A0C for ; Thu, 3 Sep 2015 16:56:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp.transmode.se (smtp.transmode.se [31.15.61.139]) by theia.denx.de (Postfix) with ESMTP id 0D5A04B761 for ; Thu, 3 Sep 2015 16:55:58 +0200 (CEST) Received: from exch1.transmode.se (exch1.transmode.se [192.168.201.16]) by smtp.transmode.se (Postfix) with ESMTP id 1AFF911870C5; Thu, 3 Sep 2015 16:55:58 +0200 (CEST) Received: from exch1.transmode.se (192.168.201.16) by exch1.transmode.se (192.168.201.16) with Microsoft SMTP Server (TLS) id 15.0.1076.9; Thu, 3 Sep 2015 16:55:57 +0200 Received: from exch1.transmode.se ([fe80::bd49:a412:5dc4:aadd]) by exch1.transmode.se ([fe80::bd49:a412:5dc4:aadd%17]) with mapi id 15.00.1076.000; Thu, 3 Sep 2015 16:55:57 +0200 From: Joakim Tjernlund To: "yorksun@freescale.com" , "u-boot@lists.denx.de" Thread-Topic: FSL DDR3/4 wrlvl_override question Thread-Index: AQHQ5lijasRmOsnn0EaIYAoSp7RpHQ== Date: Thu, 3 Sep 2015 14:55:57 +0000 Message-ID: <1441292157.3349.297.camel@transmode.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Evolution 3.16.4 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [192.168.200.4] Content-ID: MIME-Version: 1.0 Subject: [U-Boot] FSL DDR3/4 wrlvl_override question X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" in drivers/ddr/fsl/options.c we have: #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) /* * due to ddr3 dimm is fly-by topology * we suggest to enable write leveling to * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; popts->zq_en = 1; popts->wrlvl_override = 0; #endif Here one disable wrlvl_override no matter what board code wants. However board code still sets wrlvl_override as it needs specify a good start value for WRLVL_START DQS[0], just like one do for the other DQS[X] in WRLVL_CNTL_2/3 How about remove the above popts->wrlvl_override = 0; line? Furthermore drivers/ddr/fsl/ctrl_regs.c I think set_ddr_wrlvl_cntl() should be adjusted to(or similar): so that board not using auto WRLVL a chance to specify these parameters. I am no expert on DDR so I might be totally off here ... Jocke --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2098,7 +2098,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, /* WRLVL_WLR: Write leveling repeition time */ unsigned int wrlvl_wlr = 0; /* WRLVL_START: Write leveling start time */ - unsigned int wrlvl_start = 0; + unsigned int wrlvl_start = 8; /* suggest enable write leveling for DDR3 due to fly-by topology */ if (wrlvl_en) { @@ -2131,10 +2131,11 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, * Override the write leveling sample and start time * according to specific board */ - if (popts->wrlvl_override) { - wrlvl_smpl = popts->wrlvl_sample; - wrlvl_start = popts->wrlvl_start; - } + } + + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; }