From patchwork Mon Aug 17 13:30:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 507981 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9EDBB14007F for ; Mon, 17 Aug 2015 23:33:00 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8016D4B8AD; Mon, 17 Aug 2015 15:32:26 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xU1JYaEOJFmt; Mon, 17 Aug 2015 15:32:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32D564B987; Mon, 17 Aug 2015 15:32:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A91F4B963 for ; Mon, 17 Aug 2015 15:31:32 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kEynpPAGkMSO for ; Mon, 17 Aug 2015 15:31:32 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by theia.denx.de (Postfix) with ESMTPS id C0BC44B953 for ; Mon, 17 Aug 2015 15:31:22 +0200 (CEST) Received: by pacgr6 with SMTP id gr6so108855512pac.2 for ; Mon, 17 Aug 2015 06:31:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cgZXbI/HdZnojU4zfGiAFOmTzMIqwj0Wwrw7LndkqWQ=; b=SHtZE3f7QmrXw6MqY3hlSdIcwmQAexD96gjQFXeG0Q/9MUK/oe/zkS3kQkS6PROgrR fzzJ3Qc60BfsvRV0jJoI92qN8PRpOlBK9/HJBVJ2H/ANzD1UOjwUj+Wp4zUHjELHlgO1 +ODR9jEgAauOREMRD6LLu553wWIglV3Sj5lVaUjYbVa7YfJ5/lfOR/n5XVUl92mJwo0k VXAptNutZQhGMNe20OTB2kEfgRtsIYp1zzJW//r20WBBgv7pBga4/g/u584dncFpu+nt npbEnomP6iov3wz7GYPfvfN7ybxRcnH+daGWlqQ7uzLOHQplZZTnsEjIeW/o9TVWCLdu EY0A== X-Received: by 10.68.98.5 with SMTP id ee5mr2730919pbb.95.1439818281617; Mon, 17 Aug 2015 06:31:21 -0700 (PDT) Received: from Jubuntu.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id d5sm14752034pdn.74.2015.08.17.06.31.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Aug 2015 06:31:20 -0700 (PDT) From: Jagan Teki To: u-boot@lists.denx.de Date: Mon, 17 Aug 2015 19:00:17 +0530 Message-Id: <1439818219-25617-15-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439818219-25617-1-git-send-email-jteki@openedev.com> References: <1439818219-25617-1-git-send-email-jteki@openedev.com> Cc: Jagan Teki Subject: [U-Boot] [PATCH v3 14/16] spi: zynq_spi: Add config reg shift named macros X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki --- drivers/spi/zynq_spi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b9cf335..817728c 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -28,6 +28,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ +#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ +#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ + #define ZYNQ_SPI_FIFO_DEPTH 128 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ @@ -139,7 +143,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) * xx01 - cs1 * x011 - cs2 */ - cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; + cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; writel(cr, ®s->cr); } @@ -256,14 +260,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) /* Set baudrate x8, if the freq is 0 */ baud_rate_val = 0x2; } else if (plat->speed_hz != speed) { - while ((baud_rate_val < 8) && + while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && ((plat->frequency / (2 << baud_rate_val)) > speed)) baud_rate_val++; plat->speed_hz = speed / (2 << baud_rate_val); } confr &= ~ZYNQ_SPI_CR_BRD_MASK; - confr |= (baud_rate_val << 3); + confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); writel(confr, ®s->cr); priv->freq = speed;