From patchwork Mon Aug 17 07:59:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 507883 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3AFF4140293 for ; Mon, 17 Aug 2015 18:00:50 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1CC64B9F2; Mon, 17 Aug 2015 10:00:46 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EJMd4iDp1zKM; Mon, 17 Aug 2015 10:00:46 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1B2374BA1B; Mon, 17 Aug 2015 10:00:28 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B49144B974 for ; Mon, 17 Aug 2015 10:00:17 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T_CzU0xKTwm3 for ; Mon, 17 Aug 2015 10:00:17 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 49A0B4B976 for ; Mon, 17 Aug 2015 10:00:11 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t7H809wl013640; Mon, 17 Aug 2015 03:00:09 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7H809hG017543; Mon, 17 Aug 2015 03:00:09 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Mon, 17 Aug 2015 03:00:09 -0500 Received: from uda0132425.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7H7xwho010983; Mon, 17 Aug 2015 03:00:08 -0500 From: Vignesh R To: Tom Rini Date: Mon, 17 Aug 2015 13:29:53 +0530 Message-ID: <1439798397-1397-7-git-send-email-vigneshr@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1439798397-1397-1-git-send-email-vigneshr@ti.com> References: <1439798397-1397-1-git-send-email-vigneshr@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [U-Boot RESEND v2 06/10] ARM: AM43XX: Add functions to enable and disable EDMA3 clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R Reviewed-by: Tom Rini Reviewed-by: Jagan Teki --- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index b6396942bbff..35c431eb292d 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -135,3 +135,39 @@ void enable_basic_clocks(void) /* For OPP100 the mac clock should be /5. */ writel(0x4, &cmdpll->clkselmacclk); } + +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks(void) +{ + u32 *const clk_domains_edma3[] = { + 0 + }; + + u32 *const clk_modules_explicit_en_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_edma3, + clk_modules_explicit_en_edma3, + 1); +} + +void disable_edma3_clocks(void) +{ + u32 *const clk_domains_edma3[] = { + 0 + }; + + u32 *const clk_modules_disable_edma3[] = { + &cmper->tpccclkctrl, + &cmper->tptc0clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_edma3, + clk_modules_disable_edma3, + 1); +} +#endif