From patchwork Mon Aug 17 07:59:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 507887 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BE3F2140293 for ; Mon, 17 Aug 2015 18:01:32 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 89B364BA17; Mon, 17 Aug 2015 10:01:10 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JEBbjN8g1aFR; Mon, 17 Aug 2015 10:01:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A9214BA6B; Mon, 17 Aug 2015 10:01:01 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A49E44B9DE for ; Mon, 17 Aug 2015 10:00:22 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ghZXgkN8MPj9 for ; Mon, 17 Aug 2015 10:00:22 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 52D944B9F7 for ; Mon, 17 Aug 2015 10:00:17 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t7H80F1d023085; Mon, 17 Aug 2015 03:00:15 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7H80Fg8026966; Mon, 17 Aug 2015 03:00:15 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Mon, 17 Aug 2015 03:00:15 -0500 Received: from uda0132425.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t7H7xwhs010983; Mon, 17 Aug 2015 03:00:14 -0500 From: Vignesh R To: Tom Rini Date: Mon, 17 Aug 2015 13:29:57 +0530 Message-ID: <1439798397-1397-11-git-send-email-vigneshr@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1439798397-1397-1-git-send-email-vigneshr@ti.com> References: <1439798397-1397-1-git-send-email-vigneshr@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [U-Boot RESEND v2 10/10] ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: Vignesh R Reviewed-by: Jagan Teki --- arch/arm/include/asm/arch-omap5/hardware.h | 5 +++++ include/configs/dra7xx_evm.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index f7011b4e904a..a5bd60009289 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -23,4 +23,9 @@ /* GPMC Base address */ #define GPMC_BASE 0x50000000 +/* EDMA3 Base address for DRA7XX and AM57XX */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#define EDMA3_BASE 0x43300000 +#endif + #endif diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 74994479e60b..6e32de854619 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -166,6 +166,8 @@ /* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_DMA_SUPPORT +#define CONFIG_TI_EDMA3 #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000