From patchwork Wed Aug 12 17:22:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 506711 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2C1641401DE for ; Thu, 13 Aug 2015 03:22:31 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D82F84B67D; Wed, 12 Aug 2015 19:22:27 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9eue0paK7WPQ; Wed, 12 Aug 2015 19:22:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21BD24B65D; Wed, 12 Aug 2015 19:22:27 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 55A8E4B65D for ; Wed, 12 Aug 2015 19:22:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VOoPGdIr4ekr for ; Wed, 12 Aug 2015 19:22:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.mleia.com (li271-223.members.linode.com [178.79.152.223]) by theia.denx.de (Postfix) with ESMTPS id 1BA5C4B653 for ; Wed, 12 Aug 2015 19:22:21 +0200 (CEST) Received: from mail.mleia.com (localhost [127.0.0.1]) by mail.mleia.com (Postfix) with ESMTP id 74F7C104FC4; Wed, 12 Aug 2015 18:28:16 +0100 (BST) From: Vladimir Zapolskiy To: Heiko Schocher , Tom Rini Date: Wed, 12 Aug 2015 20:22:13 +0300 Message-Id: <1439400133-22225-1-git-send-email-vz@mleia.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-49551924 X-CRM114-CacheID: sfid-20150812_182816_501516_39DCDA67 X-CRM114-Status: GOOD ( 14.13 ) Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] i2c: lpc32xx: correct sanity check for requested bus speed X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: Vladimir Zapolskiy Tested-by: Sylvain Lemieux --- The change is based on * https://patchwork.ozlabs.org/patch/503817/ * https://patchwork.ozlabs.org/patch/500511/ drivers/i2c/lpc32xx_i2c.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index be166b0..6c8b504 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -69,20 +69,20 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { int half_period; - int clk_rate; if (speed == 0) return -EINVAL; - if (adap->hwadapnr == 2) - /* OTG I2C clock source is different. */ - clk_rate = get_periph_clk_rate(); - else - clk_rate = get_hclk_clk_rate(); - half_period = (clk_rate / speed) / 2; - - if ((half_period > 255) || (half_period < 0)) - return -EINVAL; + /* OTG I2C clock source and CLK registers are different */ + if (adap->hwadapnr == 2) { + half_period = (get_periph_clk_rate() / speed) / 2; + if (half_period > 0xFF) + return -EINVAL; + } else { + half_period = (get_hclk_clk_rate() / speed) / 2; + if (half_period > 0x3FF) + return -EINVAL; + } writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi); writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo); @@ -97,7 +97,7 @@ static void _i2c_init(struct i2c_adapter *adap, /* soft reset (auto-clears) */ writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); - /* set HI and LO periods for about 350 kHz */ + /* set HI and LO periods for half of the default speed */ lpc32xx_i2c_set_bus_speed(adap, requested_speed); }