| Message ID | 1439400133-22225-1-git-send-email-vz@mleia.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
> -----Original Message----- > From: Vladimir Zapolskiy [mailto:vz@mleia.com] > Sent: 12-Aug-15 1:22 PM > > LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones > and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit > wide. This means that if HCLK is 104MHz, then minimal configurable I2C > clock speed is about 51KHz. > > Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in > assumption that peripheral clock is 13MHz it allows to set the minimal > bus speed about 25.5KHz. > > Check for negative half clock value is removed since it is always false. > > The change fixes the following problem for I2C busses 0 and 1: > > => i2c dev 0 > Setting bus to 0 > => i2c speed 100000 > Setting bus speed to 100000 Hz > Failure changing bus speed (-22) > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> > --- > The change is based on > * https://patchwork.ozlabs.org/patch/503817/ > * https://patchwork.ozlabs.org/patch/500511/ > > drivers/i2c/lpc32xx_i2c.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c > index be166b0..6c8b504 100644 > --- a/drivers/i2c/lpc32xx_i2c.c > +++ b/drivers/i2c/lpc32xx_i2c.c > @@ -69,20 +69,20 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, > unsigned int speed) > { [...] Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
On Wed, Aug 12, 2015 at 08:22:13PM +0300, Vladimir Zapolskiy wrote: > LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones > and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit > wide. This means that if HCLK is 104MHz, then minimal configurable I2C > clock speed is about 51KHz. > > Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in > assumption that peripheral clock is 13MHz it allows to set the minimal > bus speed about 25.5KHz. > > Check for negative half clock value is removed since it is always false. > > The change fixes the following problem for I2C busses 0 and 1: > > => i2c dev 0 > Setting bus to 0 > => i2c speed 100000 > Setting bus speed to 100000 Hz > Failure changing bus speed (-22) > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> > Tested-by: Sylvain Lemieux <slemieux@tycoint.com> Applied to u-boot/master, thanks!
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index be166b0..6c8b504 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -69,20 +69,20 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { int half_period; - int clk_rate; if (speed == 0) return -EINVAL; - if (adap->hwadapnr == 2) - /* OTG I2C clock source is different. */ - clk_rate = get_periph_clk_rate(); - else - clk_rate = get_hclk_clk_rate(); - half_period = (clk_rate / speed) / 2; - - if ((half_period > 255) || (half_period < 0)) - return -EINVAL; + /* OTG I2C clock source and CLK registers are different */ + if (adap->hwadapnr == 2) { + half_period = (get_periph_clk_rate() / speed) / 2; + if (half_period > 0xFF) + return -EINVAL; + } else { + half_period = (get_hclk_clk_rate() / speed) / 2; + if (half_period > 0x3FF) + return -EINVAL; + } writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi); writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo); @@ -97,7 +97,7 @@ static void _i2c_init(struct i2c_adapter *adap, /* soft reset (auto-clears) */ writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); - /* set HI and LO periods for about 350 kHz */ + /* set HI and LO periods for half of the default speed */ lpc32xx_i2c_set_bus_speed(adap, requested_speed); }
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- The change is based on * https://patchwork.ozlabs.org/patch/503817/ * https://patchwork.ozlabs.org/patch/500511/ drivers/i2c/lpc32xx_i2c.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)