From patchwork Fri Jul 3 11:16:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 491003 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D17EE14075E for ; Fri, 3 Jul 2015 21:17:29 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8952D4B6AF; Fri, 3 Jul 2015 13:17:13 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4lpP5a2vYNvN; Fri, 3 Jul 2015 13:17:13 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8BABE4B660; Fri, 3 Jul 2015 13:16:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 42FFC4B65A for ; Fri, 3 Jul 2015 13:16:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BldGrbEzZjq2 for ; Fri, 3 Jul 2015 13:16:41 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id EBA214B624 for ; Fri, 3 Jul 2015 13:16:34 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t63BGUWP028790; Fri, 3 Jul 2015 06:16:30 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t63BGUuF015545; Fri, 3 Jul 2015 06:16:30 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 3 Jul 2015 06:16:22 -0500 Received: from uda0132425.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t63BGE4j017118; Fri, 3 Jul 2015 06:16:28 -0500 From: Vignesh R To: Albert Aribaud , Tom Rini , Jagan Teki , Lokesh Vutla Date: Fri, 3 Jul 2015 16:46:07 +0530 Message-ID: <1435922173-6531-6-git-send-email-vigneshr@ti.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1435922173-6531-1-git-send-email-vigneshr@ti.com> References: <1435922173-6531-1-git-send-email-vigneshr@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Kishon Vijay Abraham I Subject: [U-Boot] [PATCH 05/11] ARM: OMAP5: Add functions to enable and disable EDMA3 clocks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R --- arch/arm/cpu/armv7/omap5/hw_data.c | 41 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++++ arch/arm/include/asm/omap_common.h | 9 ++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 3a723cace71a..33f92b7e225d 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -565,6 +565,47 @@ void enable_basic_uboot_clocks(void) 1); } +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks(void) +{ + u32 const clk_domains_edma3[] = { + 0 + }; + + u32 const clk_modules_hw_auto_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_edma3[] = { + 0 + }; + + do_enable_clocks(clk_domains_edma3, + clk_modules_hw_auto_edma3, + clk_modules_explicit_en_edma3, + 1); +} + +void disable_edma3_clocks(void) +{ + u32 const clk_domains_edma3[] = { + 0 + }; + + u32 const clk_modules_disable_edma3[] = { + (*prcm)->cm_l3main1_tptc1_clkctrl, + (*prcm)->cm_l3main1_tptc2_clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_edma3, + clk_modules_disable_edma3, + 1); +} +#endif + const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index cd51fe7678be..d01ce88306ee 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -989,4 +989,8 @@ struct prcm_regs const dra7xx_prcm = { .prm_abbldo_mpu_setup = 0x4AE07DDC, .prm_abbldo_mpu_ctrl = 0x4AE07DE0, + + /*l3main1 edma*/ + .cm_l3main1_tptc1_clkctrl = 0x4a008778, + .cm_l3main1_tptc2_clkctrl = 0x4a008780, }; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 30e899ad46e3..1d758fc9050c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -349,6 +349,10 @@ struct prcm_regs { /* IPU */ u32 cm_ipu_clkstctrl; u32 cm_ipu_i2c5_clkctrl; + + /*l3main1 edma*/ + u32 cm_l3main1_tptc1_clkctrl; + u32 cm_l3main1_tptc2_clkctrl; }; struct omap_sys_ctrl_regs { @@ -598,6 +602,11 @@ void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); +#ifdef CONFIG_TI_EDMA3 +void enable_edma3_clocks(void); +void disable_edma3_clocks(void); +#endif + /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1