Message ID | 1430309106-22973-2-git-send-email-jagannadh.teki@gmail.com |
---|---|
State | Superseded |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 13a9cad..112ac5e 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -17,7 +17,6 @@ #include <asm/arch/hardware.h> -#define BIT(x) (1 << x) #define CL_BIT(x) (0 << x) /* Timer register bits */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 6109b92..b1513e9 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -56,8 +56,6 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ -#define BIT(x) (1 << (x)) - #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 diff --git a/arch/arm/include/asm/arch-tegra20/dc.h b/arch/arm/include/asm/arch-tegra20/dc.h index 20790b6..cdacdfb 100644 --- a/arch/arm/include/asm/arch-tegra20/dc.h +++ b/arch/arm/include/asm/arch-tegra20/dc.h @@ -351,8 +351,6 @@ struct dc_ctlr { struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */ }; -#define BIT(pos) (1U << pos) - /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define CTRL_MODE_SHIFT 5 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index ff61147..74c3d5d 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 -#define BIT(x) (1 << (x)) - /* SOC-specific pll info */ #ifdef CONFIG_SOC_DM355 #define ARM_PLLDIV PLLC_PLLDIV1 diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 85a046b..a0d1e5d 100644 --- a/arch/arm/mach-keystone/include/mach/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h @@ -11,8 +11,6 @@ #include <asm/arch/hardware.h> -#define BIT(x) (1 << (x)) - /* PLL Control Registers */ struct pllctl_regs { u32 ctl; /* 00 */ diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c index 05c9ef2..7bb20ec 100644 --- a/arch/arm/mvebu-common/mbus.c +++ b/arch/arm/mvebu-common/mbus.c @@ -54,8 +54,6 @@ #include <asm/arch/soc.h> #include <linux/mbus.h> -#define BIT(nr) (1UL << (nr)) - /* DDR target is the same on all platforms */ #define TARGET_DDR 0 diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index b3dae89..8263d27 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -12,8 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BIT(nr) (1UL << (nr)) - #define ETH_PHY_CTRL_REG 0 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 7a62cc3..abcedc2 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -16,7 +16,6 @@ #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) -#define BIT(x) (1 << (x)) #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) #define JZ_NAND_ECC_CTRL_RS BIT(2) #define JZ_NAND_ECC_CTRL_RESET BIT(1) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 484d64c..0daa79e 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -41,7 +41,6 @@ printf(fmt, ##args) #define CONFIG_NR_CPUS 1 -#define BIT(nr) (1UL << (nr)) #define ETH_HLEN 14 /* Total octets in header */ /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ diff --git a/drivers/spi/andes_spi.h b/drivers/spi/andes_spi.h index b7d2945..915af86 100644 --- a/drivers/spi/andes_spi.h +++ b/drivers/spi/andes_spi.h @@ -23,8 +23,6 @@ struct andes_spi_regs { unsigned int ver; /* 0x3c - SPI version reg */ }; -#define BIT(x) (1 << (x)) - /* 0x00 - APB SPI interface setting register */ #define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0) #define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16) diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h index d4612d3..80d8e9f 100644 --- a/drivers/spi/davinci_spi.h +++ b/drivers/spi/davinci_spi.h @@ -36,8 +36,6 @@ struct davinci_spi_regs { dv_reg intvec1; /* 0x64 */ }; -#define BIT(x) (1 << (x)) - /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 #define SPIGCR0_SPIRST_MASK 0x0 diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c index 235557e..cb682dd 100644 --- a/drivers/spi/ep93xx_spi.c +++ b/drivers/spi/ep93xx_spi.c @@ -16,8 +16,6 @@ #include <asm/arch/ep93xx.h> - -#define BIT(x) (1<<(x)) #define SSPBASE SPI_BASE #define SSPCR0 0x0000 diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index ec24415..9f1cbdd 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -12,7 +12,6 @@ #define MC_CCSR_BASE_ADDR \ ((struct mc_ccsr_registers __iomem *)0x8340000) -#define BIT(x) (1 << (x)) #define GCR1_P1_STOP BIT(31) #define GCR1_P2_STOP BIT(30) #define GCR1_P1_DE_RST BIT(23)
Since BIT macro is visiable to include/common.h there is no need to define again it on local headers hence removed. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> --- Changes for v2: - none arch/arm/include/asm/arch-am33xx/cpu.h | 1 - arch/arm/include/asm/arch-omap5/cpu.h | 2 -- arch/arm/include/asm/arch-tegra20/dc.h | 2 -- arch/arm/mach-davinci/cpu.c | 2 -- arch/arm/mach-keystone/include/mach/clock_defs.h | 2 -- arch/arm/mvebu-common/mbus.c | 2 -- board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 2 -- drivers/mtd/nand/jz4740_nand.c | 1 - drivers/net/mvneta.c | 1 - drivers/spi/andes_spi.h | 2 -- drivers/spi/davinci_spi.h | 2 -- drivers/spi/ep93xx_spi.c | 2 -- include/fsl-mc/fsl_mc.h | 1 - 13 files changed, 22 deletions(-)