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h=from:to:cc:subject:date:message-id; bh=2RMWMbmXTFiORFjyfEX27EFk9WRWGXYhmWBOHA5rA9I=; b=O10q+mKHHHjICj2UKwf5IdJPSGb5h2KVJiirmJb5oIT057g4SeXwnHVIro+SCHQ5rS fKyO6n1WioIdD4jnC9y5OReBdw8Gn9fim3ZYXOX2Y0tWb+zW1GvujioEiDCAnnFRBfla szWKCrcyvnn1Td+7UTCiSuleeohlNqJaRsp1DgD1hqn/U2AiQ/1/CI55b5UzZVWDXPB8 Cpus+j2tBauoZWeNo9hD9To55G8UpCmUbjpCTtpHjt38wHCkVUDsToZfk69NlJreElVe 0UidwvVTfwZ7AC3Dl+jmVG+sbXtNwY6w67/x/VCehYXOSGdhGvMCyRu+Rm33lglC+hKm RxPQ== X-Received: by 10.68.210.46 with SMTP id mr14mr41150694pbc.73.1430309129072; Wed, 29 Apr 2015 05:05:29 -0700 (PDT) Received: from Jubuntu.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id mx5sm25314333pdb.75.2015.04.29.05.05.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Apr 2015 05:05:25 -0700 (PDT) From: Jagannadha Sutradharudu Teki To: u-boot@lists.denx.de Date: Wed, 29 Apr 2015 17:35:05 +0530 Message-Id: <1430309106-22973-1-git-send-email-jagannadh.teki@gmail.com> X-Mailer: git-send-email 1.9.1 X-Mailman-Approved-At: Wed, 29 Apr 2015 14:35:48 +0200 Cc: Masahiro Yamada , Tom Rini Subject: [U-Boot] [PATCH v2 1/2] linux/bitops.h: Add BIT macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31 Signed-off-by: Jagannadha Sutradharudu Teki Cc: Masahiro Yamada Cc: Tom Rini Cc: Simon Glass --- Changes for v2: - v1 has made changes only on spi stuff https://patchwork.ozlabs.org/patch/463462/ arch/arc/lib/cache.c | 10 +- arch/arc/lib/interrupts.c | 4 +- arch/arc/lib/timer.c | 2 +- arch/arm/cpu/arm1136/mx31/timer.c | 4 +- arch/arm/cpu/arm1136/mx35/generic.c | 8 +- arch/arm/cpu/arm920t/ep93xx/timer.c | 4 +- arch/arm/cpu/arm920t/s3c24x0/speed.c | 4 +- arch/arm/cpu/arm926ejs/mx25/generic.c | 2 +- arch/arm/cpu/arm926ejs/mx27/timer.c | 4 +- arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c | 6 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 8 +- arch/arm/cpu/armv7/am33xx/board.c | 10 +- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 30 +- arch/arm/cpu/armv7/exynos/clock.c | 2 +- arch/arm/cpu/armv7/exynos/common_setup.h | 12 +- arch/arm/cpu/armv7/exynos/exynos4_setup.h | 30 +- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 152 ++-- arch/arm/cpu/armv7/exynos/sec_boot.S | 4 +- arch/arm/cpu/armv7/exynos/spl_boot.c | 2 +- arch/arm/cpu/armv7/exynos/system.c | 4 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 8 +- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- arch/arm/cpu/armv7/mx6/clock.c | 4 +- arch/arm/cpu/armv7/mx6/ddr.c | 18 +- arch/arm/cpu/armv7/mx6/soc.c | 2 +- arch/arm/cpu/armv7/omap-common/mem-common.c | 2 +- arch/arm/cpu/armv7/sunxi/dram_sun4i.c | 2 +- arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 2 +- arch/arm/cpu/armv7/sunxi/psci.S | 10 +- arch/arm/cpu/armv7/sunxi/usbc.c | 8 +- arch/arm/cpu/armv7/u8500/prcmu.c | 12 +- arch/arm/cpu/armv7/zynq/clk.c | 2 +- arch/arm/cpu/armv7m/stm32f4/clock.c | 36 +- arch/arm/cpu/armv7m/stm32f4/timer.c | 6 +- arch/arm/imx-common/misc.c | 4 +- arch/arm/imx-common/spl.c | 2 +- arch/arm/imx-common/timer.c | 8 +- arch/arm/include/asm/arch-am33xx/clock.h | 10 +- arch/arm/include/asm/arch-am33xx/gpio.h | 2 +- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 12 +- arch/arm/include/asm/arch-armada100/armada100.h | 4 +- arch/arm/include/asm/arch-armada100/config.h | 2 +- arch/arm/include/asm/arch-armada100/spi.h | 32 +- .../include/asm/arch-armada100/utmi-armada100.h | 6 +- arch/arm/include/asm/arch-armv7/sysctrl.h | 8 +- arch/arm/include/asm/arch-armv7/systimer.h | 8 +- arch/arm/include/asm/arch-ep93xx/ep93xx.h | 166 ++--- arch/arm/include/asm/arch-exynos/dmc.h | 6 +- arch/arm/include/asm/arch-exynos/dsim.h | 24 +- arch/arm/include/asm/arch-exynos/ehci.h | 26 +- arch/arm/include/asm/arch-exynos/fb.h | 166 ++--- arch/arm/include/asm/arch-exynos/i2s-regs.h | 28 +- arch/arm/include/asm/arch-exynos/mmc.h | 40 +- arch/arm/include/asm/arch-exynos/power.h | 14 +- arch/arm/include/asm/arch-exynos/pwm.h | 2 +- arch/arm/include/asm/arch-exynos/spi.h | 36 +- arch/arm/include/asm/arch-exynos/system.h | 2 +- arch/arm/include/asm/arch-exynos/xhci-exynos.h | 6 +- arch/arm/include/asm/arch-lpc32xx/clk.h | 74 +- arch/arm/include/asm/arch-lpc32xx/emc.h | 12 +- arch/arm/include/asm/arch-lpc32xx/timer.h | 4 +- arch/arm/include/asm/arch-lpc32xx/uart.h | 56 +- arch/arm/include/asm/arch-lpc32xx/wdt.h | 20 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 +- arch/arm/include/asm/arch-mvebu/spi.h | 14 +- arch/arm/include/asm/arch-mx25/imx-regs.h | 66 +- arch/arm/include/asm/arch-mx25/macro.h | 2 +- arch/arm/include/asm/arch-mx27/imx-regs.h | 268 +++---- arch/arm/include/asm/arch-mx31/imx-regs.h | 44 +- arch/arm/include/asm/arch-mx35/crm_regs.h | 52 +- arch/arm/include/asm/arch-mx35/imx-regs.h | 34 +- arch/arm/include/asm/arch-mx35/lowlevel_macro.S | 2 +- arch/arm/include/asm/arch-mx5/crm_regs.h | 6 +- arch/arm/include/asm/arch-mx5/imx-regs.h | 50 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 158 ++--- arch/arm/include/asm/arch-mx6/imx-regs.h | 22 +- arch/arm/include/asm/arch-mx6/iomux.h | 12 +- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h | 142 ++-- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 188 ++--- arch/arm/include/asm/arch-mxs/regs-i2c.h | 196 ++--- arch/arm/include/asm/arch-mxs/regs-lcdif.h | 112 +-- arch/arm/include/asm/arch-mxs/regs-lradc.h | 138 ++-- arch/arm/include/asm/arch-mxs/regs-ocotp.h | 82 +-- arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 638 ++++++++--------- arch/arm/include/asm/arch-mxs/regs-power-mx23.h | 224 +++--- arch/arm/include/asm/arch-mxs/regs-power-mx28.h | 272 +++---- arch/arm/include/asm/arch-mxs/regs-rtc.h | 62 +- arch/arm/include/asm/arch-mxs/regs-ssp.h | 166 ++--- arch/arm/include/asm/arch-mxs/regs-timrot.h | 44 +- arch/arm/include/asm/arch-mxs/regs-uartapp.h | 166 ++--- arch/arm/include/asm/arch-mxs/regs-usb.h | 16 +- arch/arm/include/asm/arch-mxs/regs-usbphy.h | 116 +-- arch/arm/include/asm/arch-omap3/am35x_def.h | 28 +- arch/arm/include/asm/arch-omap3/dma.h | 10 +- arch/arm/include/asm/arch-omap3/dss.h | 30 +- arch/arm/include/asm/arch-omap3/ehci.h | 20 +- arch/arm/include/asm/arch-omap3/mmc_host_def.h | 20 +- arch/arm/include/asm/arch-omap3/mux.h | 12 +- arch/arm/include/asm/arch-omap3/omap3-regs.h | 32 +- arch/arm/include/asm/arch-omap4/clock.h | 26 +- arch/arm/include/asm/arch-omap4/ehci.h | 16 +- arch/arm/include/asm/arch-omap4/mux_omap4.h | 12 +- arch/arm/include/asm/arch-omap4/omap.h | 6 +- arch/arm/include/asm/arch-omap5/clock.h | 78 +- arch/arm/include/asm/arch-omap5/ehci.h | 14 +- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 10 +- arch/arm/include/asm/arch-omap5/mux_omap5.h | 12 +- arch/arm/include/asm/arch-omap5/omap.h | 14 +- arch/arm/include/asm/arch-omap5/sata.h | 2 +- arch/arm/include/asm/arch-pxa/pxa-regs.h | 788 ++++++++++----------- arch/arm/include/asm/arch-pxa/regs-mmc.h | 80 +-- arch/arm/include/asm/arch-pxa/regs-uart.h | 96 +-- arch/arm/include/asm/arch-pxa/regs-usb.h | 110 +-- arch/arm/include/asm/arch-rmobile/ehci-rmobile.h | 66 +- arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h | 6 +- arch/arm/include/asm/arch-rmobile/sh_sdhi.h | 118 +-- arch/arm/include/asm/arch-s3c24x0/iomux.h | 44 +- arch/arm/include/asm/arch-s5pc1xx/mmc.h | 38 +- arch/arm/include/asm/arch-s5pc1xx/power.h | 4 +- arch/arm/include/asm/arch-s5pc1xx/pwm.h | 2 +- arch/arm/include/asm/arch-socfpga/clock_manager.h | 26 +- arch/arm/include/asm/arch-socfpga/system_manager.h | 22 +- arch/arm/include/asm/arch-spear/hardware.h | 8 +- arch/arm/include/asm/arch-spear/spr_emi.h | 4 +- arch/arm/include/asm/arch-stm32f4/fmc.h | 6 +- arch/arm/include/asm/arch-stm32f4/stm32.h | 10 +- arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 2 +- arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 2 +- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 14 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +- arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 4 +- arch/arm/include/asm/arch-sunxi/display.h | 88 +-- arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 6 +- arch/arm/include/asm/arch-sunxi/dram_sun6i.h | 40 +- arch/arm/include/asm/arch-sunxi/mmc.h | 4 +- arch/arm/include/asm/arch-sunxi/rsb.h | 12 +- arch/arm/include/asm/arch-tegra/ap.h | 8 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 114 +-- arch/arm/include/asm/arch-tegra/pmc.h | 76 +- arch/arm/include/asm/arch-tegra/scu.h | 2 +- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 58 +- arch/arm/include/asm/arch-tegra/usb.h | 68 +- arch/arm/include/asm/arch-tegra114/sysctr.h | 4 +- arch/arm/include/asm/arch-tegra124/ahb.h | 12 +- arch/arm/include/asm/arch-tegra124/flow.h | 8 +- arch/arm/include/asm/arch-tegra124/mc.h | 2 +- arch/arm/include/asm/arch-tegra124/sysctr.h | 4 +- arch/arm/include/asm/arch-vf610/crm_regs.h | 60 +- arch/arm/include/asm/arch-vf610/imx-regs.h | 42 +- arch/arm/include/asm/armv7.h | 4 +- arch/arm/include/asm/armv7m.h | 10 +- arch/arm/include/asm/armv8/mmu.h | 14 +- arch/arm/include/asm/ehci-omap.h | 26 +- arch/arm/include/asm/emif.h | 100 +-- arch/arm/include/asm/imx-common/dma.h | 28 +- arch/arm/include/asm/imx-common/iomux-v3.h | 44 +- arch/arm/include/asm/imx-common/regs-apbh.h | 176 ++--- arch/arm/include/asm/imx-common/regs-bch.h | 50 +- arch/arm/include/asm/imx-common/regs-gpmi.h | 88 +-- arch/arm/include/asm/imx-common/regs-usbphy.h | 10 +- arch/arm/include/asm/macro.h | 4 +- arch/arm/include/asm/omap_mmc.h | 4 +- arch/arm/include/asm/pl310.h | 6 +- arch/arm/include/asm/proc-armv/ptrace.h | 8 +- arch/arm/include/asm/system.h | 68 +- arch/arm/include/asm/ti-common/davinci_nand.h | 10 +- arch/arm/include/asm/ti-common/keystone_nav.h | 2 +- arch/arm/include/asm/ti-common/ti-edma3.h | 2 +- arch/arm/lib/_divsi3.S | 8 +- arch/arm/lib/gic_64.S | 2 +- arch/arm/lib/memset.S | 2 +- arch/arm/lib/relocate.S | 2 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 32 +- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 32 +- arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 32 +- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 32 +- arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 16 +- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 16 +- arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 32 +- arch/arm/mach-at91/armv7/clock.c | 2 +- arch/arm/mach-at91/armv7/sama5d3_devices.c | 8 +- arch/arm/mach-at91/include/mach/at91_matrix.h | 8 +- arch/arm/mach-at91/include/mach/at91_pmc.h | 28 +- arch/arm/mach-at91/include/mach/at91_rstc.h | 2 +- arch/arm/mach-at91/include/mach/at91_spi.h | 8 +- .../mach-at91/include/mach/at91sam9260_matrix.h | 24 +- .../mach-at91/include/mach/at91sam9261_matrix.h | 22 +- .../mach-at91/include/mach/at91sam9263_matrix.h | 22 +- arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | 18 +- .../mach-at91/include/mach/at91sam9g45_matrix.h | 42 +- .../arm/mach-at91/include/mach/at91sam9rl_matrix.h | 22 +- .../arm/mach-at91/include/mach/at91sam9x5_matrix.h | 42 +- arch/arm/mach-bcm283x/include/mach/mbox.h | 8 +- arch/arm/mach-bcm283x/include/mach/timer.h | 8 +- arch/arm/mach-davinci/dm355.c | 2 +- arch/arm/mach-davinci/dm644x.c | 6 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/include/mach/aintc_defs.h | 2 +- .../arm/mach-davinci/include/mach/da850_lowlevel.h | 4 +- arch/arm/mach-davinci/include/mach/da8xx-usb.h | 30 +- arch/arm/mach-davinci/include/mach/ddr2_defs.h | 4 +- arch/arm/mach-davinci/include/mach/hardware.h | 38 +- arch/arm/mach-davinci/include/mach/pll_defs.h | 38 +- arch/arm/mach-davinci/include/mach/psc_defs.h | 4 +- arch/arm/mach-davinci/include/mach/sdmmc_defs.h | 102 +-- arch/arm/mach-davinci/include/mach/syscfg_defs.h | 12 +- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-kirkwood/cpu.c | 18 +- arch/arm/mach-kirkwood/include/mach/gpio.h | 4 +- arch/arm/mach-orion5x/cpu.c | 10 +- arch/arm/mach-orion5x/timer.c | 2 +- arch/arm/mach-tegra/cpu.h | 8 +- arch/arm/mach-tegra/pinmux-common.c | 2 +- arch/arm/mach-tegra/powergate.c | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 26 +- arch/arm/mach-tegra/tegra124/xusb-padctl.c | 30 +- arch/arm/mach-tegra/tegra20/clock.c | 20 +- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 42 +- arch/arm/mach-tegra/tegra30/clock.c | 20 +- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 56 +- arch/arm/mach-versatile/timer.c | 14 +- arch/arm/mvebu-common/dram.c | 4 +- arch/arm/mvebu-common/serdes/board_env_spec.h | 6 +- arch/arm/mvebu-common/serdes/high_speed_env_lib.c | 32 +- arch/avr32/cpu/at32ap700x/portmux.c | 222 +++--- arch/avr32/include/asm/arch-at32ap700x/addrspace.h | 6 +- arch/avr32/include/asm/arch-at32ap700x/portmux.h | 22 +- arch/avr32/include/asm/arch-common/portmux-pio.h | 8 +- arch/blackfin/cpu/cpu.c | 2 +- arch/blackfin/include/asm/mach-bf561/ports.h | 64 +- arch/blackfin/include/asm/mach-common/bits/cgu.h | 34 +- arch/blackfin/include/asm/mach-common/bits/eppi.h | 2 +- .../include/asm/mach-common/bits/ports-a.h | 32 +- .../include/asm/mach-common/bits/ports-b.h | 32 +- .../include/asm/mach-common/bits/ports-c.h | 32 +- .../include/asm/mach-common/bits/ports-d.h | 32 +- .../include/asm/mach-common/bits/ports-e.h | 32 +- .../include/asm/mach-common/bits/ports-f.h | 32 +- .../include/asm/mach-common/bits/ports-g.h | 32 +- .../include/asm/mach-common/bits/ports-h.h | 32 +- .../include/asm/mach-common/bits/ports-i.h | 32 +- .../include/asm/mach-common/bits/ports-j.h | 32 +- arch/blackfin/include/asm/mach-common/bits/uart4.h | 92 +-- arch/m68k/cpu/mcf5227x/speed.c | 4 +- arch/m68k/cpu/mcf532x/speed.c | 6 +- arch/m68k/cpu/mcf5445x/speed.c | 4 +- arch/m68k/include/asm/cache.h | 106 +-- arch/m68k/include/asm/coldfire/flexbus.h | 10 +- arch/mips/include/asm/jz4740.h | 594 ++++++++-------- arch/mips/include/asm/malta.h | 8 +- arch/mips/mach-au1x00/au1x00_usb_ohci.h | 54 +- arch/nios2/cpu/interrupts.c | 12 +- arch/powerpc/cpu/mpc5xxx/cpu_init.c | 26 +- arch/powerpc/cpu/mpc5xxx/interrupts.c | 2 +- arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c | 14 +- arch/powerpc/cpu/mpc5xxx/speed.c | 6 +- arch/powerpc/cpu/mpc5xxx/usb_ohci.h | 54 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 6 +- arch/powerpc/cpu/ppc4xx/4xx_pcie.c | 8 +- arch/powerpc/cpu/ppc4xx/usb_ohci.h | 54 +- arch/powerpc/include/asm/fsl_mpc83xx_serdes.h | 2 +- arch/powerpc/include/asm/fsl_tgec.h | 14 +- arch/powerpc/include/asm/immap_512x.h | 12 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 34 +- arch/sh/cpu/sh4/watchdog.c | 6 +- arch/sparc/cpu/leon3/usb_uhci.c | 2 +- arch/sparc/cpu/leon3/usb_uhci.h | 22 +- arch/x86/cpu/cpu.c | 4 +- arch/x86/cpu/ivybridge/bd82x6x.c | 4 +- arch/x86/cpu/ivybridge/early_init.c | 10 +- arch/x86/cpu/ivybridge/gma.c | 38 +- arch/x86/cpu/ivybridge/gma.h | 14 +- arch/x86/cpu/ivybridge/lpc.c | 90 +-- arch/x86/cpu/ivybridge/model_206ax.c | 36 +- arch/x86/cpu/ivybridge/northbridge.c | 20 +- arch/x86/cpu/ivybridge/report_platform.c | 6 +- arch/x86/cpu/ivybridge/usb_xhci.c | 8 +- arch/x86/cpu/quark/hte.c | 10 +- arch/x86/cpu/quark/mrc_util.c | 24 +- arch/x86/cpu/quark/smc.c | 98 +-- arch/x86/cpu/quark/smc.h | 66 +- arch/x86/cpu/start.S | 4 +- arch/x86/include/asm/arch-ivybridge/model_206ax.h | 20 +- arch/x86/include/asm/arch-ivybridge/pch.h | 174 ++--- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 22 +- arch/x86/include/asm/ioapic.h | 10 +- arch/x86/include/asm/lapic.h | 2 +- arch/x86/include/asm/lapic_def.h | 20 +- arch/x86/include/asm/msr-index.h | 32 +- arch/x86/include/asm/mtrr.h | 8 +- arch/x86/include/asm/turbo.h | 4 +- arch/x86/lib/bios.c | 6 +- arch/x86/lib/bios_interrupts.c | 4 +- arch/x86/lib/cmd_mtrr.c | 2 +- arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/physmem.c | 2 +- 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board/atmel/at91sam9261ek/at91sam9261ek.c | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 6 +- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 4 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 2 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +- board/atmel/sama5d3xek/sama5d3xek.c | 4 +- board/bf527-ezkit/video.c | 10 +- board/birdland/bav335x/board.c | 2 +- board/bluewater/snapper9260/snapper9260.c | 2 +- board/calao/tny_a9260/tny_a9260.c | 2 +- board/calao/usb_a9263/usb_a9263.c | 2 +- board/canmb/canmb.c | 4 +- board/cloudengines/pogo_e02/pogo_e02.h | 6 +- board/cm-bf537e/gpio_cfi_flash.c | 6 +- board/cm5200/cm5200.c | 2 +- board/cm5200/cmd_cm5200.c | 24 +- board/cmi/flash.c | 2 +- board/comelit/dig297/dig297.c | 2 +- board/compulab/cm_fx6/cm_fx6.c | 2 +- board/compulab/cm_t335/cm_t335.c | 2 +- board/compulab/common/omap3_display.c | 16 +- board/d-link/dns325/dns325.h | 4 +- board/davedenx/qong/lowlevel_init.S | 34 +- board/davedenx/qong/qong_fpga.h | 2 +- board/davinci/da8xxevm/da850evm.c | 2 +- board/davinci/dm355leopard/dm355leopard.c | 20 +- board/davinci/dm365evm/dm365evm.c | 6 +- board/davinci/sonata/sonata.c | 2 +- board/egnite/ethernut5/ethernut5.c | 2 +- board/esd/cpci405/flash.c | 4 +- board/esd/meesc/meesc.c | 2 +- board/esd/otc570/otc570.c | 2 +- board/esd/pmc440/pmc440.h | 26 +- board/esg/ima3-mx53/ima3-mx53.c | 2 +- board/freescale/common/dcu_sii9022a.c | 16 +- board/freescale/common/sleep.h | 2 +- board/freescale/mx31ads/lowlevel_init.S | 18 +- board/freescale/mx6qarm2/mx6qarm2.c | 2 +- board/freescale/mx6sabresd/mx6sabresd.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/gdsys/405ex/io64.c | 4 +- board/gdsys/common/ihs_mdio.c | 4 +- board/gdsys/common/mclink.c | 6 +- board/gdsys/common/osd.c | 2 +- board/gumstix/pepper/board.c | 2 +- board/ifm/ac14xx/ac14xx.c | 12 +- board/ifm/o2dnt2/o2dnt2.c | 8 +- board/in-circuit/grasshopper/grasshopper.c | 2 +- board/inka4x0/inka4x0.c | 2 +- board/intercontrol/digsy_mtc/digsy_mtc.c | 34 +- board/iomega/iconnect/iconnect.h | 10 +- board/ipek01/ipek01.c | 2 +- board/isee/igep0033/board.c | 2 +- board/jornada/jornada.c | 4 +- board/jornada/setup.S | 16 +- board/jupiter/jupiter.c | 8 +- board/karo/tk71/tk71.c | 4 +- board/karo/tx25/lowlevel_init.S | 4 +- board/kmc/kzm9g/kzm9g.c | 32 +- board/kosagi/novena/video.c | 26 +- board/logicpd/am3517evm/am3517evm.c | 2 +- board/logicpd/imx27lite/imx27lite.c | 2 +- board/micronas/vct/ebi.h | 14 +- board/mimc/mimc200/mimc200.c | 4 +- board/motionpro/motionpro.c | 6 +- board/mpl/common/usb_uhci.c | 2 +- board/mpl/common/usb_uhci.h | 22 +- board/mpl/pati/cmd_pati.c | 20 +- board/munices/munices.c | 2 +- board/omicron/calimain/calimain.c | 2 +- board/pandora/pandora.c | 6 +- board/pdm360ng/pdm360ng.c | 4 +- board/phytec/pcm030/pcm030.c | 2 +- board/phytec/pcm051/board.c | 2 +- board/raidsonic/ib62x0/ib62x0.h | 6 +- board/renesas/alt/alt.c | 14 +- board/renesas/ecovec/ecovec.c | 10 +- board/renesas/gose/gose.c | 14 +- board/renesas/koelsch/koelsch.c | 14 +- board/renesas/lager/lager.c | 14 +- board/renesas/porter/porter.c | 12 +- board/renesas/r0p7734/r0p7734.c | 2 +- board/renesas/silk/silk.c | 14 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- board/samsung/goni/lowlevel_init.S | 18 +- board/samsung/smdkc100/onenand.c | 10 +- board/samsung/universal_c210/universal.c | 8 +- board/sbc8641d/sbc8641d.c | 2 +- board/siemens/corvus/board.c | 4 +- board/siemens/draco/board.c | 2 +- board/siemens/pxm2/board.c | 2 +- board/siemens/rut/board.c | 2 +- board/silica/pengwyn/board.c | 2 +- board/socrates/socrates.c | 2 +- board/st/stm32f429-discovery/stm32f429-discovery.c | 2 +- board/synopsys/axs101/axs101.c | 2 +- board/synopsys/axs101/nand.c | 12 +- board/syteco/zmx25/lowlevel_init.S | 6 +- board/ti/am335x/board.c | 2 +- board/ti/am335x/mux.c | 16 +- board/ti/am43xx/board.c | 2 +- board/ti/beagle_x15/board.c | 2 +- board/ti/dra7xx/evm.c | 2 +- board/ti/ks2_evm/ddr3_cfg.c | 16 +- board/ti/ti814x/evm.c | 2 +- board/tqc/tqm5200/cmd_stk52xx.c | 44 +- board/tqc/tqm5200/tqm5200.c | 8 +- board/trizepsiv/conxs.c | 4 +- board/v38b/v38b.c | 4 +- board/woodburn/woodburn.c | 2 +- board/zipitz2/zipitz2.c | 22 +- common/bedbug.c | 8 +- common/bootm.c | 2 +- common/cli_hush.c | 4 +- common/cmd_nvedit.c | 2 +- common/usb_kbd.c | 24 +- common/usb_storage.c | 2 +- drivers/bios_emulator/atibios.c | 2 +- drivers/block/ahci.c | 44 +- drivers/block/dwc_ahsata.c | 26 +- drivers/block/ftide020.h | 104 +-- drivers/block/pata_bfin.c | 8 +- drivers/block/sata_dwc.c | 16 +- drivers/block/sata_dwc.h | 236 +++--- drivers/block/sata_sil.c | 12 +- drivers/block/sata_sil.h | 84 +-- drivers/block/sata_sil3114.c | 2 +- drivers/crypto/ace_sha.h | 190 ++--- drivers/crypto/fsl/desc.h | 14 +- drivers/crypto/fsl/desc_constr.h | 2 +- drivers/ddr/mvebu/ddr3_dfs.c | 18 +- drivers/ddr/mvebu/ddr3_init.c | 6 +- drivers/ddr/mvebu/ddr3_sdram.c | 4 +- drivers/ddr/mvebu/ddr3_spd.c | 8 +- drivers/gpio/mxs_gpio.c | 4 +- drivers/gpio/sandbox.c | 4 +- drivers/i2c/davinci_i2c.h | 48 +- drivers/i2c/i2c-uniphier-f.c | 42 +- drivers/i2c/i2c-uniphier.c | 18 +- drivers/i2c/i2c_core.c | 6 +- drivers/i2c/mxc_i2c.c | 28 +- drivers/i2c/omap24xx_i2c.c | 4 +- drivers/i2c/omap24xx_i2c.h | 68 +- drivers/i2c/pca9564_i2c.c | 2 +- drivers/i2c/sh_i2c.c | 22 +- drivers/i2c/sh_sh7734_i2c.c | 56 +- drivers/input/tegra-kbc.c | 10 +- drivers/mmc/mmc_spi.c | 16 +- drivers/mmc/mxcmmc.c | 88 +-- drivers/mmc/omap_hsmmc.c | 4 +- drivers/mmc/pxa_mmc_gen.c | 2 +- drivers/mmc/s3c_sdi.c | 46 +- drivers/mmc/sh_mmcif.h | 200 +++--- drivers/mmc/sh_sdhi.c | 2 +- drivers/mmc/tegra_mmc.c | 8 +- drivers/mtd/nand/atmel_nand_ecc.h | 40 +- drivers/mtd/nand/davinci_nand.c | 8 +- drivers/mtd/nand/kb9202_nand.c | 16 +- drivers/mtd/nand/kirkwood_nand.c | 4 +- drivers/mtd/nand/kmeter1_nand.c | 14 +- drivers/mtd/nand/mpc5121_nfc.c | 46 +- drivers/mtd/nand/mxc_nand.h | 52 +- drivers/mtd/nand/nand_base.c | 14 +- drivers/mtd/nand/nomadik.c | 4 +- drivers/mtd/nand/omap_gpmc.c | 2 +- drivers/mtd/nand/s3c2410_nand.c | 2 +- drivers/mtd/nand/tegra_nand.h | 128 ++-- drivers/mtd/onenand/onenand_spl.c | 2 +- drivers/mtd/spi/sandbox.c | 4 +- drivers/mtd/spi/sf_internal.h | 8 +- drivers/mtd/ubi/eba.c | 2 +- drivers/net/bcm-sf2-eth-gmac.h | 4 +- drivers/net/davinci_emac.c | 2 +- drivers/net/davinci_emac.h | 10 +- drivers/net/designware.h | 112 +-- drivers/net/dnet.c | 2 +- drivers/net/dnet.h | 106 +-- drivers/net/e1000.c | 36 +- drivers/net/eepro100.c | 6 +- drivers/net/ep93xx_eth.c | 4 +- drivers/net/ep93xx_eth.h | 2 +- drivers/net/ethoc.c | 64 +- drivers/net/fec_mxc.h | 12 +- drivers/net/ftgmac100.h | 154 ++-- drivers/net/ftmac100.h | 94 +-- drivers/net/ftmac110.h | 74 +- drivers/net/keystone_net.c | 2 +- drivers/net/ks8851_mll.h | 292 ++++---- drivers/net/mvgbe.h | 176 ++--- drivers/net/mvneta.c | 6 +- drivers/net/phy/micrel.c | 14 +- drivers/net/phy/mv88e61xx.c | 10 +- drivers/net/phy/vitesse.c | 10 +- drivers/net/sunxi_emac.c | 2 +- drivers/net/tsi108_eth.c | 94 +-- drivers/net/vsc9953.c | 4 +- drivers/net/xilinx_ll_temac.h | 116 +-- drivers/net/xilinx_ll_temac_fifo.h | 36 +- drivers/net/xilinx_ll_temac_sdma.h | 86 +-- drivers/pci/pci_tegra.c | 64 +- drivers/pci/pcie_imx.c | 10 +- drivers/power/as3722.c | 4 +- drivers/power/exynos-tmu.c | 22 +- drivers/qe/uec_phy.c | 4 +- drivers/qe/uec_phy.h | 54 +- drivers/rtc/ftrtc010.c | 10 +- drivers/rtc/imxdi.c | 28 +- drivers/rtc/m41t62.c | 18 +- drivers/rtc/mc146818.c | 4 +- drivers/rtc/pl031.c | 2 +- drivers/rtc/rv3029.c | 18 +- drivers/serial/altera_jtag_uart.c | 12 +- drivers/serial/altera_uart.c | 50 +- drivers/serial/arm_dcc.c | 12 +- drivers/serial/ns16550.c | 2 +- drivers/serial/opencores_yanu.c | 4 +- drivers/serial/serial_arc.c | 6 +- drivers/serial/serial_lpuart.c | 46 +- drivers/serial/serial_max3100.c | 20 +- drivers/serial/serial_pl01x_internal.h | 88 +-- drivers/serial/serial_pxa.c | 2 +- drivers/serial/serial_s5p.c | 4 +- drivers/serial/serial_stm32.c | 12 +- drivers/spi/altera_spi.c | 26 +- drivers/spi/atmel_spi.h | 52 +- drivers/spi/bfin_spi6xx.c | 8 +- drivers/spi/cadence_qspi_apb.c | 28 +- drivers/spi/designware_spi.c | 14 +- drivers/spi/exynos_spi.c | 4 +- drivers/spi/fsl_dspi.c | 2 +- drivers/spi/fsl_espi.c | 20 +- drivers/spi/fsl_qspi.c | 4 +- drivers/spi/ftssp010_spi.c | 50 +- drivers/spi/ich.c | 4 +- drivers/spi/mpc8xxx_spi.c | 2 +- drivers/spi/omap3_spi.h | 48 +- drivers/spi/sh_qspi.c | 16 +- drivers/spi/tegra114_spi.c | 64 +- drivers/spi/tegra20_sflash.c | 50 +- drivers/spi/tegra20_slink.c | 56 +- drivers/spi/ti_qspi.c | 10 +- drivers/spi/xilinx_spi.h | 70 +- drivers/spi/zynq_spi.c | 16 +- drivers/thermal/imx_thermal.c | 8 +- drivers/tpm/tpm_tis_lpc.c | 28 +- drivers/usb/dwc3/core.h | 160 ++--- drivers/usb/dwc3/dwc3-omap.c | 48 +- drivers/usb/dwc3/gadget.h | 20 +- drivers/usb/eth/asix88179.c | 156 ++-- drivers/usb/gadget/atmel_usba_udc.h | 34 +- drivers/usb/gadget/ci_udc.c | 4 +- drivers/usb/gadget/ci_udc.h | 38 +- drivers/usb/gadget/designware_udc.c | 16 +- drivers/usb/gadget/pxa27x_udc.c | 2 +- drivers/usb/host/dwc2.h | 484 ++++++------- drivers/usb/host/ehci-hcd.c | 6 +- drivers/usb/host/ehci-mx5.c | 48 +- drivers/usb/host/ehci-mx6.c | 8 +- drivers/usb/host/ehci-mxc.c | 52 +- drivers/usb/host/ehci-mxs.c | 4 +- drivers/usb/host/ehci-vf.c | 10 +- drivers/usb/host/ehci.h | 70 +- drivers/usb/host/isp116x.h | 136 ++-- drivers/usb/host/ohci-s3c24xx.c | 18 +- drivers/usb/host/ohci-s3c24xx.h | 54 +- drivers/usb/host/ohci.h | 56 +- drivers/usb/host/r8a66597.h | 10 +- drivers/usb/host/xhci-uniphier.c | 4 +- drivers/usb/host/xhci.h | 146 ++-- drivers/usb/musb-new/musb_core.h | 2 +- drivers/usb/musb-new/musb_regs.h | 6 +- drivers/usb/musb-new/omap2430.h | 14 +- drivers/usb/musb-new/sunxi.c | 2 +- drivers/usb/musb/am35x.c | 4 +- drivers/usb/musb/am35x.h | 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include/configs/at91sam9m10g45ek.h | 4 +- include/configs/at91sam9n12ek.h | 4 +- include/configs/at91sam9rlek.h | 4 +- include/configs/at91sam9x5ek.h | 4 +- include/configs/bf537-pnav.h | 4 +- include/configs/bf537-stamp.h | 4 +- include/configs/bf561-acvilon.h | 4 +- include/configs/br4.h | 4 +- include/configs/cam_enc_4xx.h | 2 +- include/configs/corvus.h | 4 +- include/configs/cpu9260.h | 4 +- include/configs/crownbay.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/db-mv784mp-gp.h | 2 +- include/configs/ethernut5.h | 6 +- include/configs/galileo.h | 2 +- include/configs/goflexhome.h | 8 +- include/configs/ids8313.h | 2 +- include/configs/io64.h | 2 +- include/configs/ip04.h | 4 +- include/configs/kilauea.h | 2 +- include/configs/km_kirkwood.h | 4 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/luan.h | 2 +- include/configs/lwmon5.h | 2 +- include/configs/maxbcm.h | 4 +- include/configs/meesc.h | 4 +- include/configs/minnowmax.h | 2 +- include/configs/mpc5121ads.h | 10 +- include/configs/mx51_efikamx.h | 2 +- include/configs/nas220.h | 8 +- include/configs/origen.h | 2 +- include/configs/otc570.h | 4 +- include/configs/pm9261.h | 6 +- include/configs/pm9263.h | 4 +- include/configs/pm9g45.h | 4 +- include/configs/pr1.h | 4 +- include/configs/qong.h | 4 +- include/configs/s5pc210_universal.h | 6 +- include/configs/sama5d3_xplained.h | 4 +- include/configs/sama5d3xek.h | 4 +- include/configs/sama5d4_xplained.h | 4 +- include/configs/sama5d4ek.h | 4 +- include/configs/sbc35_a9g20.h | 4 +- include/configs/siemens-am33x-common.h | 4 +- include/configs/smdkc100.h | 2 +- include/configs/snapper9260.h | 6 +- include/configs/stamp9g20.h | 4 +- include/configs/taurus.h | 6 +- include/configs/tegra-common.h | 2 +- include/configs/tny_a9260.h | 4 +- include/configs/trats.h | 6 +- include/configs/trats2.h | 6 +- include/configs/tricorder.h | 6 +- include/configs/tx25.h | 2 +- include/configs/usb_a9263.h | 4 +- include/configs/vct.h | 2 +- include/configs/versatile.h | 2 +- include/configs/vexpress_common.h | 14 +- include/configs/vf610twr.h | 2 +- include/configs/vl_ma2sc.h | 4 +- include/configs/x86-chromebook.h | 2 +- include/configs/xpedite517x.h | 4 +- include/configs/xpedite520x.h | 4 +- include/dialog_pmic.h | 20 +- include/dm/device.h | 12 +- include/dm/uclass.h | 2 +- include/dp83848.h | 96 +-- include/dt-bindings/pinctrl/am33xx.h | 6 +- include/dt-bindings/pinctrl/omap.h | 22 +- include/dwmmc.h | 90 +-- include/ec_commands.h | 46 +- include/faraday/ftahbc020s.h | 6 +- include/faraday/ftpci100.h | 8 +- include/faraday/ftpmu010.h | 86 +-- include/faraday/ftsdc010.h | 146 ++-- include/faraday/ftsdmc020.h | 22 +- include/faraday/ftsdmc021.h | 24 +- include/faraday/ftsmc020.h | 12 +- include/faraday/fttmr010.h | 42 +- include/faraday/ftwdt010_wdt.h | 12 +- include/fsl_ddr.h | 14 +- include/fsl_ddr_sdram.h | 2 +- include/fsl_debug_server.h | 2 +- include/fsl_memac.h | 20 +- include/fsl_pmic.h | 32 +- include/fsl_usb.h | 28 +- include/i2s.h | 4 +- include/libata.h | 208 +++--- include/linux/bitops.h | 1 + include/linux/edd.h | 24 +- include/linux/ethtool.h | 136 ++-- include/linux/mtd/fsmc_nand.h | 24 +- include/linux/mtd/nand.h | 22 +- include/linux/mtd/onenand_regs.h | 58 +- include/linux/mtd/samsung_onenand.h | 30 +- include/linux/screen_info.h | 2 +- include/linux/serial_reg.h | 36 +- include/linux/usb/cdc.h | 10 +- include/linux/usb/ch9.h | 52 +- include/linux/usb/dwc3.h | 22 +- include/linux/usb/xhci-omap.h | 40 +- include/mc13783.h | 96 +-- include/mc13892.h | 122 ++-- include/mc34704.h | 8 +- include/mmc.h | 62 +- include/mpc83xx.h | 38 +- include/mvebu_mmc.h | 178 ++--- include/nand.h | 4 +- include/netdev.h | 4 +- include/palmas.h | 22 +- include/power/as3722.h | 4 +- include/power/max17042_fg.h | 2 +- include/power/max77686_pmic.h | 10 +- include/power/max77693_fg.h | 2 +- include/power/max77693_pmic.h | 4 +- include/power/max8997_pmic.h | 26 +- include/power/max8998_pmic.h | 12 +- include/radeon.h | 262 +++---- include/sdhci.h | 18 +- include/search.h | 18 +- include/sh_pfc.h | 4 +- include/spi.h | 22 +- include/tsec.h | 6 +- include/tsi108.h | 8 +- include/twl4030.h | 36 +- include/twl6030.h | 70 +- include/usb/ehci-fsl.h | 92 +-- include/usb/fotg210.h | 264 +++---- include/usb/fusbh200.h | 26 +- include/usb/s3c_udc.h | 2 +- include/usb/ulpi.h | 96 +-- include/zfs/spa.h | 2 +- lib/lzma/LzmaDec.c | 4 +- lib/lzma/Types.h | 2 +- post/drivers/memory.c | 2 +- tools/ifdtool.c | 38 +- tools/mxsimage.c | 4 +- tools/mxsimage.h | 4 +- 773 files changed, 11020 insertions(+), 11019 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index e369e5a..1875424 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -9,14 +9,14 @@ #include /* Bit values in IC_CTRL */ -#define IC_CTRL_CACHE_DISABLE (1 << 0) +#define IC_CTRL_CACHE_DISABLE BIT(0) /* Bit values in DC_CTRL */ -#define DC_CTRL_CACHE_DISABLE (1 << 0) -#define DC_CTRL_INV_MODE_FLUSH (1 << 6) -#define DC_CTRL_FLUSH_STATUS (1 << 8) +#define DC_CTRL_CACHE_DISABLE BIT(0) +#define DC_CTRL_INV_MODE_FLUSH BIT(6) +#define DC_CTRL_FLUSH_STATUS BIT(8) #define CACHE_VER_NUM_MASK 0xF -#define SLC_CTRL_SB (1 << 2) +#define SLC_CTRL_SB BIT(2) int icache_status(void) { diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c index d7cab3b..ed18500 100644 --- a/arch/arc/lib/interrupts.c +++ b/arch/arc/lib/interrupts.c @@ -9,8 +9,8 @@ #include /* Bit values in STATUS32 */ -#define E1_MASK (1 << 1) /* Level 1 interrupts enable */ -#define E2_MASK (1 << 2) /* Level 2 interrupts enable */ +#define E1_MASK BIT(1) /* Level 1 interrupts enable */ +#define E2_MASK BIT(2) /* Level 2 interrupts enable */ int interrupt_init(void) { diff --git a/arch/arc/lib/timer.c b/arch/arc/lib/timer.c index a0acbbc..d20ecb8 100644 --- a/arch/arc/lib/timer.c +++ b/arch/arc/lib/timer.c @@ -6,7 +6,7 @@ #include -#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */ +#define NH_MODE BIT(1) /* Disable timer if CPU is halted */ int timer_init(void) { diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 3a81ce4..8729f27 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -18,8 +18,8 @@ #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ /* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_SWR BIT(15) /* Software reset */ +#define GPTCR_FRR BIT(9) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ #define GPTCR_TEN 1 /* Timer enable */ diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index bc98edd..6207806 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -261,7 +261,7 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART1_BAUD: case UART2_BAUD: case UART3_BAUD: - clk_sel = mpdr3 & (1 << 14); + clk_sel = mpdr3 & BIT(14); pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); @@ -269,7 +269,7 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; pdf = mpdr2 & 0x3F; - clk_sel = mpdr2 & (1 << 6); + clk_sel = mpdr2 & BIT(6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); @@ -277,13 +277,13 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case SSI2_BAUD: pre_pdf = (mpdr2 >> 27) & 0x7; pdf = (mpdr2 >> 8) & 0x3F; - clk_sel = mpdr2 & (1 << 6); + clk_sel = mpdr2 & BIT(6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case CSI_BAUD: - clk_sel = mpdr2 & (1 << 7); + clk_sel = mpdr2 & BIT(7); pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c index c2f239a..78a4e49 100644 --- a/arch/arm/cpu/arm920t/ep93xx/timer.c +++ b/arch/arm/cpu/arm920t/ep93xx/timer.c @@ -18,8 +18,8 @@ #include #include -#define TIMER_CLKSEL (1 << 3) -#define TIMER_ENABLE (1 << 7) +#define TIMER_CLKSEL BIT(3) +#define TIMER_ENABLE BIT(7) #define TIMER_FREQ 508469 /* ticks / second */ #define TIMER_MAX_VAL 0xFFFFFFFF diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c index 3701c5d..17c946f 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c @@ -74,10 +74,10 @@ ulong get_HCLK(void) case 2: return get_FCLK() / 2; case 4: - return (readl(&clk_power->camdivn) & (1 << 9)) ? + return (readl(&clk_power->camdivn) & BIT(9)) ? get_FCLK() / 8 : get_FCLK() / 4; case 6: - return (readl(&clk_power->camdivn) & (1 << 8)) ? + return (readl(&clk_power->camdivn) & BIT(8)) ? get_FCLK() / 6 : get_FCLK() / 3; } #else diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 8912098..b9e6b68 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -205,7 +205,7 @@ int cpu_eth_init(bd_t *bis) ulong val; val = readl(&ccm->cgr0); - val |= (1 << 23); + val |= BIT(23); writel(val, &ccm->cgr0); return fecmxc_initialize(bis); } diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c index 40fe2aa..32856ac 100644 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ b/arch/arm/cpu/arm926ejs/mx27/timer.c @@ -22,8 +22,8 @@ #include /* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 8) /* Freerun / restart */ +#define GPTCR_SWR BIT(15) /* Software reset */ +#define GPTCR_FRR BIT(8) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */ #define GPTCR_TEN 1 /* Timer enable */ diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c index 96bd32f..68cfff8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c @@ -58,7 +58,7 @@ void mxs_lradc_enable_batt_measurement(void) writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set); /* Configure the channel. */ - writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, + writel(BIT(7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, ®s->hw_lradc_ctrl2_clr); writel(0xffffffff, ®s->hw_lradc_ch7_clr); clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK); @@ -68,8 +68,8 @@ void mxs_lradc_enable_batt_measurement(void) writel(1 << 7, ®s->hw_lradc_ctrl0_set); /* Start the channel sampling. */ - writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | - ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | + writel((BIT(7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | + (BIT(3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | 100, ®s->hw_lradc_delay3); writel(0xffffffff, ®s->hw_lradc_ch7_clr); diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a744e5d..83400d5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -135,7 +135,7 @@ static void initialize_dram_values(void) * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last * element to be set */ - writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); + writel(BIT(24), MXS_DRAM_BASE + (4 * 8)); } #endif @@ -282,7 +282,7 @@ static void mx23_mem_init(void) */ /* Clear START and SREFRESH bit from DRAM_CTL8 */ - clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); + clrbits_le32(MXS_DRAM_BASE + 0x20, BIT(16) | BIT(8)); initialize_dram_values(); @@ -293,7 +293,7 @@ static void mx23_mem_init(void) /* Wait for EMI_STAT bit DRAM_HALTED */ for (;;) { - if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) + if (!(readl(MXS_EMI_BASE + 0x10) & BIT(1))) break; early_delay(1000); } @@ -335,7 +335,7 @@ static void mx28_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x40, 1); /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ - while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) + while (!(readl(MXS_DRAM_BASE + 0xe8) & BIT(20))) ; } #endif diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 67bef23..d520b18 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -129,10 +129,10 @@ int cpu_mmc_init(bd_t *bis) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* USB 2.0 PHY Control */ -#define CM_PHY_PWRDN (1 << 0) -#define CM_PHY_OTG_PWRDN (1 << 1) -#define OTGVDET_EN (1 << 19) -#define OTGSESSENDEN (1 << 20) +#define CM_PHY_PWRDN BIT(0) +#define CM_PHY_OTG_PWRDN BIT(1) +#define OTGVDET_EN BIT(19) +#define OTGSESSENDEN BIT(20) static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) { @@ -241,7 +241,7 @@ static void rtc32k_enable(void) writel(RTC_KICK1R_WE, &rtc->kick1r); /* Enable the RTC 32K OSC by setting bits 3 and 6. */ - writel((1 << 3) | (1 << 6), &rtc->osc); + writel(BIT(3) | BIT(6), &rtc->osc); } #endif diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 9b5a47b..512fb1e 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -51,31 +51,31 @@ /* ADPLLJ register values */ #define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ #define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) -#define ADPLLJ_CLKCTRL_IDLE (1 << 23) -#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) -#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) -#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) -#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) -#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) -#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) -#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) +#define ADPLLJ_CLKCTRL_CLKDCOLDOEN BIT(29) +#define ADPLLJ_CLKCTRL_IDLE BIT(23) +#define ADPLLJ_CLKCTRL_CLKOUTEN BIT(20) +#define ADPLLJ_CLKCTRL_CLKOUTLDOEN BIT(19) +#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ BIT(17) +#define ADPLLJ_CLKCTRL_LPMODE BIT(12) +#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN BIT(11) +#define ADPLLJ_CLKCTRL_REGM4XEN BIT(10) +#define ADPLLJ_CLKCTRL_TINITZ BIT(0) #define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ ADPLLJ_CLKCTRL_CLKOUTEN | \ ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) -#define ADPLLJ_STATUS_PHASELOCK (1 << 10) -#define ADPLLJ_STATUS_FREQLOCK (1 << 9) +#define ADPLLJ_STATUS_PHASELOCK BIT(10) +#define ADPLLJ_STATUS_FREQLOCK BIT(9) #define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ ADPLLJ_STATUS_FREQLOCK) -#define ADPLLJ_STATUS_BYPASSACK (1 << 8) -#define ADPLLJ_STATUS_BYPASS (1 << 0) +#define ADPLLJ_STATUS_BYPASSACK BIT(8) +#define ADPLLJ_STATUS_BYPASS BIT(0) #define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ ADPLLJ_STATUS_BYPASS) -#define ADPLLJ_TENABLE_ENB (1 << 0) -#define ADPLLJ_TENABLEDIV_ENB (1 << 0) +#define ADPLLJ_TENABLE_ENB BIT(0) +#define ADPLLJ_TENABLEDIV_ENB BIT(0) #define ADPLLJ_M2NDIV_M2SHIFT 16 diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index df4d473..1e3af95 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1008,7 +1008,7 @@ static unsigned long exynos5420_get_lcd_clk(void) * 1: SCLK_SPLL */ sel = readl(&clk->src_disp10); - sel &= (1 << 4); + sel &= BIT(4); if (sel) sclk = get_pll_clk(SPLL); diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h index 5235abb..f518332 100644 --- a/arch/arm/cpu/armv7/exynos/common_setup.h +++ b/arch/arm/cpu/armv7/exynos/common_setup.h @@ -49,14 +49,14 @@ void sdelay(unsigned long); enum l2_cache_params { CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0), CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0), - CACHE_DISABLE_CLEAN_EVICT = (1 << 3), - CACHE_DATA_RAM_SETUP = (1 << 5), + CACHE_DISABLE_CLEAN_EVICT = BIT(3), + CACHE_DATA_RAM_SETUP = BIT(5), CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6), CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6), - CACHE_ENABLE_HAZARD_DETECT = (1 << 7), - CACHE_TAG_RAM_SETUP = (1 << 9), - CACHE_ECC_AND_PARITY = (1 << 21), - CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) + CACHE_ENABLE_HAZARD_DETECT = BIT(7), + CACHE_TAG_RAM_SETUP = BIT(9), + CACHE_ECC_AND_PARITY = BIT(21), + CACHE_ENABLE_FORCE_L2_LOGIC = BIT(27) }; diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h index 9f29d94..9924227 100644 --- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h @@ -396,12 +396,12 @@ /* DMC */ #define DIRECT_CMD_NOP 0x07000000 #define DIRECT_CMD_ZQ 0x0a000000 -#define DIRECT_CMD_CHIP1_SHIFT (1 << 20) +#define DIRECT_CMD_CHIP1_SHIFT BIT(20) #define MEM_TIMINGS_MSR_COUNT 4 -#define CTRL_START (1 << 0) -#define CTRL_DLL_ON (1 << 1) -#define AREF_EN (1 << 5) -#define DRV_TYPE (1 << 6) +#define CTRL_START BIT(0) +#define CTRL_DLL_ON BIT(1) +#define AREF_EN BIT(5) +#define DRV_TYPE BIT(6) struct mem_timings { unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -481,9 +481,9 @@ struct mem_timings { | CTRL_ZQ_FORCE_IMPP | CTRL_DCC) #define ASYNC (0 << 0) -#define CLK_RATIO (1 << 1) -#define DIV_PIPE (1 << 3) -#define AWR_ON (1 << 4) +#define CLK_RATIO BIT(1) +#define DIV_PIPE BIT(3) +#define AWR_ON BIT(4) #define AREF_DISABLE (0 << 5) #define DRV_TYPE_DISABLE (0 << 6) #define CHIP0_NOT_EMPTY (0 << 8) @@ -503,10 +503,10 @@ struct mem_timings { #define DPWRDN_TYPE (0 << 3) #define TP_DISABLE (0 << 4) #define DSREF_DIABLE (0 << 5) -#define ADD_LAT_PALL (1 << 6) +#define ADD_LAT_PALL BIT(6) #define MEM_TYPE_DDR3 (0x6 << 8) #define MEM_WIDTH_32 (0x2 << 12) -#define NUM_CHIP_2 (1 << 16) +#define NUM_CHIP_2 BIT(16) #define BL_8 (0x3 << 20) #define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\ | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\ @@ -517,7 +517,7 @@ struct mem_timings { #define CHIP_BANK_8 (0x3 << 0) #define CHIP_ROW_14 (0x2 << 4) #define CHIP_COL_10 (0x3 << 8) -#define CHIP_MAP_INTERLEAVED (1 << 12) +#define CHIP_MAP_INTERLEAVED BIT(12) #define CHIP_MASK (0xe0 << 16) #ifdef CONFIG_MIU_LINEAR #define CHIP0_BASE (0x40 << 24) @@ -537,7 +537,7 @@ struct mem_timings { #define CTRL_OFF (0 << 0) #define CTRL_DLL_OFF (0 << 1) #define CTRL_HALF (0 << 2) -#define CTRL_DFDQS (1 << 3) +#define CTRL_DFDQS BIT(3) #define DQS_DELAY (0 << 4) #define CTRL_START_POINT (0x10 << 8) #define CTRL_INC (0x10 << 16) @@ -548,9 +548,9 @@ struct mem_timings { #define CTRL_SHIFTC (0x6 << 0) #define CTRL_REF (8 << 4) -#define CTRL_SHGATE (1 << 29) -#define TERM_READ_EN (1 << 30) -#define TERM_WRITE_EN (1 << 31) +#define CTRL_SHGATE BIT(29) +#define TERM_READ_EN BIT(30) +#define TERM_WRITE_EN BIT(31) #define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\ | TERM_READ_EN | TERM_WRITE_EN) diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 9073f50..fbe2e9f 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -17,7 +17,7 @@ #define ENABLE_BIT 0x1 #define DISABLE_BIT 0x0 -#define CA_SWAP_EN (1 << 0) +#define CA_SWAP_EN BIT(0) /* Set PLL */ #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) @@ -28,7 +28,7 @@ #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2) #define DMC_MEMCONTROL_TP_DISABLE (0 << 4) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) -#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) +#define DMC_MEMCONTROL_DSREF_ENABLE BIT(5) #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) @@ -38,7 +38,7 @@ #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12) #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 BIT(16) #define DMC_MEMCONTROL_BL_8 (3 << 20) #define DMC_MEMCONTROL_BL_4 (2 << 20) @@ -46,12 +46,12 @@ #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 BIT(25) #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) /* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED BIT(12) #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) @@ -83,27 +83,27 @@ #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 -#define DFI_INIT_START (1 << 28) -#define EMPTY (1 << 8) -#define AREF_EN (1 << 5) +#define DFI_INIT_START BIT(28) +#define EMPTY BIT(8) +#define AREF_EN BIT(5) -#define DFI_INIT_COMPLETE_CHO (1 << 2) -#define DFI_INIT_COMPLETE_CH1 (1 << 3) +#define DFI_INIT_COMPLETE_CHO BIT(2) +#define DFI_INIT_COMPLETE_CH1 BIT(3) -#define RDLVL_COMPLETE_CHO (1 << 14) -#define RDLVL_COMPLETE_CH1 (1 << 15) +#define RDLVL_COMPLETE_CHO BIT(14) +#define RDLVL_COMPLETE_CH1 BIT(15) -#define CLK_STOP_EN (1 << 0) -#define DPWRDN_EN (1 << 1) -#define DSREF_EN (1 << 5) +#define CLK_STOP_EN BIT(0) +#define DPWRDN_EN BIT(1) +#define DSREF_EN BIT(5) /* COJCONTROL register bit fields */ #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) -#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3) +#define DMC_CONCONTROL_IO_PD_CON_ENABLE BIT(3) #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) -#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5) +#define DMC_CONCONTROL_AREF_EN_ENABLE BIT(5) #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) -#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) +#define DMC_CONCONTROL_EMPTY_ENABLE BIT(8) #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) @@ -145,24 +145,24 @@ /* CLK_DIV_SYSLFT */ #define CLK_DIV_SYSLFT_VAL 0x00000311 -#define MUX_APLL_SEL_MASK (1 << 0) -#define MUX_MPLL_SEL_MASK (1 << 8) +#define MUX_APLL_SEL_MASK BIT(0) +#define MUX_MPLL_SEL_MASK BIT(8) #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) -#define MUX_CPLL_SEL_MASK (1 << 8) -#define MUX_EPLL_SEL_MASK (1 << 12) -#define MUX_VPLL_SEL_MASK (1 << 16) -#define MUX_GPLL_SEL_MASK (1 << 28) -#define MUX_BPLL_SEL_MASK (1 << 0) -#define MUX_HPM_SEL_MASK (1 << 20) -#define HPM_SEL_SCLK_MPLL (1 << 21) -#define PLL_LOCKED (1 << 29) -#define APLL_CON0_LOCKED (1 << 29) -#define MPLL_CON0_LOCKED (1 << 29) -#define BPLL_CON0_LOCKED (1 << 29) -#define CPLL_CON0_LOCKED (1 << 29) -#define EPLL_CON0_LOCKED (1 << 29) -#define GPLL_CON0_LOCKED (1 << 29) -#define VPLL_CON0_LOCKED (1 << 29) +#define MUX_CPLL_SEL_MASK BIT(8) +#define MUX_EPLL_SEL_MASK BIT(12) +#define MUX_VPLL_SEL_MASK BIT(16) +#define MUX_GPLL_SEL_MASK BIT(28) +#define MUX_BPLL_SEL_MASK BIT(0) +#define MUX_HPM_SEL_MASK BIT(20) +#define HPM_SEL_SCLK_MPLL BIT(21) +#define PLL_LOCKED BIT(29) +#define APLL_CON0_LOCKED BIT(29) +#define MPLL_CON0_LOCKED BIT(29) +#define BPLL_CON0_LOCKED BIT(29) +#define CPLL_CON0_LOCKED BIT(29) +#define EPLL_CON0_LOCKED BIT(29) +#define GPLL_CON0_LOCKED BIT(29) +#define VPLL_CON0_LOCKED BIT(29) #define CLK_REG_DISABLE 0x0 #define TOP2_VAL 0x0110000 @@ -211,7 +211,7 @@ #define CLK_DIV_ISP2_VAL 0x1 /* CLK_SRC_KFC */ -#define SRC_KFC_HPM_SEL (1 << 15) +#define SRC_KFC_HPM_SEL BIT(15) /* CLK_SRC_KFC */ #define CLK_SRC_KFC_VAL 0x00008001 @@ -235,7 +235,7 @@ #define CLK_DIV_DISP1_0_FIMD1 (2 << 0) /* CLK_GATE_IP_DISP1 */ -#define CLK_GATE_DP1_ALLOW (1 << 4) +#define CLK_GATE_DP1_ALLOW BIT(4) /* AUDIO CLK SEL */ #define AUDIO0_SEL_EPLL (0x6 << 28) @@ -244,18 +244,18 @@ #define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) /* CLK_SRC_CDREX */ -#define MUX_MCLK_CDR_MSPLL (1 << 4) -#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define MUX_MCLK_CDR_MSPLL BIT(4) +#define MUX_BPLL_SEL_FOUTBPLL BIT(0) #define BPLL_SEL_MASK 0x7 #define FOUTBPLL 2 -#define DDR3PHY_CTRL_PHY_RESET (1 << 0) +#define DDR3PHY_CTRL_PHY_RESET BIT(0) #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) #define PHY_CON0_RESET_VAL 0x17020a40 -#define P0_CMD_EN (1 << 14) -#define BYTE_RDLVL_EN (1 << 13) -#define CTRL_SHGATE (1 << 8) +#define P0_CMD_EN BIT(14) +#define BYTE_RDLVL_EN BIT(13) +#define CTRL_SHGATE BIT(8) #define PHY_CON1_RESET_VAL 0x09210100 #define RDLVL_PASS_ADJ_VAL 0x6 @@ -264,24 +264,24 @@ #define READ_LEVELLING_DDR3 0x0100 #define PHY_CON2_RESET_VAL 0x00010004 -#define INIT_DESKEW_EN (1 << 6) -#define DLL_DESKEW_EN (1 << 12) -#define RDLVL_GATE_EN (1 << 24) -#define RDLVL_EN (1 << 25) +#define INIT_DESKEW_EN BIT(6) +#define DLL_DESKEW_EN BIT(12) +#define RDLVL_GATE_EN BIT(24) +#define RDLVL_EN BIT(25) #define RDLVL_INCR_ADJ (0x1 << 16) /* DREX_PAUSE */ -#define DREX_PAUSE_EN (1 << 0) +#define DREX_PAUSE_EN BIT(0) -#define BYPASS_EN (1 << 22) +#define BYPASS_EN BIT(22) /* MEMMORY VAL */ #define PHY_CON0_VAL 0x17021A00 #define PHY_CON12_RESET_VAL 0x10100070 #define PHY_CON12_VAL 0x10107F50 -#define CTRL_START (1 << 6) -#define CTRL_DLL_ON (1 << 5) +#define CTRL_START BIT(6) +#define CTRL_DLL_ON BIT(5) #define CTRL_LOCK_COARSE_OFFSET 10 #define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) #define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ @@ -319,10 +319,10 @@ /* ZQ Configurations */ #define PHY_CON16_RESET_VAL 0x08000304 -#define ZQ_CLK_EN (1 << 27) -#define ZQ_CLK_DIV_EN (1 << 18) -#define ZQ_MANUAL_STR (1 << 1) -#define ZQ_DONE (1 << 0) +#define ZQ_CLK_EN BIT(27) +#define ZQ_CLK_DIV_EN BIT(18) +#define ZQ_MANUAL_STR BIT(1) +#define ZQ_DONE BIT(0) #define ZQ_MODE_DDS_OFFSET 24 #define CTRL_RDLVL_GATE_ENABLE 1 @@ -371,18 +371,18 @@ #define PHY_CON32_RESET_VAL 0x0 #define PHY_CON33_RESET_VAL 0x0 -#define SL_DLL_DYN_CON_EN (1 << 1) -#define FP_RESYNC (1 << 3) -#define CTRL_START (1 << 6) +#define SL_DLL_DYN_CON_EN BIT(1) +#define FP_RESYNC BIT(3) +#define CTRL_START BIT(6) -#define DMC_AREF_EN (1 << 5) -#define DMC_CONCONTROL_EMPTY (1 << 8) -#define DFI_INIT_START (1 << 28) +#define DMC_AREF_EN BIT(5) +#define DMC_CONCONTROL_EMPTY BIT(8) +#define DFI_INIT_START BIT(28) #define DMC_MEMCONTROL_VAL 0x00312700 -#define CLK_STOP_EN (1 << 0) -#define DPWRDN_EN (1 << 1) -#define DSREF_EN (1 << 5) +#define CLK_STOP_EN BIT(0) +#define DPWRDN_EN BIT(1) +#define DSREF_EN BIT(5) #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 #define MEMBASECONFIG_CHIP_MASK_OFFSET 0 @@ -398,25 +398,25 @@ #define TIMINGROW_VAL 0x345A8692 #define TIMINGDATA_VAL 0x3630065C #define TIMINGPOWER_VAL 0x50380336 -#define DFI_INIT_COMPLETE (1 << 3) +#define DFI_INIT_COMPLETE BIT(3) #define BRBRSVCONTROL_VAL 0x00000033 #define BRBRSVCONFIG_VAL 0x88778877 /* Clock Gating Control (CGCONTROL) register */ -#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ -#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ -#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ -#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ +#define MEMIF_CG_EN BIT(3) /* Memory interface clock gating */ +#define SCG_CG_EN BIT(2) /* Scheduler clock gating */ +#define BUSIF_WR_CG_EN BIT(1) /* Bus interface write channel clock gating */ +#define BUSIF_RD_CG_EN BIT(0) /* Bus interface read channel clock gating */ #define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) /* DMC PHY Control0 register */ #define PHY_CONTROL0_RESET_VAL 0x0 -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ +#define MEM_TERM_EN BIT(31) /* Termination enable for memory */ +#define PHY_TERM_EN BIT(30) /* Termination enable for PHY */ +#define DMC_CTRL_SHGATE BIT(29) /* Duration of DQS gating signal */ +#define FP_RSYNC BIT(3) /* Force DLL resyncronization */ /* Driver strength for CK, CKE, CS & CA */ #define IMP_OUTPUT_DRV_40_OHM 0x5 @@ -694,7 +694,7 @@ #define CLK_SRC_DISP1_0_VAL 0x6 #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE -#define APLL_FOUT (1 << 0) +#define APLL_FOUT BIT(0) #define KPLL_FOUT NOT_AVAILABLE #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE @@ -879,8 +879,8 @@ #define CLK_SRC_DISP1_0_VAL 0x10666600 #define CLK_DIV_DISP1_0_VAL 0x01050211 -#define APLL_FOUT (1 << 0) -#define KPLL_FOUT (1 << 0) +#define APLL_FOUT BIT(0) +#define KPLL_FOUT BIT(0) #define CLK_DIV_CPERI1_VAL 0x3f3f0000 #endif diff --git a/arch/arm/cpu/armv7/exynos/sec_boot.S b/arch/arm/cpu/armv7/exynos/sec_boot.S index dfc3455..cfff223 100644 --- a/arch/arm/cpu/armv7/exynos/sec_boot.S +++ b/arch/arm/cpu/armv7/exynos/sec_boot.S @@ -102,7 +102,7 @@ _gic_state: /* Read the current cpu state */ ldr r10, [r0, r7, lsl #2] svc_entry: - tst r10, #(1 << 4) + tst r10, #BIT(4) adrne r0, _switch_addr bne wait_for_addr /* Clear INFORM1 */ @@ -114,7 +114,7 @@ svc_entry: /* Get INFORM0 */ ldrne r1, =(0x10040000 + 0x800) ldrne pc, [r1] - tst r10, #(1 << 0) + tst r10, #BIT(0) ldrne pc, =0x23e00000 adr r0, _hotplug_addr wait_for_addr: diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index c7f943e..58bbe78 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -151,7 +151,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) } for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { - todo = min(uboot_size - upto, (unsigned int)(1 << 15)); + todo = min(uboot_size - upto, (unsigned int)BIT(15)); spi_rx_tx(regs, todo, (void *)(uboot_addr), (void *)(SPI_FLASH_UBOOT_POS), i); } diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c index ad12445..2a936ed 100644 --- a/arch/arm/cpu/armv7/exynos/system.c +++ b/arch/arm/cpu/armv7/exynos/system.c @@ -42,7 +42,7 @@ static void exynos4_set_system_display(void) * 1: FIMD Bypass */ cfg = readl(&sysreg->display_ctrl); - cfg |= (1 << 1); + cfg |= BIT(1); writel(cfg, &sysreg->display_ctrl); } @@ -58,7 +58,7 @@ static void exynos5_set_system_display(void) * 1: FIMD Bypass */ cfg = readl(&sysreg->disp1blk_cfg); - cfg |= (1 << 15); + cfg |= BIT(15); writel(cfg, &sysreg->disp1blk_cfg); } diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 1a640bb..46ceaf0 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -38,23 +38,23 @@ DECLARE_GLOBAL_DATA_PTR; #define PMD_ATTRINDX(t) ((t) << 2) /* Section */ -#define PMD_SECT_AF (1 << 10) +#define PMD_SECT_AF BIT(10) #define BLOCK_SIZE_L1 (1UL << 30) #define BLOCK_SIZE_L2 (1UL << 21) /* TTBCR flags */ -#define TTBCR_EAE (1 << 31) +#define TTBCR_EAE BIT(31) #define TTBCR_T0SZ(x) ((x) << 0) #define TTBCR_T1SZ(x) ((x) << 16) #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) #define TTBCR_IRGN0_NC (0 << 8) -#define TTBCR_IRGN0_WBWA (1 << 8) +#define TTBCR_IRGN0_WBWA BIT(8) #define TTBCR_IRGN0_WT (2 << 8) #define TTBCR_IRGN0_WBNWA (3 << 8) #define TTBCR_IRGN0_MASK (3 << 8) #define TTBCR_ORGN0_NC (0 << 10) -#define TTBCR_ORGN0_WBWA (1 << 10) +#define TTBCR_ORGN0_WBWA BIT(10) #define TTBCR_ORGN0_WT (2 << 10) #define TTBCR_ORGN0_WBNWA (3 << 10) #define TTBCR_ORGN0_MASK (3 << 10) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index f5bc672..9afabcd 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -16,7 +16,7 @@ .macro init_arm_erratum /* ARM erratum ID #468414 */ mrc 15, 0, r1, c1, c0, 1 - orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + orr r1, r1, #BIT(5) /* enable L1NEON bit */ mcr 15, 0, r1, c1, c0, 1 .endm diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e..5065f35 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -675,8 +675,8 @@ int enable_pcie_clock(void) * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important * for PCI express link that is clocked from the i.MX6. */ -#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) -#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN BIT(12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN BIT(10) #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index fef2231..60bcf79 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -242,7 +242,7 @@ void mx6sdl_dram_iocfg(unsigned width, * section titled MMDC initialization */ #define MR(val, ba, cmd, cs1) \ - ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) + ((val << 16) | BIT(15) | (cmd << 4) | (cs1 << 3) | ba) #ifdef CONFIG_MX6SX #define MMDC1(entry, value) do {} while (0) #else @@ -460,19 +460,19 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpodtctrl, val); /* complete calibration */ - val = (1 << 11); /* Force measurement on delay-lines */ + val = BIT(11); /* Force measurement on delay-lines */ mmdc0->mpmur0 = val; if (sysinfo->dsize > 1) MMDC1(mpmur0, val); /* Step 1: configuration request */ - mmdc0->mdscr = (u32)(1 << 15); /* config request */ + mmdc0->mdscr = (u32)BIT(15); /* config request */ /* Step 2: Timing configuration */ mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | (tfaw << 4) | tcl; mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | - (tras << 16) | (1 << 15) /* trpa */ | + (tras << 16) | BIT(15) /* trpa */ | (twr << 9) | (tmrd << 5) | tcwl; mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | @@ -496,7 +496,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, coladdr += 1; mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ (coladdr - 9) << 20 | /* COL */ - (1 << 19) | /* Burst Length = 8 for DDR3 */ + BIT(19) | /* Burst Length = 8 for DDR3 */ (sysinfo->dsize << 16); /* DDR data bus size */ /* Step 6: Perform ZQ calibration */ @@ -506,7 +506,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 7: Enable MMDC with desired chip select */ - mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ + mmdc0->mdctl |= BIT(31) | /* SDE_0 for CS0 */ ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ /* Step 8: Write Mode Registers to Init DDR3 devices */ @@ -523,11 +523,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdscr = MR(val, 1, 3, cs); /* MR0 */ val = ((tcl - 1) << 4) | /* CAS */ - (1 << 8) | /* DLL Reset */ + BIT(8) | /* DLL Reset */ ((twr - 3) << 9); /* Write Recovery */ mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */ - val = (1 << 10); + val = BIT(10); mmdc0->mdscr = MR(val, 0, 4, cs); } @@ -548,7 +548,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ + mmdc0->mdref = BIT(14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ /* Step 13: Deassert config request - init complete */ diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd34138..d64f8f8 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -405,7 +405,7 @@ void boot_mode_apply(unsigned cfg_val) if (cfg_val) reg |= 1 << 28; else - reg &= ~(1 << 28); + reg &= ~BIT(28); writel(reg, &psrc->gpr10); } /* diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index fc4290c..4e91592 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -64,7 +64,7 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, writel(gpmc_config[5], &cs->config6); /* Enable the config */ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); + BIT(6)), &cs->config7); sdelay(2000); } diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c index c736fa3..f91f263 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c @@ -533,7 +533,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) * be related to periodic impedance re-calibration. This particular * magic value is borrowed from the Allwinner boot0 bootloader, and * using it helps to avoid troubles */ - writel((1 << 24) | (1 << 1), &dram->zqcr1); + writel(BIT(24) | BIT(1), &dram->zqcr1); #endif /* Needed at least for sun5i, because it does not self clear there */ diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 5dbbf61..0e5712e 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -275,7 +275,7 @@ static void mctl_com_init(struct dram_sun6i_para *para) MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); /* Unknown magic performed by boot0 */ - setbits_le32(&mctl_com->dbgcr, (1 << 6)); + setbits_le32(&mctl_com->dbgcr, BIT(6)); if (para->chan == 1) { /* Shutdown channel 1 */ diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index e0a524e..27cbb55 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -98,7 +98,7 @@ psci_fiq_enter: add r11, r11, r8 1: ldr r10, [r11, #0x48] - tst r10, #(1 << 2) + tst r10, #BIT(2) bne 2f timer_wait r10, ONE_MS b 1b @@ -263,7 +263,7 @@ _sunxi_cpu_entry: .globl psci_cpu_off psci_cpu_off: mrc p15, 0, r0, c1, c0, 0 @ SCTLR - bic r0, r0, #(1 << 2) @ Clear C bit + bic r0, r0, #BIT(2) @ Clear C bit mcr p15, 0, r0, c1, c0, 0 @ SCTLR isb dsb @@ -273,7 +273,7 @@ psci_cpu_off: clrex @ Why??? mrc p15, 0, r0, c1, c0, 1 @ ACTLR - bic r0, r0, #(1 << 6) @ Clear SMP bit + bic r0, r0, #BIT(6) @ Clear SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR isb dsb @@ -295,7 +295,7 @@ psci_arch_init: movt r4, #(GICD_BASE >> 16) ldr r5, [r4, #GICD_IGROUPRn] - bic r5, r5, #(1 << 15) @ SGI15 as Group-0 + bic r5, r5, #BIT(15) @ SGI15 as Group-0 str r5, [r4, #GICD_IGROUPRn] mov r5, #0 @ Set SGI15 priority to 0 @@ -307,7 +307,7 @@ psci_arch_init: str r5, [r4, #GICC_PMR] @ Be cool with non-secure ldr r5, [r4, #GICC_CTLR] - orr r5, r5, #(1 << 3) @ Switch FIQEn on + orr r5, r5, #BIT(3) @ Switch FIQEn on str r5, [r4, #GICC_CTLR] mrc p15, 0, r5, c1, c1, 0 @ Read SCR diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c index a0e9604..41717a4 100644 --- a/arch/arm/cpu/armv7/sunxi/usbc.c +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -31,10 +31,10 @@ #define SUNXI_USB_CSR 0x404 #define SUNXI_USB_PASSBY_EN 1 -#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) -#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) -#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) -#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) +#define SUNXI_EHCI_AHB_ICHR8_EN BIT(10) +#define SUNXI_EHCI_AHB_INCR4_BURST_EN BIT(9) +#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN BIT(8) +#define SUNXI_EHCI_ULPI_BYPASS_EN BIT(0) static struct sunxi_usbc_hcd { struct usb_hcd *hcd; diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index 26ffdc2..8a46c6f 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -22,11 +22,11 @@ /* CPU mailbox registers */ #define PRCMU_I2C_WRITE(slave) \ - (((slave) << 1) | I2CWRITE | (1 << 6)) + (((slave) << 1) | I2CWRITE | BIT(6)) #define PRCMU_I2C_READ(slave) \ - (((slave) << 1) | I2CREAD | (1 << 6)) + (((slave) << 1) | I2CREAD | BIT(6)) -#define I2C_MBOX_BIT (1 << 5) +#define I2C_MBOX_BIT BIT(5) static int prcmu_is_ready(void) { @@ -99,7 +99,7 @@ int prcmu_i2c_read(u8 reg, u16 slave) /* prepare the data for mailbox 5 */ writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(BIT(3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); writeb(slave, PRCM_REQ_MB5_I2CSLAVE); writeb(0, PRCM_REQ_MB5_I2CVAL); @@ -155,7 +155,7 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) /* prepare the data for mailbox 5 */ writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(BIT(3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); writeb(slave, PRCM_REQ_MB5_I2CSLAVE); writeb(reg_data, PRCM_REQ_MB5_I2CVAL); @@ -187,7 +187,7 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) void u8500_prcmu_enable(u32 *reg) { - writel(readl(reg) | (1 << 8), reg); + writel(readl(reg) | BIT(8), reg); } void db8500_prcmu_init(void) diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c index d2885dc..7e78083 100644 --- a/arch/arm/cpu/armv7/zynq/clk.c +++ b/arch/arm/cpu/armv7/zynq/clk.c @@ -19,7 +19,7 @@ /* Register bitfield defines */ #define PLLCTRL_FBDIV_MASK 0x7f000 #define PLLCTRL_FBDIV_SHIFT 12 -#define PLLCTRL_BPFORCE_MASK (1 << 4) +#define PLLCTRL_BPFORCE_MASK BIT(4) #define PLLCTRL_PWRDWN_MASK 2 #define PLLCTRL_PWRDWN_SHIFT 1 #define PLLCTRL_RESET_MASK 1 diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index 2eded1f..c33292d 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -12,19 +12,19 @@ #include #include -#define RCC_CR_HSION (1 << 0) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_HSION BIT(0) +#define RCC_CR_HSEON BIT(16) +#define RCC_CR_HSERDY BIT(17) +#define RCC_CR_HSEBYP BIT(18) +#define RCC_CR_CSSON BIT(19) +#define RCC_CR_PLLON BIT(24) +#define RCC_CR_PLLRDY BIT(25) #define RCC_PLLCFGR_PLLM_MASK 0x3F #define RCC_PLLCFGR_PLLN_MASK 0x7FC0 #define RCC_PLLCFGR_PLLP_MASK 0x30000 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000 -#define RCC_PLLCFGR_PLLSRC (1 << 22) +#define RCC_PLLCFGR_PLLSRC BIT(22) #define RCC_PLLCFGR_PLLN_SHIFT 6 #define RCC_PLLCFGR_PLLP_SHIFT 16 #define RCC_PLLCFGR_PLLQ_SHIFT 24 @@ -32,14 +32,14 @@ #define RCC_CFGR_AHB_PSC_MASK 0xF0 #define RCC_CFGR_APB1_PSC_MASK 0x1C00 #define RCC_CFGR_APB2_PSC_MASK 0xE000 -#define RCC_CFGR_SW0 (1 << 0) -#define RCC_CFGR_SW1 (1 << 1) +#define RCC_CFGR_SW0 BIT(0) +#define RCC_CFGR_SW1 BIT(1) #define RCC_CFGR_SW_MASK 0x3 #define RCC_CFGR_SW_HSI 0 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 -#define RCC_CFGR_SWS0 (1 << 2) -#define RCC_CFGR_SWS1 (1 << 3) +#define RCC_CFGR_SWS0 BIT(2) +#define RCC_CFGR_SWS1 BIT(3) #define RCC_CFGR_SWS_MASK 0xC #define RCC_CFGR_SWS_HSI 0 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 @@ -48,19 +48,19 @@ #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_PWREN BIT(28) -#define PWR_CR_VOS0 (1 << 14) -#define PWR_CR_VOS1 (1 << 15) +#define PWR_CR_VOS0 BIT(14) +#define PWR_CR_VOS1 BIT(15) #define PWR_CR_VOS_MASK 0xC000 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1) #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) #define FLASH_ACR_WS(n) n -#define FLASH_ACR_PRFTEN (1 << 8) -#define FLASH_ACR_ICEN (1 << 9) -#define FLASH_ACR_DCEN (1 << 10) +#define FLASH_ACR_PRFTEN BIT(8) +#define FLASH_ACR_ICEN BIT(9) +#define FLASH_ACR_DCEN BIT(10) struct pll_psc { u8 pll_m; diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c index 102ae6d..116ecc8 100644 --- a/arch/arm/cpu/armv7m/stm32f4/timer.c +++ b/arch/arm/cpu/armv7m/stm32f4/timer.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; #define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) -#define RCC_APB1ENR_TIM2EN (1 << 0) +#define RCC_APB1ENR_TIM2EN BIT(0) struct stm32_tim2_5 { u32 cr1; @@ -40,9 +40,9 @@ struct stm32_tim2_5 { u32 or; }; -#define TIM_CR1_CEN (1 << 0) +#define TIM_CR1_CEN BIT(0) -#define TIM_EGR_UG (1 << 0) +#define TIM_EGR_UG BIT(0) int timer_init(void) { diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c index 12256a3..8304b26 100644 --- a/arch/arm/imx-common/misc.c +++ b/arch/arm/imx-common/misc.c @@ -13,8 +13,8 @@ /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 -#define MXS_BLOCK_SFTRST (1 << 31) -#define MXS_BLOCK_CLKGATE (1 << 30) +#define MXS_BLOCK_SFTRST BIT(31) +#define MXS_BLOCK_CLKGATE BIT(30) int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned int timeout) diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index ac6e40e..0849b65 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -18,7 +18,7 @@ u32 spl_boot_device(void) { struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28); + unsigned int gpr10_boot = readl(&psrc->gpr10) & BIT(28); unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index e522990..c1bf8d5 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -26,12 +26,12 @@ struct mxc_gpt { static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; /* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ -#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_SWR BIT(15) /* Software reset */ +#define GPTCR_24MEN BIT(10) /* Enable 24MHz clock input */ +#define GPTCR_FRR BIT(9) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ -#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ +#define GPTCR_CLKSOURCE_PRE BIT(6) /* Clock source PRECLK */ #define GPTCR_CLKSOURCE_MASK (0x7 << 6) #define GPTCR_TEN 1 /* Timer enable */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 4af6b57..15e83b6 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -43,15 +43,15 @@ /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 -#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) +#define CM_CLKMODE_DPLL_SSC_EN_MASK BIT(12) #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_REGM4XEN_MASK BIT(11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK BIT(10) #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK BIT(9) #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK BIT(8) #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) #define CM_CLKMODE_DPLL_EN_SHIFT 0 diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 220603d..8a9b991 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -17,7 +17,7 @@ /* GPIO CTRL register */ #define GPIO_CTRL_DISABLEMODULE_SHIFT 0 -#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_DISABLEMODULE_MASK BIT(0) #define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK /* GPIO OUTPUT ENABLE register */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 479893e..0db76ed 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -73,20 +73,20 @@ /* USB Clock Control */ #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) -#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) -#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) +#define USBOTGSSX_CLKCTRL_MODULE_EN BIT(1) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 BIT(8) #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) -#define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define USBPHYOCPSCP_MODULE_EN BIT(1) #define CM_DEVICE_INST 0x44df4100 #define PRM_DEVICE_INST 0x44df4000 -#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) -#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) +#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 BIT(8) +#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K BIT(8) /* Control status register */ -#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_MASK BIT(31) #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index d9feb16..015024d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -32,8 +32,8 @@ #define USB_SPH_AXI_RST 0x02 /* MPMU Clocks */ -#define APB2_26M_EN (1 << 20) -#define AP_26M (1 << 4) +#define APB2_26M_EN BIT(20) +#define AP_26M BIT(4) /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index e062da1..5aeba88 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -24,7 +24,7 @@ #define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ #define MV_MFPR_BASE ARMD1_MFPR_BASE #define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register +#define CONFIG_SYS_NS16550_IER BIT(6) /* Bit 6 in UART_IER register represents UART Unit Enable */ /* * I2C definition diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h index 9efa1bf..e3fdea1 100644 --- a/arch/arm/include/asm/arch-armada100/spi.h +++ b/arch/arm/include/asm/arch-armada100/spi.h @@ -41,19 +41,19 @@ struct ssp_reg { #define TX_THRESH_DEF 8 #define TIMEOUT_DEF 1000 -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity +#define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */ +#define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */ +#define SSCR1_LBM BIT(2) /* Loop-Back Mode */ +#define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ +#define SSCR1_SPH BIT(4) /* Motorola SPI SSPSCLK phase setting */ +#define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */ #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ #define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ #define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ #define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out +#define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */ #define SSCR0_DSS 0x0f /* Data Size Select (mask) */ @@ -64,16 +64,16 @@ struct ssp_reg { #define SSCR0_TI (0x1 << 4) /* TI's Synchronous Serial Protocol (SSP) */ #define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port +#define SSCR0_ECS BIT(6) /* External clock select */ +#define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */ -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ +#define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */ +#define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */ +#define SSSR_BSY BIT(4) /* SSP Busy */ +#define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */ +#define SSSR_RFS BIT(6) /* Receive FIFO Service Request */ +#define SSSR_ROR BIT(7) /* Receive FIFO Overrun */ +#define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */ #endif /* __ARMADA100_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h index 953dd44..fe63381 100644 --- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ b/arch/arm/include/asm/arch-armada100/utmi-armada100.h @@ -15,7 +15,7 @@ #define UTMI_PHY_BASE 0xD4206000 /* utmi_ctrl - bits */ -#define INPKT_DELAY_SOF (1 << 28) +#define INPKT_DELAY_SOF BIT(28) #define PLL_PWR_UP 2 #define PHY_PWR_UP 1 @@ -25,7 +25,7 @@ #define PLL_REFDIV_MASK 0x0000000F #define PLL_REFDIV 0 #define PLL_READY 0x800000 -#define VCOCAL_START (1 << 21) +#define VCOCAL_START BIT(21) #define N_DIVIDER 0xEE #define M_DIVIDER 0x0B @@ -33,7 +33,7 @@ /* utmi_tx - bits */ #define CK60_PHSEL 17 #define PHSEL_VAL 0x4 -#define RCAL_START (1 << 12) +#define RCAL_START BIT(12) /* * USB PHY registers diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h index 34e88a8..35370ff 100644 --- a/arch/arm/include/asm/arch-armv7/sysctrl.h +++ b/arch/arm/include/asm/arch-armv7/sysctrl.h @@ -8,10 +8,10 @@ #define _SYSCTRL_H_ /* System controller (SP810) register definitions */ -#define SP810_TIMER0_ENSEL (1 << 15) -#define SP810_TIMER1_ENSEL (1 << 17) -#define SP810_TIMER2_ENSEL (1 << 19) -#define SP810_TIMER3_ENSEL (1 << 21) +#define SP810_TIMER0_ENSEL BIT(15) +#define SP810_TIMER1_ENSEL BIT(17) +#define SP810_TIMER2_ENSEL BIT(19) +#define SP810_TIMER3_ENSEL BIT(21) struct sysctrl { u32 scctrl; /* 0x000 */ diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h index a0412bd..e676a52 100644 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -12,10 +12,10 @@ #define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ #define SYSTIMER_RELOAD 0xFFFFFFFF -#define SYSTIMER_EN (1 << 7) -#define SYSTIMER_32BIT (1 << 1) -#define SYSTIMER_PRESC_16 (1 << 2) -#define SYSTIMER_PRESC_256 (1 << 3) +#define SYSTIMER_EN BIT(7) +#define SYSTIMER_32BIT BIT(1) +#define SYSTIMER_PRESC_16 BIT(2) +#define SYSTIMER_PRESC_256 BIT(3) struct systimer { u32 timer0load; /* 0x00 */ diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h index 330493b..ddf2a98 100644 --- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h @@ -148,47 +148,47 @@ struct mac_regs { }; #endif -#define SELFCTL_RWP (1 << 7) -#define SELFCTL_GPO0 (1 << 5) -#define SELFCTL_PUWE (1 << 4) -#define SELFCTL_PDWE (1 << 3) -#define SELFCTL_MIIL (1 << 2) -#define SELFCTL_RESET (1 << 0) - -#define INTSTS_RWI (1 << 30) -#define INTSTS_RXMI (1 << 29) -#define INTSTS_RXBI (1 << 28) -#define INTSTS_RXSQI (1 << 27) -#define INTSTS_TXLEI (1 << 26) -#define INTSTS_ECIE (1 << 25) -#define INTSTS_TXUHI (1 << 24) -#define INTSTS_MOI (1 << 18) -#define INTSTS_TXCOI (1 << 17) -#define INTSTS_RXROI (1 << 16) -#define INTSTS_MIII (1 << 12) -#define INTSTS_PHYI (1 << 11) -#define INTSTS_TI (1 << 10) -#define INTSTS_AHBE (1 << 8) -#define INTSTS_OTHER (1 << 4) -#define INTSTS_TXSQ (1 << 3) -#define INTSTS_RXSQ (1 << 2) - -#define BMCTL_MT (1 << 13) -#define BMCTL_TT (1 << 12) -#define BMCTL_UNH (1 << 11) -#define BMCTL_TXCHR (1 << 10) -#define BMCTL_TXDIS (1 << 9) -#define BMCTL_TXEN (1 << 8) -#define BMCTL_EH2 (1 << 6) -#define BMCTL_EH1 (1 << 5) -#define BMCTL_EEOB (1 << 4) -#define BMCTL_RXCHR (1 << 2) -#define BMCTL_RXDIS (1 << 1) -#define BMCTL_RXEN (1 << 0) - -#define BMSTS_TXACT (1 << 7) -#define BMSTS_TP (1 << 4) -#define BMSTS_RXACT (1 << 3) +#define SELFCTL_RWP BIT(7) +#define SELFCTL_GPO0 BIT(5) +#define SELFCTL_PUWE BIT(4) +#define SELFCTL_PDWE BIT(3) +#define SELFCTL_MIIL BIT(2) +#define SELFCTL_RESET BIT(0) + +#define INTSTS_RWI BIT(30) +#define INTSTS_RXMI BIT(29) +#define INTSTS_RXBI BIT(28) +#define INTSTS_RXSQI BIT(27) +#define INTSTS_TXLEI BIT(26) +#define INTSTS_ECIE BIT(25) +#define INTSTS_TXUHI BIT(24) +#define INTSTS_MOI BIT(18) +#define INTSTS_TXCOI BIT(17) +#define INTSTS_RXROI BIT(16) +#define INTSTS_MIII BIT(12) +#define INTSTS_PHYI BIT(11) +#define INTSTS_TI BIT(10) +#define INTSTS_AHBE BIT(8) +#define INTSTS_OTHER BIT(4) +#define INTSTS_TXSQ BIT(3) +#define INTSTS_RXSQ BIT(2) + +#define BMCTL_MT BIT(13) +#define BMCTL_TT BIT(12) +#define BMCTL_UNH BIT(11) +#define BMCTL_TXCHR BIT(10) +#define BMCTL_TXDIS BIT(9) +#define BMCTL_TXEN BIT(8) +#define BMCTL_EH2 BIT(6) +#define BMCTL_EH1 BIT(5) +#define BMCTL_EEOB BIT(4) +#define BMCTL_RXCHR BIT(2) +#define BMCTL_RXDIS BIT(1) +#define BMCTL_RXEN BIT(0) + +#define BMSTS_TXACT BIT(7) +#define BMSTS_TP BIT(4) +#define BMSTS_RXACT BIT(3) #define BMSTS_QID_MASK 0x07 #define BMSTS_QID_RXDATA 0x00 #define BMSTS_QID_TXDATA 0x01 @@ -205,30 +205,30 @@ struct mac_regs { #define AFP_TX 0x06 #define AFP_HASH 0x07 -#define RXCTL_PAUSEA (1 << 20) -#define RXCTL_RXFCE1 (1 << 19) -#define RXCTL_RXFCE0 (1 << 18) -#define RXCTL_BCRC (1 << 17) -#define RXCTL_SRXON (1 << 16) -#define RXCTL_RCRCA (1 << 13) -#define RXCTL_RA (1 << 12) -#define RXCTL_PA (1 << 11) -#define RXCTL_BA (1 << 10) -#define RXCTL_MA (1 << 9) -#define RXCTL_IAHA (1 << 8) -#define RXCTL_IA3 (1 << 3) -#define RXCTL_IA2 (1 << 2) -#define RXCTL_IA1 (1 << 1) -#define RXCTL_IA0 (1 << 0) - -#define TXCTL_DEFDIS (1 << 7) -#define TXCTL_MBE (1 << 6) -#define TXCTL_ICRC (1 << 5) -#define TXCTL_TPD (1 << 4) -#define TXCTL_OCOLL (1 << 3) -#define TXCTL_SP (1 << 2) -#define TXCTL_PB (1 << 1) -#define TXCTL_STXON (1 << 0) +#define RXCTL_PAUSEA BIT(20) +#define RXCTL_RXFCE1 BIT(19) +#define RXCTL_RXFCE0 BIT(18) +#define RXCTL_BCRC BIT(17) +#define RXCTL_SRXON BIT(16) +#define RXCTL_RCRCA BIT(13) +#define RXCTL_RA BIT(12) +#define RXCTL_PA BIT(11) +#define RXCTL_BA BIT(10) +#define RXCTL_MA BIT(9) +#define RXCTL_IAHA BIT(8) +#define RXCTL_IA3 BIT(3) +#define RXCTL_IA2 BIT(2) +#define RXCTL_IA1 BIT(1) +#define RXCTL_IA0 BIT(0) + +#define TXCTL_DEFDIS BIT(7) +#define TXCTL_MBE BIT(6) +#define TXCTL_ICRC BIT(5) +#define TXCTL_TPD BIT(4) +#define TXCTL_OCOLL BIT(3) +#define TXCTL_SP BIT(2) +#define TXCTL_PB BIT(1) +#define TXCTL_STXON BIT(0) #define MIICMD_REGAD_MASK (0x001F) #define MIICMD_PHYAD_MASK (0x03E0) @@ -237,7 +237,7 @@ struct mac_regs { #define MIICMD_OPCODE_READ (0x8000) #define MIICMD_OPCODE_WRITE (0x4000) -#define MIISTS_BUSY (1 << 0) +#define MIISTS_BUSY BIT(0) /* * 0x80020000 - 0x8002FFFF: USB OHCI @@ -284,9 +284,9 @@ struct sdram_regs { }; #endif -#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) -#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) -#define SDRAM_DEVCFG_SROMLL (1 << 5) +#define SDRAM_DEVCFG_EXTBUSWIDTH BIT(2) +#define SDRAM_DEVCFG_BANKCOUNT BIT(3) +#define SDRAM_DEVCFG_SROMLL BIT(5) #define SDRAM_DEVCFG_CASLAT_2 0x00010000 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 @@ -304,13 +304,13 @@ struct sdram_regs { #define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 #define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 -#define GLCONFIG_INIT (1 << 0) -#define GLCONFIG_MRS (1 << 1) -#define GLCONFIG_SMEMBUSY (1 << 5) -#define GLCONFIG_LCR (1 << 6) -#define GLCONFIG_REARBEN (1 << 7) -#define GLCONFIG_CLKSHUTDOWN (1 << 30) -#define GLCONFIG_CKE (1 << 31) +#define GLCONFIG_INIT BIT(0) +#define GLCONFIG_MRS BIT(1) +#define GLCONFIG_SMEMBUSY BIT(5) +#define GLCONFIG_LCR BIT(6) +#define GLCONFIG_REARBEN BIT(7) +#define GLCONFIG_CLKSHUTDOWN BIT(30) +#define GLCONFIG_CKE BIT(31) #define EP93XX_SDRAMCTRL 0x80060000 #define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 @@ -387,7 +387,7 @@ struct smc_regs { #define SMC_BCR_IDCY_SHIFT 0 #define SMC_BCR_WST1_SHIFT 5 -#define SMC_BCR_BLE (1 << 10) +#define SMC_BCR_BLE BIT(10) #define SMC_BCR_WST2_SHIFT 11 #define SMC_BCR_MW_SHIFT 28 @@ -628,8 +628,8 @@ struct syscon_regs { #define SYSCON_OFF_CLKSET1 0x0020 #define SYSCON_OFF_SYSCFG 0x009c -#define SYSCON_PWRCNT_UART_BAUD (1 << 29) -#define SYSCON_PWRCNT_USH_EN (1 << 28) +#define SYSCON_PWRCNT_UART_BAUD BIT(29) +#define SYSCON_PWRCNT_USH_EN BIT(28) #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 @@ -637,15 +637,15 @@ struct syscon_regs { #define SYSCON_CLKSET_PLL_PS_SHIFT 16 #define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 #define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 -#define SYSCON_CLKSET1_NBYP1 (1 << 23) +#define SYSCON_CLKSET1_NBYP1 BIT(23) #define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 -#define SYSCON_CLKSET2_PLL2_EN (1 << 18) -#define SYSCON_CLKSET2_NBYP2 (1 << 19) +#define SYSCON_CLKSET2_PLL2_EN BIT(18) +#define SYSCON_CLKSET2_NBYP2 BIT(19) #define SYSCON_CLKSET2_USB_DIV_SHIFT 28 #define SYSCON_CHIPID_REV_MASK 0xF0000000 -#define SYSCON_DEVICECFG_SWRST (1 << 31) +#define SYSCON_DEVICECFG_SWRST BIT(31) #define SYSCON_SYSCFG_LASDO 0x00000020 diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index 4990a1a..6429e5c 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,7 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 -#define CONCONTROL_UPDATE_MODE (1 << 3) +#define CONCONTROL_UPDATE_MODE BIT(3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24 @@ -469,7 +469,7 @@ enum mem_manuf { #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 /* PHY_CON4 rgister fields */ -#define PHY_CON10_CTRL_OFFSETR3 (1 << 24) +#define PHY_CON10_CTRL_OFFSETR3 BIT(24) /* PHY_CON12 register fields */ #define PHY_CON12_CTRL_START_POINT_SHIFT 24 @@ -488,7 +488,7 @@ enum mem_manuf { #define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 #define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) -#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) +#define PHY_CON16_ZQ_MODE_NOTERM_MASK BIT(19) /* PHY_CON42 register fields */ #define PHY_CON42_CTRL_BSTLEN_SHIFT 8 diff --git a/arch/arm/include/asm/arch-exynos/dsim.h b/arch/arm/include/asm/arch-exynos/dsim.h index 86ff4da..a48c0ff 100644 --- a/arch/arm/include/asm/arch-exynos/dsim.h +++ b/arch/arm/include/asm/arch-exynos/dsim.h @@ -45,13 +45,13 @@ struct exynos_mipi_dsim { */ /* DSIM_STATUS */ #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) -#define DSIM_PLL_STABLE (1 << 31) +#define DSIM_STOP_STATE_CLK BIT(8) +#define DSIM_TX_READY_HS_CLK BIT(10) +#define DSIM_PLL_STABLE BIT(31) /* DSIM_SWRST */ -#define DSIM_FUNCRST (1 << 16) -#define DSIM_SWRST (1 << 0) +#define DSIM_FUNCRST BIT(16) +#define DSIM_SWRST BIT(0) /* EXYNOS_DSIM_TIMEOUT */ #define DSIM_LPDR_TOUT_SHIFT (0) @@ -100,7 +100,7 @@ struct exynos_mipi_dsim { #define DSIM_FORCE_STOP_STATE_SHIFT (20) /* EXYNOS_DSIM_MDRESOL */ -#define DSIM_MAIN_STAND_BY (1 << 31) +#define DSIM_MAIN_STAND_BY BIT(31) #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) @@ -133,15 +133,15 @@ struct exynos_mipi_dsim { #define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) /* EXYNOS_DSIM_INTSRC */ -#define INTSRC_FRAME_DONE (1 << 24) -#define INTSRC_PLL_STABLE (1 << 31) -#define INTSRC_SWRST_RELEASE (1 << 30) +#define INTSRC_FRAME_DONE BIT(24) +#define INTSRC_PLL_STABLE BIT(31) +#define INTSRC_SWRST_RELEASE BIT(30) /* EXYNOS_DSIM_INTMSK */ -#define INTMSK_FRAME_DONE (1 << 24) +#define INTMSK_FRAME_DONE BIT(24) /* EXYNOS_DSIM_FIFOCTRL */ -#define SFR_HEADER_EMPTY (1 << 22) +#define SFR_HEADER_EMPTY BIT(22) /* EXYNOS_DSIM_PKTHDR */ #define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0) @@ -151,7 +151,7 @@ struct exynos_mipi_dsim { /* EXYNOS_DSIM_PHYACCHR */ #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) #define DSIM_AFC_CTL_SHIFT (5) -#define DSIM_AFC_EN (1 << 14) +#define DSIM_AFC_EN BIT(14) /* EXYNOS_DSIM_PHYACCHR1 */ #define DSIM_DPDN_SWAP_DATA_SHIFT (0) diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index 3800fa9..0ccace9 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -19,22 +19,22 @@ #define RSTCON_HOSTPHY_SWRST (0xf << 3) #define RSTCON_SWRST (0x1 << 0) -#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) +#define HOST_CTRL0_PHYSWRSTALL BIT(31) +#define HOST_CTRL0_COMMONON_N BIT(9) +#define HOST_CTRL0_SIDDQ BIT(6) +#define HOST_CTRL0_FORCESLEEP BIT(5) +#define HOST_CTRL0_FORCESUSPEND BIT(4) +#define HOST_CTRL0_WORDINTERFACE BIT(3) +#define HOST_CTRL0_UTMISWRST BIT(2) +#define HOST_CTRL0_LINKSWRST BIT(1) +#define HOST_CTRL0_PHYSWRST BIT(0) #define HOST_CTRL0_FSEL_MASK (7 << 16) -#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) +#define EHCICTRL_ENAINCRXALIGN BIT(29) +#define EHCICTRL_ENAINCR4 BIT(28) +#define EHCICTRL_ENAINCR8 BIT(27) +#define EHCICTRL_ENAINCR16 BIT(26) #define HSIC_CTRL_REFCLKSEL (0x2) #define HSIC_CTRL_REFCLKSEL_MASK (0x3) diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h index f0d69b7..7bf2a14 100644 --- a/arch/arm/include/asm/arch-exynos/fb.h +++ b/arch/arm/include/asm/arch-exynos/fb.h @@ -168,12 +168,12 @@ static inline unsigned int exynos_fimd_get_base_offset(void) /* VIDCON0 */ #define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30) -#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30) +#define EXYNOS_VIDCON0_DSI_ENABLE BIT(30) #define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29) -#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29) -#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29) +#define EXYNOS_VIDCON0_SCAN_INTERLACE BIT(29) +#define EXYNOS_VIDCON0_SCAN_MASK BIT(29) #define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26) -#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26) +#define EXYNOS_VIDCON0_VIDOUT_ITU BIT(26) #define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26) #define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26) #define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26) @@ -181,62 +181,62 @@ static inline unsigned int exynos_fimd_get_base_offset(void) #define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) #define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26) #define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17) -#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17) +#define EXYNOS_VIDCON0_PNRMODE_BGR_P BIT(17) #define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17) #define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17) #define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17) #define EXYNOS_VIDCON0_PNRMODE_SHIFT (17) #define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16) -#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16) -#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16) +#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME BIT(16) +#define EXYNOS_VIDCON0_CLKVALUP_MASK BIT(16) #define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) #define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5) -#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5) -#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5) +#define EXYNOS_VIDCON0_VCLKEN_FREERUN BIT(5) +#define EXYNOS_VIDCON0_VCLKEN_MASK BIT(5) #define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4) -#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4) -#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4) +#define EXYNOS_VIDCON0_CLKDIR_DIVIDED BIT(4) +#define EXYNOS_VIDCON0_CLKDIR_MASK BIT(4) #define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2) -#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2) -#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2) -#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1) +#define EXYNOS_VIDCON0_CLKSEL_SCLK BIT(2) +#define EXYNOS_VIDCON0_CLKSEL_MASK BIT(2) +#define EXYNOS_VIDCON0_ENVID_ENABLE BIT(1) #define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1) -#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0) +#define EXYNOS_VIDCON0_ENVID_F_ENABLE BIT(0) #define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0) /* VIDCON1 */ #define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) -#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7) +#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE BIT(7) #define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6) -#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6) +#define EXYNOS_VIDCON1_IHSYNC_INVERT BIT(6) #define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5) -#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5) +#define EXYNOS_VIDCON1_IVSYNC_INVERT BIT(5) #define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4) -#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4) +#define EXYNOS_VIDCON1_IVDEN_INVERT BIT(4) /* VIDCON2 */ #define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23) -#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23) -#define EXYNOS_VIDCON2_EN601_MASK (1 << 23) +#define EXYNOS_VIDCON2_EN601_ENABLE BIT(23) +#define EXYNOS_VIDCON2_EN601_MASK BIT(23) #define EXYNOS_VIDCON2_WB_DISABLE (0 << 15) -#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15) -#define EXYNOS_VIDCON2_WB_MASK (1 << 15) +#define EXYNOS_VIDCON2_WB_ENABLE BIT(15) +#define EXYNOS_VIDCON2_WB_MASK BIT(15) #define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) +#define EXYNOS_VIDCON2_TVFORMATSEL_SW BIT(14) +#define EXYNOS_VIDCON2_TVFORMATSEL_MASK BIT(14) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 BIT(12) #define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) #define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) #define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8) -#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8) -#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8) +#define EXYNOS_VIDCON2_ORGYUV_CBCRY BIT(8) +#define EXYNOS_VIDCON2_ORGYUV_MASK BIT(8) #define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7) -#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7) -#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7) +#define EXYNOS_VIDCON2_YUVORD_CRCB BIT(7) +#define EXYNOS_VIDCON2_YUVORD_MASK BIT(7) /* PRTCON */ #define EXYNOS_PRTCON_UPDATABLE (0 << 11) -#define EXYNOS_PRTCON_PROTECT (1 << 11) +#define EXYNOS_PRTCON_PROTECT BIT(11) /* VIDTCON0 */ #define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) @@ -258,41 +258,41 @@ static inline unsigned int exynos_fimd_get_base_offset(void) /* Window 0~4 Control - WINCONx */ #define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) -#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22) -#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22) +#define EXYNOS_WINCON_DATAPATH_LOCAL BIT(22) +#define EXYNOS_WINCON_DATAPATH_MASK BIT(22) #define EXYNOS_WINCON_BUFSEL_0 (0 << 20) -#define EXYNOS_WINCON_BUFSEL_1 (1 << 20) -#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20) +#define EXYNOS_WINCON_BUFSEL_1 BIT(20) +#define EXYNOS_WINCON_BUFSEL_MASK BIT(20) #define EXYNOS_WINCON_BUFSEL_SHIFT (20) #define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19) -#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19) -#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19) +#define EXYNOS_WINCON_BUFAUTO_ENABLE BIT(19) +#define EXYNOS_WINCON_BUFAUTO_MASK BIT(19) #define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18) -#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18) +#define EXYNOS_WINCON_BITSWP_ENABLE BIT(18) #define EXYNOS_WINCON_BITSWP_SHIFT (18) #define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17) -#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17) +#define EXYNOS_WINCON_BYTESWP_ENABLE BIT(17) #define EXYNOS_WINCON_BYTESWP_SHIFT (17) #define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16) -#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16) +#define EXYNOS_WINCON_HAWSWP_ENABLE BIT(16) #define EXYNOS_WINCON_HAWSWP_SHIFT (16) #define EXYNOS_WINCON_WSWP_DISABLE (0 << 15) -#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15) +#define EXYNOS_WINCON_WSWP_ENABLE BIT(15) #define EXYNOS_WINCON_WSWP_SHIFT (15) #define EXYNOS_WINCON_INRGB_RGB (0 << 13) -#define EXYNOS_WINCON_INRGB_YUV (1 << 13) -#define EXYNOS_WINCON_INRGB_MASK (1 << 13) +#define EXYNOS_WINCON_INRGB_YUV BIT(13) +#define EXYNOS_WINCON_INRGB_MASK BIT(13) #define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9) -#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9) +#define EXYNOS_WINCON_BURSTLEN_8WORD BIT(9) #define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9) #define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9) #define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7) -#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7) +#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE BIT(7) #define EXYNOS_WINCON_BLD_PLANE (0 << 6) -#define EXYNOS_WINCON_BLD_PIXEL (1 << 6) -#define EXYNOS_WINCON_BLD_MASK (1 << 6) +#define EXYNOS_WINCON_BLD_PIXEL BIT(6) +#define EXYNOS_WINCON_BLD_MASK BIT(6) #define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2) -#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2) +#define EXYNOS_WINCON_BPPMODE_2BPP BIT(2) #define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2) #define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2) #define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2) @@ -308,17 +308,17 @@ static inline unsigned int exynos_fimd_get_base_offset(void) #define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2) #define EXYNOS_WINCON_BPPMODE_SHIFT (2) #define EXYNOS_WINCON_ALPHA0_SEL (0 << 1) -#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1) -#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1) +#define EXYNOS_WINCON_ALPHA1_SEL BIT(1) +#define EXYNOS_WINCON_ALPHA_SEL_MASK BIT(1) #define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0) -#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0) +#define EXYNOS_WINCON_ENWIN_ENABLE BIT(0) /* WINCON1 special */ #define EXYNOS_WINCON1_VP_DISABLE (0 << 24) -#define EXYNOS_WINCON1_VP_ENABLE (1 << 24) +#define EXYNOS_WINCON1_VP_ENABLE BIT(24) #define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23) -#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23) -#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23) +#define EXYNOS_WINCON1_LOCALSEL_VP BIT(23) +#define EXYNOS_WINCON1_LOCALSEL_MASK BIT(23) /* WINSHMAP */ #define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) @@ -366,57 +366,57 @@ static inline unsigned int exynos_fimd_get_base_offset(void) /* VIDINTCON0 */ #define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) -#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) +#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE BIT(19) #define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) -#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) +#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE BIT(18) #define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) -#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) +#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE BIT(17) #define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC BIT(15) #define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) #define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) #define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15) #define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13) -#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK BIT(13) #define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) #define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) #define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) -#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) +#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE BIT(12) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 BIT(11) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 BIT(10) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 BIT(9) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 BIT(6) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 BIT(5) #define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) #define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) #define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 BIT(2) #define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2) #define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) #define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) #define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) #define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1) -#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1) +#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE BIT(1) #define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0) -#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0) -#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0) +#define EXYNOS_VIDINTCON0_INT_ENABLE BIT(0) +#define EXYNOS_VIDINTCON0_INT_MASK BIT(0) /* VIDINTCON1 */ -#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5) -#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2) -#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1) -#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0) +#define EXYNOS_VIDINTCON1_INTVPPEND BIT(5) +#define EXYNOS_VIDINTCON1_INTI80PEND BIT(2) +#define EXYNOS_VIDINTCON1_INTFRMPEND BIT(1) +#define EXYNOS_VIDINTCON1_INTFIFOPEND BIT(0) /* WINMAP */ -#define EXYNOS_WINMAP_ENABLE (1 << 24) +#define EXYNOS_WINMAP_ENABLE BIT(24) /* WxKEYCON0 (1~4) */ #define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26) -#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26) +#define EXYNOS_KEYCON0_KEYBLEN_ENABLE BIT(26) #define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25) -#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25) +#define EXYNOS_KEYCON0_KEY_ENABLE BIT(25) #define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24) -#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24) +#define EXYNOS_KEYCON0_DIRCON_MATCH_BG BIT(24) #define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) /* WxKEYCON1 (1~4) */ @@ -440,18 +440,18 @@ static inline unsigned int exynos_fimd_get_base_offset(void) #define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8) #define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4) #define EXYNOS_RSPOL_LOW (0 << 2) -#define EXYNOS_RSPOL_HIGH (1 << 2) +#define EXYNOS_RSPOL_HIGH BIT(2) #define EXYNOS_I80IFEN_DISABLE (0 << 0) -#define EXYNOS_I80IFEN_ENABLE (1 << 0) +#define EXYNOS_I80IFEN_ENABLE BIT(0) /* TRIGCON */ -#define EXYNOS_I80SOFT_TRIG_EN (1 << 0) -#define EXYNOS_I80START_TRIG (1 << 1) -#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) +#define EXYNOS_I80SOFT_TRIG_EN BIT(0) +#define EXYNOS_I80START_TRIG BIT(1) +#define EXYNOS_I80STATUS_TRIG_DONE BIT(2) /* DP_MIE_CLKCON */ #define EXYNOS_DP_MIE_DISABLE (0 << 0) -#define EXYNOS_DP_CLK_ENABLE (1 << 1) +#define EXYNOS_DP_CLK_ENABLE BIT(1) #define EXYNOS_MIE_CLK_ENABLE (3 << 0) #endif /* _REGS_FB_H */ diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h index 4a4a7a0..bf1f596 100644 --- a/arch/arm/include/asm/arch-exynos/i2s-regs.h +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -8,10 +8,10 @@ #ifndef __I2S_REGS_H__ #define __I2S_REGS_H__ -#define CON_RESET (1 << 31) -#define CON_TXFIFO_FULL (1 << 8) -#define CON_TXCH_PAUSE (1 << 4) -#define CON_ACTIVE (1 << 0) +#define CON_RESET BIT(31) +#define CON_TXFIFO_FULL BIT(8) +#define CON_TXCH_PAUSE BIT(4) +#define CON_ACTIVE BIT(0) #define MOD_OP_CLK (3 << 30) #define MOD_BLCP_SHIFT 24 @@ -21,36 +21,36 @@ #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) #define MOD_BLC_16BIT (0 << 13) -#define MOD_BLC_8BIT (1 << 13) +#define MOD_BLC_8BIT BIT(13) #define MOD_BLC_24BIT (2 << 13) #define MOD_BLC_MASK (3 << 13) -#define MOD_SLAVE (1 << 11) +#define MOD_SLAVE BIT(11) #define MOD_RCLKSRC (0 << 10) #define MOD_MASK (3 << 8) #define MOD_LR_LLOW (0 << 7) -#define MOD_LR_RLOW (1 << 7) +#define MOD_LR_RLOW BIT(7) #define MOD_SDF_IIS (0 << 5) -#define MOD_SDF_MSB (1 << 5) +#define MOD_SDF_MSB BIT(5) #define MOD_SDF_LSB (2 << 5) #define MOD_SDF_MASK (3 << 5) #define MOD_RCLK_256FS (0 << 3) -#define MOD_RCLK_512FS (1 << 3) +#define MOD_RCLK_512FS BIT(3) #define MOD_RCLK_384FS (2 << 3) #define MOD_RCLK_768FS (3 << 3) #define MOD_RCLK_MASK (3 << 3) #define MOD_BCLK_32FS (0 << 1) -#define MOD_BCLK_48FS (1 << 1) +#define MOD_BCLK_48FS BIT(1) #define MOD_BCLK_16FS (2 << 1) #define MOD_BCLK_24FS (3 << 1) #define MOD_BCLK_MASK (3 << 1) -#define MOD_CDCLKCON (1 << 12) +#define MOD_CDCLKCON BIT(12) -#define FIC_TXFLUSH (1 << 15) -#define FIC_RXFLUSH (1 << 7) +#define FIC_TXFLUSH BIT(15) +#define FIC_RXFLUSH BIT(7) -#define PSREN (1 << 15) +#define PSREN BIT(15) #define PSVAL (3 << 8) #endif /* __I2S_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 0fb6461..463de14 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -14,10 +14,10 @@ #define SDHCI_CONTROL3 0x84 #define SDHCI_CONTROL4 0x8C -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define SDHCI_CTRL2_SLCARDOUT (1 << 28) +#define SDHCI_CTRL2_ENSTAASYNCCLR BIT(31) +#define SDHCI_CTRL2_ENCMDCNFMSK BIT(30) +#define SDHCI_CTRL2_CDINVRXD3 BIT(29) +#define SDHCI_CTRL2_SLCARDOUT BIT(28) #define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) #define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) @@ -27,28 +27,28 @@ #define SDHCI_CTRL2_LVLDAT_SHIFT (16) #define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define SDHCI_CTRL2_SDCDSEL (1 << 13) -#define SDHCI_CTRL2_SDSIGPC (1 << 12) -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) +#define SDHCI_CTRL2_ENFBCLKTX BIT(15) +#define SDHCI_CTRL2_ENFBCLKRX BIT(14) +#define SDHCI_CTRL2_SDCDSEL BIT(13) +#define SDHCI_CTRL2_SDSIGPC BIT(12) +#define SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11) #define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) #define SDHCI_CTRL2_DFCNT_SHIFT (9) -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define SDHCI_CTRL2_RWAITMODE (1 << 7) -#define SDHCI_CTRL2_DISBUFRD (1 << 6) +#define SDHCI_CTRL2_ENCLKOUTHOLD BIT(8) +#define SDHCI_CTRL2_RWAITMODE BIT(7) +#define SDHCI_CTRL2_DISBUFRD BIT(6) #define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) #define SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define SDHCI_CTRL2_PWRSYNC (1 << 3) -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define SDHCI_CTRL3_FCSEL3 (1 << 31) -#define SDHCI_CTRL3_FCSEL2 (1 << 23) -#define SDHCI_CTRL3_FCSEL1 (1 << 15) -#define SDHCI_CTRL3_FCSEL0 (1 << 7) +#define SDHCI_CTRL2_PWRSYNC BIT(3) +#define SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1) +#define SDHCI_CTRL2_HWINITFIN BIT(0) + +#define SDHCI_CTRL3_FCSEL3 BIT(31) +#define SDHCI_CTRL3_FCSEL2 BIT(23) +#define SDHCI_CTRL3_FCSEL1 BIT(15) +#define SDHCI_CTRL3_FCSEL0 BIT(7) #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 3f97b31..7650981 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -1700,28 +1700,28 @@ unsigned int get_boot_mode(void); void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); -#define EXYNOS_MIPI_PHY_ENABLE (1 << 0) -#define EXYNOS_MIPI_PHY_SRESETN (1 << 1) -#define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +#define EXYNOS_MIPI_PHY_ENABLE BIT(0) +#define EXYNOS_MIPI_PHY_SRESETN BIT(1) +#define EXYNOS_MIPI_PHY_MRESETN BIT(2) void set_usbhost_phy_ctrl(unsigned int enable); /* Enables hardware tripping to power off the system when TMU fails */ void set_hw_thermal_trip(void); -#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_EN BIT(0) #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) void set_usbdrd_phy_ctrl(unsigned int enable); -#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) +#define POWER_USB_DRD_PHY_CTRL_EN BIT(0) #define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) void set_dp_phy_ctrl(unsigned int enable); -#define EXYNOS_DP_PHY_ENABLE (1 << 0) +#define EXYNOS_DP_PHY_ENABLE BIT(0) -#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) +#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH BIT(8) #define POWER_ENABLE_HW_TRIP (1UL << 31) /* diff --git a/arch/arm/include/asm/arch-exynos/pwm.h b/arch/arm/include/asm/arch-exynos/pwm.h index 43474c3..48cd0ac 100644 --- a/arch/arm/include/asm/arch-exynos/pwm.h +++ b/arch/arm/include/asm/arch-exynos/pwm.h @@ -27,7 +27,7 @@ #define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) #define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) #define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) -#define TCON4_AUTO_RELOAD (1 << 22) +#define TCON4_AUTO_RELOAD BIT(22) #ifndef __ASSEMBLY__ struct s5p_timer { diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index 0ba931b..68e7f97 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -33,44 +33,44 @@ struct exynos_spi { #define SF_READ_DATA_CMD 0x3 /* SPI_CHCFG */ -#define SPI_CH_HS_EN (1 << 6) -#define SPI_CH_RST (1 << 5) -#define SPI_SLAVE_MODE (1 << 4) -#define SPI_CH_CPOL_L (1 << 3) -#define SPI_CH_CPHA_B (1 << 2) -#define SPI_RX_CH_ON (1 << 1) -#define SPI_TX_CH_ON (1 << 0) +#define SPI_CH_HS_EN BIT(6) +#define SPI_CH_RST BIT(5) +#define SPI_SLAVE_MODE BIT(4) +#define SPI_CH_CPOL_L BIT(3) +#define SPI_CH_CPHA_B BIT(2) +#define SPI_RX_CH_ON BIT(1) +#define SPI_TX_CH_ON BIT(0) /* SPI_MODECFG */ #define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) #define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) /* SPI_CSREG */ -#define SPI_SLAVE_SIG_INACT (1 << 0) +#define SPI_SLAVE_SIG_INACT BIT(0) /* SPI_STS */ -#define SPI_ST_TX_DONE (1 << 25) +#define SPI_ST_TX_DONE BIT(25) #define SPI_FIFO_LVL_MASK 0x1ff #define SPI_TX_LVL_OFFSET 6 #define SPI_RX_LVL_OFFSET 15 /* Feedback Delay */ #define SPI_CLK_BYPASS (0 << 0) -#define SPI_FB_DELAY_90 (1 << 0) +#define SPI_FB_DELAY_90 BIT(0) #define SPI_FB_DELAY_180 (2 << 0) #define SPI_FB_DELAY_270 (3 << 0) /* Packet Count */ -#define SPI_PACKET_CNT_EN (1 << 16) +#define SPI_PACKET_CNT_EN BIT(16) /* Swap config */ -#define SPI_TX_SWAP_EN (1 << 0) -#define SPI_TX_BYTE_SWAP (1 << 2) -#define SPI_TX_HWORD_SWAP (1 << 3) -#define SPI_TX_BYTE_SWAP (1 << 2) -#define SPI_RX_SWAP_EN (1 << 4) -#define SPI_RX_BYTE_SWAP (1 << 6) -#define SPI_RX_HWORD_SWAP (1 << 7) +#define SPI_TX_SWAP_EN BIT(0) +#define SPI_TX_BYTE_SWAP BIT(2) +#define SPI_TX_HWORD_SWAP BIT(3) +#define SPI_TX_BYTE_SWAP BIT(2) +#define SPI_RX_SWAP_EN BIT(4) +#define SPI_RX_BYTE_SWAP BIT(6) +#define SPI_RX_HWORD_SWAP BIT(7) #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 3ffb296..88595c3 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -35,7 +35,7 @@ struct exynos5_sysreg { }; #endif -#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) +#define USB20_PHY_CFG_HOST_LINK_EN BIT(0) /* * Data Synchronization Barrier acts as a special kind of memory barrier. diff --git a/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/arch/arm/include/asm/arch-exynos/xhci-exynos.h index 92b90a4..cbb673a 100644 --- a/arch/arm/include/asm/arch-exynos/xhci-exynos.h +++ b/arch/arm/include/asm/arch-exynos/xhci-exynos.h @@ -14,9 +14,9 @@ #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) -#define PHYUTMI_OTGDISABLE (1 << 6) -#define PHYUTMI_FORCESUSPEND (1 << 1) -#define PHYUTMI_FORCESLEEP (1 << 0) +#define PHYUTMI_OTGDISABLE BIT(6) +#define PHYUTMI_FORCESUSPEND BIT(1) +#define PHYUTMI_FORCESLEEP BIT(0) #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 9449869..12066cc 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -83,26 +83,26 @@ struct clk_pm_regs { #define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) /* Power Control Register bits */ -#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) -#define CLK_PWR_EMC_SREFREQ (1 << 9) -#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) -#define CLK_PWR_SDRAM_SREFREQ (1 << 7) -#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) -#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) -#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) -#define CLK_PWR_NORMAL_RUN (1 << 2) -#define CLK_PWR_HIGHCORE_CTRL (1 << 1) -#define CLK_PWR_STOP_MODE (1 << 0) +#define CLK_PWR_HCLK_RUN_PERIPH BIT(10) +#define CLK_PWR_EMC_SREFREQ BIT(9) +#define CLK_PWR_EMC_SREFREQ_UPDATE BIT(8) +#define CLK_PWR_SDRAM_SREFREQ BIT(7) +#define CLK_PWR_HIGHCORE_LEVEL BIT(5) +#define CLK_PWR_SYSCLKEN_LEVEL BIT(4) +#define CLK_PWR_SYSCLKEN_CTRL BIT(3) +#define CLK_PWR_NORMAL_RUN BIT(2) +#define CLK_PWR_HIGHCORE_CTRL BIT(1) +#define CLK_PWR_STOP_MODE BIT(0) /* SYSCLK Control Register bits */ -#define CLK_SYSCLK_PLL397 (1 << 1) -#define CLK_SYSCLK_MUX (1 << 0) +#define CLK_SYSCLK_PLL397 BIT(1) +#define CLK_SYSCLK_MUX BIT(0) /* HCLK PLL Control Register bits */ -#define CLK_HCLK_PLL_OPERATING (1 << 16) -#define CLK_HCLK_PLL_BYPASS (1 << 15) -#define CLK_HCLK_PLL_DIRECT (1 << 14) -#define CLK_HCLK_PLL_FEEDBACK (1 << 13) +#define CLK_HCLK_PLL_OPERATING BIT(16) +#define CLK_HCLK_PLL_BYPASS BIT(15) +#define CLK_HCLK_PLL_DIRECT BIT(14) +#define CLK_HCLK_PLL_FEEDBACK BIT(13) #define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) #define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) #define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) @@ -115,52 +115,52 @@ struct clk_pm_regs { #define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) #define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) #define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) -#define CLK_HCLK_PLL_LOCKED (1 << 0) +#define CLK_HCLK_PLL_LOCKED BIT(0) /* Ethernet MAC Clock Control Register bits */ #define CLK_MAC_RMII (0x3 << 3) #define CLK_MAC_MII (0x1 << 3) -#define CLK_MAC_MASTER (1 << 2) -#define CLK_MAC_SLAVE (1 << 1) -#define CLK_MAC_REG (1 << 0) +#define CLK_MAC_MASTER BIT(2) +#define CLK_MAC_SLAVE BIT(1) +#define CLK_MAC_REG BIT(0) /* I2C Clock Control Register bits */ -#define CLK_I2C2_ENABLE (1 << 1) -#define CLK_I2C1_ENABLE (1 << 0) +#define CLK_I2C2_ENABLE BIT(1) +#define CLK_I2C1_ENABLE BIT(0) /* Timer Clock Control1 Register bits */ -#define CLK_TIMCLK_MOTOR (1 << 6) -#define CLK_TIMCLK_TIMER3 (1 << 5) -#define CLK_TIMCLK_TIMER2 (1 << 4) -#define CLK_TIMCLK_TIMER1 (1 << 3) -#define CLK_TIMCLK_TIMER0 (1 << 2) -#define CLK_TIMCLK_TIMER5 (1 << 1) -#define CLK_TIMCLK_TIMER4 (1 << 0) +#define CLK_TIMCLK_MOTOR BIT(6) +#define CLK_TIMCLK_TIMER3 BIT(5) +#define CLK_TIMCLK_TIMER2 BIT(4) +#define CLK_TIMCLK_TIMER1 BIT(3) +#define CLK_TIMCLK_TIMER0 BIT(2) +#define CLK_TIMCLK_TIMER5 BIT(1) +#define CLK_TIMCLK_TIMER4 BIT(0) /* Timer Clock Control Register bits */ -#define CLK_TIMCLK_HSTIMER (1 << 1) -#define CLK_TIMCLK_WATCHDOG (1 << 0) +#define CLK_TIMCLK_HSTIMER BIT(1) +#define CLK_TIMCLK_WATCHDOG BIT(0) /* UART Clock Control Register bits */ #define CLK_UART(n) (1 << ((n) - 3)) /* UARTn Clock Select Registers bits */ -#define CLK_UART_HCLK (1 << 16) +#define CLK_UART_HCLK BIT(16) #define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) #define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) /* DMA Clock Control Register bits */ -#define CLK_DMA_ENABLE (1 << 0) +#define CLK_DMA_ENABLE BIT(0) /* NAND Clock Control Register bits */ -#define CLK_NAND_MLC (1 << 1) -#define CLK_NAND_MLC_INT (1 << 5) +#define CLK_NAND_MLC BIT(1) +#define CLK_NAND_MLC_INT BIT(5) /* SSP Clock Control Register bits */ -#define CLK_SSP0_ENABLE_CLOCK (1 << 0) +#define CLK_SSP0_ENABLE_CLOCK BIT(0) /* SDRAMCLK register bits */ -#define CLK_SDRAM_DDR_SEL (1 << 1) +#define CLK_SDRAM_DDR_SEL BIT(1) unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h index 1a2bab2..06f4b3a 100644 --- a/arch/arm/include/asm/arch-lpc32xx/emc.h +++ b/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -59,13 +59,13 @@ struct emc_regs { }; /* Static Memory Configuration Register bits */ -#define EMC_STAT_CONFIG_WP (1 << 20) -#define EMC_STAT_CONFIG_EW (1 << 8) -#define EMC_STAT_CONFIG_PB (1 << 7) -#define EMC_STAT_CONFIG_PC (1 << 6) -#define EMC_STAT_CONFIG_PM (1 << 3) +#define EMC_STAT_CONFIG_WP BIT(20) +#define EMC_STAT_CONFIG_EW BIT(8) +#define EMC_STAT_CONFIG_PB BIT(7) +#define EMC_STAT_CONFIG_PC BIT(6) +#define EMC_STAT_CONFIG_PM BIT(3) #define EMC_STAT_CONFIG_32BIT (2 << 0) -#define EMC_STAT_CONFIG_16BIT (1 << 0) +#define EMC_STAT_CONFIG_16BIT BIT(0) #define EMC_STAT_CONFIG_8BIT (0 << 0) /* Static Memory Delay Registers */ diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h index bd90144..42f1b8e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/timer.h +++ b/arch/arm/include/asm/arch-lpc32xx/timer.h @@ -30,8 +30,8 @@ struct timer_regs { #define TIMER_IR_MR(n) (1 << (n)) /* Timer/Counter Timer Control Register bits */ -#define TIMER_TCR_COUNTER_RESET (1 << 1) -#define TIMER_TCR_COUNTER_ENABLE (1 << 0) +#define TIMER_TCR_COUNTER_RESET BIT(1) +#define TIMER_TCR_COUNTER_ENABLE BIT(0) #define TIMER_TCR_COUNTER_DISABLE (0 << 0) /* Timer/Counter Match Control Register bits */ diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h index 01dacd6..b0be643 100644 --- a/arch/arm/include/asm/arch-lpc32xx/uart.h +++ b/arch/arm/include/asm/arch-lpc32xx/uart.h @@ -22,9 +22,9 @@ struct hsuart_regs { }; /* 14-clock UART Receiver FIFO Register bits */ -#define HSUART_RX_BREAK (1 << 10) -#define HSUART_RX_ERROR (1 << 9) -#define HSUART_RX_EMPTY (1 << 8) +#define HSUART_RX_BREAK BIT(10) +#define HSUART_RX_ERROR BIT(9) +#define HSUART_RX_EMPTY BIT(8) #define HSUART_RX_DATA (0xff << 0) /* 14-clock UART Level Register bits */ @@ -32,32 +32,32 @@ struct hsuart_regs { #define HSUART_LEVEL_RX (0xff << 0) /* 14-clock UART Interrupt Identification Register bits */ -#define HSUART_IIR_TX_INT_SET (1 << 6) -#define HSUART_IIR_RX_OE (1 << 5) -#define HSUART_IIR_BRK (1 << 4) -#define HSUART_IIR_FE (1 << 3) -#define HSUART_IIR_RX_TIMEOUT (1 << 2) -#define HSUART_IIR_RX_TRIG (1 << 1) -#define HSUART_IIR_TX (1 << 0) +#define HSUART_IIR_TX_INT_SET BIT(6) +#define HSUART_IIR_RX_OE BIT(5) +#define HSUART_IIR_BRK BIT(4) +#define HSUART_IIR_FE BIT(3) +#define HSUART_IIR_RX_TIMEOUT BIT(2) +#define HSUART_IIR_RX_TRIG BIT(1) +#define HSUART_IIR_TX BIT(0) /* 14-clock UART Control Register bits */ -#define HSUART_CTRL_HRTS_INV (1 << 21) +#define HSUART_CTRL_HRTS_INV BIT(21) #define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) #define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) #define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) #define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) -#define HSUART_CTRL_HRTS_EN (1 << 18) +#define HSUART_CTRL_HRTS_EN BIT(18) #define HSUART_CTRL_TMO_16 (0x3 << 16) #define HSUART_CTRL_TMO_8 (0x2 << 16) #define HSUART_CTRL_TMO_4 (0x1 << 16) #define HSUART_CTRL_TMO_DISABLED (0x0 << 16) -#define HSUART_CTRL_HCTS_INV (1 << 15) -#define HSUART_CTRL_HCTS_EN (1 << 14) +#define HSUART_CTRL_HCTS_INV BIT(15) +#define HSUART_CTRL_HCTS_EN BIT(14) #define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) -#define HSUART_CTRL_HSU_BREAK (1 << 8) -#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) -#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) -#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) +#define HSUART_CTRL_HSU_BREAK BIT(8) +#define HSUART_CTRL_HSU_ERR_INT_EN BIT(7) +#define HSUART_CTRL_HSU_RX_INT_EN BIT(6) +#define HSUART_CTRL_HSU_TX_INT_EN BIT(5) #define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) #define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) #define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) @@ -77,19 +77,19 @@ struct uart_ctrl_regs { }; /* UART Control Register bits */ -#define UART_CTRL_UART3_MD_CTRL (1 << 11) -#define UART_CTRL_HDPX_INV (1 << 10) -#define UART_CTRL_HDPX_EN (1 << 9) -#define UART_CTRL_UART6_IRDA (1 << 5) -#define UART_CTRL_IR_TX6_INV (1 << 4) -#define UART_CTRL_IR_RX6_INV (1 << 3) -#define UART_CTRL_IR_RX_LENGTH (1 << 2) -#define UART_CTRL_IR_TX_LENGTH (1 << 1) -#define UART_CTRL_UART5_USB_MODE (1 << 0) +#define UART_CTRL_UART3_MD_CTRL BIT(11) +#define UART_CTRL_HDPX_INV BIT(10) +#define UART_CTRL_HDPX_EN BIT(9) +#define UART_CTRL_UART6_IRDA BIT(5) +#define UART_CTRL_IR_TX6_INV BIT(4) +#define UART_CTRL_IR_RX6_INV BIT(3) +#define UART_CTRL_IR_RX_LENGTH BIT(2) +#define UART_CTRL_IR_TX_LENGTH BIT(1) +#define UART_CTRL_UART5_USB_MODE BIT(0) /* UART Clock Mode Register bits */ #define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) -#define UART_CLKMODE_STAT (1 << 14) +#define UART_CLKMODE_STAT BIT(14) #define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) #define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) #define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h index d7903c2..db2b4d4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/wdt.h +++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h @@ -22,17 +22,17 @@ struct wdt_regs { }; /* Watchdog Timer Control Register bits */ -#define WDTIM_CTRL_PAUSE_EN (1 << 2) -#define WDTIM_CTRL_RESET_COUNT (1 << 1) -#define WDTIM_CTRL_COUNT_ENAB (1 << 0) +#define WDTIM_CTRL_PAUSE_EN BIT(2) +#define WDTIM_CTRL_RESET_COUNT BIT(1) +#define WDTIM_CTRL_COUNT_ENAB BIT(0) /* Watchdog Timer Match Control Register bits */ -#define WDTIM_MCTRL_RESFRC2 (1 << 6) -#define WDTIM_MCTRL_RESFRC1 (1 << 5) -#define WDTIM_MCTRL_M_RES2 (1 << 4) -#define WDTIM_MCTRL_M_RES1 (1 << 3) -#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) -#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) -#define WDTIM_MCTRL_MR0_INT (1 << 0) +#define WDTIM_MCTRL_RESFRC2 BIT(6) +#define WDTIM_MCTRL_RESFRC1 BIT(5) +#define WDTIM_MCTRL_M_RES2 BIT(4) +#define WDTIM_MCTRL_M_RES1 BIT(3) +#define WDTIM_MCTRL_STOP_COUNT0 BIT(2) +#define WDTIM_MCTRL_RESET_COUNT0 BIT(1) +#define WDTIM_MCTRL_MR0_INT BIT(0) #endif /* _LPC32XX_WDT_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a8122c1..8420cc1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -32,8 +32,8 @@ #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 #define TIMER_COMP_VAL 0xffffffff -#define ARCH_TIMER_CTRL_ENABLE (1 << 0) -#define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define ARCH_TIMER_CTRL_ENABLE BIT(0) +#define SYS_COUNTER_CTRL_ENABLE BIT(24) #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..7c2587d 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -28,22 +28,22 @@ struct kwspi_registers { * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) */ -#define MOSI_MPP6 (1 << 0) -#define SCK_MPP10 (1 << 1) -#define MISO_MPP11 (1 << 2) +#define MOSI_MPP6 BIT(0) +#define SCK_MPP10 BIT(1) +#define MISO_MPP11 BIT(2) #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CLKPRESCL_MIN 0x12 #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_SMEMRDY BIT(1) /* SerMem Data xfer ready */ #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ #define KWSPI_XFERLEN_1BYTE 0 -#define KWSPI_XFERLEN_2BYTE (1 << 5) -#define KWSPI_XFERLEN_MASK (1 << 5) +#define KWSPI_XFERLEN_2BYTE BIT(5) +#define KWSPI_XFERLEN_MASK BIT(5) #define KWSPI_ADRLEN_1BYTE 0 -#define KWSPI_ADRLEN_2BYTE (1 << 8) +#define KWSPI_ADRLEN_2BYTE BIT(8) #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 3dffa4a..78f1d71 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -402,63 +402,63 @@ struct cspi_regs { #define CCM_CCTL_ARM_DIV_MASK 3 #define CCM_CCTL_AHB_DIV_SHIFT 28 #define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) +#define CCM_CCTL_ARM_SRC BIT(14) +#define CCM_CGR1_GPT1 BIT(19) #define CCM_PERCLK_REG(clk) (clk / 4) #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) #define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +#define CCM_RCSR_NF_16BIT_SEL BIT(14) #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) #define CCM_CRDR_BT_UART_SRC_SHIFT 29 #define CCM_CRDR_BT_UART_SRC_MASK 7 /* ESDRAM Controller register bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) +#define ESDCTL_BL BIT(7) +#define ESDCTL_FP BIT(8) #define ESDCTL_PWDT(x) (((x) & 3) << 10) #define ESDCTL_SREFR(x) (((x) & 7) << 13) #define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_16_LOWER BIT(16) #define ESDCTL_DSIZ_32 (2 << 16) #define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL9 BIT(20) #define ESDCTL_COL10 (2 << 20) #define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW12 BIT(24) #define ESDCTL_ROW13 (2 << 24) #define ESDCTL_ROW14 (3 << 24) #define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) +#define ESDCTL_SP BIT(27) #define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_PRECHARGE BIT(28) #define ESDCTL_SMODE_AUTO_REF (2 << 28) #define ESDCTL_SMODE_LOAD_MODE (3 << 28) #define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) +#define ESDCTL_SDE BIT(31) #define ESDCFG_TRC(x) (((x) & 0xf) << 0) #define ESDCFG_TRCD(x) (((x) & 0x7) << 4) #define ESDCFG_TCAS(x) (((x) & 0x3) << 8) #define ESDCFG_TRRD(x) (((x) & 0x3) << 10) #define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TWR BIT(15) #define ESDCFG_TMRD(x) (((x) & 0x3) << 16) #define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TWTR BIT(20) #define ESDCFG_TXP(x) (((x) & 0x3) << 21) -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) +#define ESDMISC_RST BIT(1) +#define ESDMISC_MDDREN BIT(2) +#define ESDMISC_MDDR_DL_RST BIT(3) +#define ESDMISC_MDDR_MDIS BIT(4) +#define ESDMISC_LHD BIT(5) +#define ESDMISC_MA10_SHARE BIT(6) +#define ESDMISC_SDRAM_RDY BIT(31) /* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ +#define GPT_CTRL_SWR BIT(15) /* Software reset */ +#define GPT_CTRL_FRR BIT(9) /* Freerun / restart */ #define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ #define GPT_CTRL_TEN 1 /* Timer enable */ @@ -504,21 +504,21 @@ struct cspi_regs { * CSPI register definitions */ #define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_EN BIT(0) +#define MXC_CSPICTRL_MODE BIT(1) +#define MXC_CSPICTRL_XCH BIT(2) +#define MXC_CSPICTRL_SMC BIT(3) +#define MXC_CSPICTRL_POL BIT(4) +#define MXC_CSPICTRL_PHA BIT(5) +#define MXC_CSPICTRL_SSCTL BIT(6) +#define MXC_CSPICTRL_SSPOL BIT(7) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_TC BIT(7) +#define MXC_CSPICTRL_RXOVF BIT(6) #define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 4 #define MXC_SPI_BASE_ADDRESSES \ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h index 6c41ea0..d8954b0 100644 --- a/arch/arm/include/asm/arch-mx25/macro.h +++ b/arch/arm/include/asm/arch-mx25/macro.h @@ -71,7 +71,7 @@ * * Default argument values: * - CTL: - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + * MRRP[0] = LCDC on priority list BIT(0) = 0x00000001 * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 92c847e..c34ba5e 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -217,157 +217,157 @@ struct fuse_bank0_regs { /* FMCR System Control bit definition*/ -#define UART4_RXD_CTL (1 << 25) -#define UART4_RTS_CTL (1 << 24) -#define KP_COL6_CTL (1 << 18) -#define KP_ROW7_CTL (1 << 17) -#define KP_ROW6_CTL (1 << 16) -#define PC_WAIT_B_CTL (1 << 14) -#define PC_READY_CTL (1 << 13) -#define PC_VS1_CTL (1 << 12) -#define PC_VS2_CTL (1 << 11) -#define PC_BVD1_CTL (1 << 10) -#define PC_BVD2_CTL (1 << 9) -#define IOS16_CTL (1 << 8) -#define NF_FMS (1 << 5) -#define NF_16BIT_SEL (1 << 4) -#define SLCDC_SEL (1 << 2) -#define SDCS1_SEL (1 << 1) -#define SDCS0_SEL (1 << 0) +#define UART4_RXD_CTL BIT(25) +#define UART4_RTS_CTL BIT(24) +#define KP_COL6_CTL BIT(18) +#define KP_ROW7_CTL BIT(17) +#define KP_ROW6_CTL BIT(16) +#define PC_WAIT_B_CTL BIT(14) +#define PC_READY_CTL BIT(13) +#define PC_VS1_CTL BIT(12) +#define PC_VS2_CTL BIT(11) +#define PC_BVD1_CTL BIT(10) +#define PC_BVD2_CTL BIT(9) +#define IOS16_CTL BIT(8) +#define NF_FMS BIT(5) +#define NF_16BIT_SEL BIT(4) +#define SLCDC_SEL BIT(2) +#define SDCS1_SEL BIT(1) +#define SDCS0_SEL BIT(0) /* important definition of some bits of WCR */ #define WCR_WDE 0x04 -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_MPEN BIT(0) +#define CSCR_SPEN BIT(1) +#define CSCR_FPM_EN BIT(2) +#define CSCR_OSC26M_DIS BIT(3) +#define CSCR_OSC26M_DIV1P5 BIT(4) #define CSCR_AHB_DIV #define CSCR_ARM_DIV -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) +#define CSCR_ARM_SRC_MPLL BIT(15) +#define CSCR_MCU_SEL BIT(16) +#define CSCR_SP_SEL BIT(17) +#define CSCR_MPLL_RESTART BIT(18) +#define CSCR_SPLL_RESTART BIT(19) +#define CSCR_MSHC_SEL BIT(20) +#define CSCR_H264_SEL BIT(21) +#define CSCR_SSI1_SEL BIT(22) +#define CSCR_SSI2_SEL BIT(23) #define CSCR_SD_CNT #define CSCR_USB_DIV -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) +#define CSCR_UPDATE_DIS BIT(31) + +#define MPCTL1_BRMO BIT(6) +#define MPCTL1_LF BIT(15) + +#define PCCR0_SSI2_EN BIT(0) +#define PCCR0_SSI1_EN BIT(1) +#define PCCR0_SLCDC_EN BIT(2) +#define PCCR0_SDHC3_EN BIT(3) +#define PCCR0_SDHC2_EN BIT(4) +#define PCCR0_SDHC1_EN BIT(5) +#define PCCR0_SDC_EN BIT(6) +#define PCCR0_SAHARA_EN BIT(7) +#define PCCR0_RTIC_EN BIT(8) +#define PCCR0_RTC_EN BIT(9) +#define PCCR0_PWM_EN BIT(11) +#define PCCR0_OWIRE_EN BIT(12) +#define PCCR0_MSHC_EN BIT(13) +#define PCCR0_LCDC_EN BIT(14) +#define PCCR0_KPP_EN BIT(15) +#define PCCR0_IIM_EN BIT(16) +#define PCCR0_I2C2_EN BIT(17) +#define PCCR0_I2C1_EN BIT(18) +#define PCCR0_GPT6_EN BIT(19) +#define PCCR0_GPT5_EN BIT(20) +#define PCCR0_GPT4_EN BIT(21) +#define PCCR0_GPT3_EN BIT(22) +#define PCCR0_GPT2_EN BIT(23) +#define PCCR0_GPT1_EN BIT(24) +#define PCCR0_GPIO_EN BIT(25) +#define PCCR0_FEC_EN BIT(26) +#define PCCR0_EMMA_EN BIT(27) +#define PCCR0_DMA_EN BIT(28) +#define PCCR0_CSPI3_EN BIT(29) +#define PCCR0_CSPI2_EN BIT(30) +#define PCCR0_CSPI1_EN BIT(31) + +#define PCCR1_MSHC_BAUDEN BIT(2) +#define PCCR1_NFC_BAUDEN BIT(3) +#define PCCR1_SSI2_BAUDEN BIT(4) +#define PCCR1_SSI1_BAUDEN BIT(5) +#define PCCR1_H264_BAUDEN BIT(6) +#define PCCR1_PERCLK4_EN BIT(7) +#define PCCR1_PERCLK3_EN BIT(8) +#define PCCR1_PERCLK2_EN BIT(9) +#define PCCR1_PERCLK1_EN BIT(10) +#define PCCR1_HCLK_USB BIT(11) +#define PCCR1_HCLK_SLCDC BIT(12) +#define PCCR1_HCLK_SAHARA BIT(13) +#define PCCR1_HCLK_RTIC BIT(14) +#define PCCR1_HCLK_LCDC BIT(15) +#define PCCR1_HCLK_H264 BIT(16) +#define PCCR1_HCLK_FEC BIT(17) +#define PCCR1_HCLK_EMMA BIT(18) +#define PCCR1_HCLK_EMI BIT(19) +#define PCCR1_HCLK_DMA BIT(20) +#define PCCR1_HCLK_CSI BIT(21) +#define PCCR1_HCLK_BROM BIT(22) +#define PCCR1_HCLK_ATA BIT(23) +#define PCCR1_WDT_EN BIT(24) +#define PCCR1_USB_EN BIT(25) +#define PCCR1_UART6_EN BIT(26) +#define PCCR1_UART5_EN BIT(27) +#define PCCR1_UART4_EN BIT(28) +#define PCCR1_UART3_EN BIT(29) +#define PCCR1_UART2_EN BIT(30) +#define PCCR1_UART1_EN BIT(31) /* SDRAM Controller registers bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) +#define ESDCTL_BL BIT(7) +#define ESDCTL_FP BIT(8) #define ESDCTL_PWDT(x) (((x) & 3) << 10) #define ESDCTL_SREFR(x) (((x) & 7) << 13) #define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_16_LOWER BIT(16) #define ESDCTL_DSIZ_32 (2 << 16) #define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL9 BIT(20) #define ESDCTL_COL10 (2 << 20) #define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW12 BIT(24) #define ESDCTL_ROW13 (2 << 24) #define ESDCTL_ROW14 (3 << 24) #define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) +#define ESDCTL_SP BIT(27) #define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_PRECHARGE BIT(28) #define ESDCTL_SMODE_AUTO_REF (2 << 28) #define ESDCTL_SMODE_LOAD_MODE (3 << 28) #define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) +#define ESDCTL_SDE BIT(31) #define ESDCFG_TRC(x) (((x) & 0xf) << 0) #define ESDCFG_TRCD(x) (((x) & 0x7) << 4) #define ESDCFG_TCAS(x) (((x) & 0x3) << 8) #define ESDCFG_TRRD(x) (((x) & 0x3) << 10) #define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TWR BIT(15) #define ESDCFG_TMRD(x) (((x) & 0x3) << 16) #define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TWTR BIT(20) #define ESDCFG_TXP(x) (((x) & 0x3) << 21) -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) +#define ESDMISC_RST BIT(1) +#define ESDMISC_MDDREN BIT(2) +#define ESDMISC_MDDR_DL_RST BIT(3) +#define ESDMISC_MDDR_MDIS BIT(4) +#define ESDMISC_LHD BIT(5) +#define ESDMISC_MA10_SHARE BIT(6) +#define ESDMISC_SDRAM_RDY BIT(31) #define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) #define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) @@ -431,15 +431,15 @@ struct fuse_bank0_regs { #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) /* Clocksource Bitfields */ -#define TCTL_SWR (1 << 15) /* Software reset */ -#define TCTL_FRR (1 << 8) /* Freerun / restart */ +#define TCTL_SWR BIT(15) /* Software reset */ +#define TCTL_FRR BIT(8) /* Freerun / restart */ #define TCTL_CAP (3 << 6) /* Capture Edge */ -#define TCTL_OM (1 << 5) /* output mode */ -#define TCTL_IRQEN (1 << 4) /* interrupt enable */ +#define TCTL_OM BIT(5) /* output mode */ +#define TCTL_IRQEN BIT(4) /* interrupt enable */ #define TCTL_CLKSOURCE 1 /* Clock source bit position */ #define TCTL_TEN 1 /* Timer enable */ #define TPRER_PRES 0xff /* Prescale */ -#define TSTAT_CAPT (1 << 1) /* Capture event */ +#define TSTAT_CAPT BIT(1) /* Capture event */ #define TSTAT_COMP 1 /* Compare event */ #define GPIO1_BASE_ADDR 0x10015000 @@ -461,12 +461,12 @@ struct fuse_bank0_regs { #define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) #define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) -#define GPIO_OUT (1 << 8) +#define GPIO_OUT BIT(8) #define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) +#define GPIO_PUEN BIT(9) -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) +#define GPIO_PF BIT(10) +#define GPIO_AF BIT(11) #define GPIO_OCR_SHIFT 12 #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) @@ -489,15 +489,15 @@ struct fuse_bank0_regs { #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) -#define IIM_STAT_BUSY (1 << 7) -#define IIM_STAT_PRGD (1 << 1) -#define IIM_STAT_SNSD (1 << 0) -#define IIM_ERR_PRGE (1 << 7) -#define IIM_ERR_WPE (1 << 6) -#define IIM_ERR_OPE (1 << 5) -#define IIM_ERR_RPE (1 << 4) -#define IIM_ERR_WLRE (1 << 3) -#define IIM_ERR_SNSE (1 << 2) -#define IIM_ERR_PARITYE (1 << 1) +#define IIM_STAT_BUSY BIT(7) +#define IIM_STAT_PRGD BIT(1) +#define IIM_STAT_SNSD BIT(0) +#define IIM_ERR_PRGE BIT(7) +#define IIM_ERR_WPE BIT(6) +#define IIM_ERR_OPE BIT(5) +#define IIM_ERR_RPE BIT(4) +#define IIM_ERR_WLRE BIT(3) +#define IIM_ERR_SNSE BIT(2) +#define IIM_ERR_PARITYE BIT(1) #endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 71ebd24..241ad3d 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -502,8 +502,8 @@ enum iomux_gp_func { }; /* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) +#define CCM_RCSR_NF16B BIT(31) +#define CCM_RCSR_NFMS BIT(30) /* WEIM CS control registers */ struct mx31_weim_cscr { @@ -549,11 +549,11 @@ struct esdc_regs { #define CCM_CGR1 (CCM_BASE + 0x24) #define CCM_CGR2 (CCM_BASE + 0x28) -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) +#define CCMR_MDS BIT(7) +#define CCMR_SBYCS BIT(4) +#define CCMR_MPE BIT(3) #define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) +#define CCMR_FPM BIT(1) #define CCMR_CKIH (2 << 1) #define MX31_IIM_BASE_ADDR 0x5001C000 @@ -617,15 +617,15 @@ struct esdc_regs { #define I2C3_BASE_ADDR 0x43f84000 #define I2C3_CLK_OFFSET 30 -#define ESDCTL_SDE (1 << 31) +#define ESDCTL_SDE BIT(31) #define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) +#define ESDCTL_CMD_PRECHARGE BIT(28) #define ESDCTL_CMD_AUTOREFRESH (2 << 28) #define ESDCTL_CMD_LOADMODEREG (3 << 28) #define ESDCTL_CMD_MANUALREFRESH (4 << 28) #define ESDCTL_ROW_13 (2 << 24) #define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) +#define ESDCTL_COL_9 BIT(20) #define ESDCTL_COL(x) ((x) << 20) #define ESDCTL_DSIZ(x) ((x) << 16) #define ESDCTL_SREFR(x) ((x) << 13) @@ -695,7 +695,7 @@ struct esdc_regs { /* bits in the SW_MUX_CTL registers */ #define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) +#define MUX_CTL_OUT_FUNC BIT(4) #define MUX_CTL_OUT_ALT1 (2 << 4) #define MUX_CTL_OUT_ALT2 (3 << 4) #define MUX_CTL_OUT_ALT3 (4 << 4) @@ -703,7 +703,7 @@ struct esdc_regs { #define MUX_CTL_OUT_ALT5 (6 << 4) #define MUX_CTL_OUT_ALT6 (7 << 4) #define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) +#define MUX_CTL_IN_GPIO BIT(0) #define MUX_CTL_IN_FUNC (2 << 0) #define MUX_CTL_IN_ALT1 (4 << 0) #define MUX_CTL_IN_ALT2 (8 << 0) @@ -891,22 +891,22 @@ struct esdc_regs { * CSPI register definitions */ #define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_EN BIT(0) +#define MXC_CSPICTRL_MODE BIT(1) +#define MXC_CSPICTRL_XCH BIT(2) +#define MXC_CSPICTRL_SMC BIT(3) +#define MXC_CSPICTRL_POL BIT(4) +#define MXC_CSPICTRL_PHA BIT(5) +#define MXC_CSPICTRL_SSCTL BIT(6) +#define MXC_CSPICTRL_SSPOL BIT(7) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 8) -#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_TC BIT(8) +#define MXC_CSPICTRL_RXOVF BIT(6) #define MXC_CSPICTRL_MAXBITS 0x1f -#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 4 diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h index a58ebd5..97bf008 100644 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -8,10 +8,10 @@ #define __CPU_ARM1136_MX35_CRM_REGS_H__ /* Register bit definitions */ -#define MXC_CCM_CCMR_WFI (1 << 30) -#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) -#define MXC_CCM_CCMR_VSTBY (1 << 28) -#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_WFI BIT(30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC BIT(29) +#define MXC_CCM_CCMR_VSTBY BIT(28) +#define MXC_CCM_CCMR_WBEN BIT(27) #define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 @@ -20,16 +20,16 @@ #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) -#define MXC_CCM_CCMR_UPE (1 << 9) -#define MXC_CCM_CCMR_MPE (1 << 3) +#define MXC_CCM_CCMR_UPE BIT(9) +#define MXC_CCM_CCMR_MPE BIT(3) -#define MXC_CCM_PDR0_PER_SEL (1 << 26) -#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_PER_SEL BIT(26) +#define MXC_CCM_PDR0_IPU_HND_BYP BIT(23) #define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) #define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) -#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_CKIL_SEL BIT(15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 #define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 @@ -40,7 +40,7 @@ #define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) #define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 #define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) +#define MXC_CCM_PDR1_MSHC_M_U BIT(7) #define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) @@ -50,8 +50,8 @@ #define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR2_CSI_M_U (1 << 7) -#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_CSI_M_U BIT(7) +#define MXC_CCM_PDR2_SSI_M_U BIT(6) #define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 #define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) @@ -59,13 +59,13 @@ #define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) -#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_SPDIF_M_U BIT(22) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 #define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 14) +#define MXC_CCM_PDR3_UART_M_U BIT(14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 #define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC_M_U BIT(6) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 #define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) @@ -77,20 +77,20 @@ #define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 #define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) -#define MXC_CCM_PDR4_USB_M_U (1 << 9) +#define MXC_CCM_PDR4_USB_M_U BIT(9) /* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) -#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_BUS_WIDTH BIT(29) +#define MXC_CCM_RCSR_BUS_16BIT BIT(29) #define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) #define MXC_CCM_RCSR_PAGE_512 (0 << 27) -#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_2K BIT(27) #define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) #define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) -#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) -#define MXC_CCM_RCSR_NF16B (1 << 14) -#define MXC_CCM_RCSR_NFC_4K (1 << 9) -#define MXC_CCM_RCSR_NFC_FMS (1 << 8) +#define MXC_CCM_RCSR_SOFT_RESET BIT(15) +#define MXC_CCM_RCSR_NF16B BIT(14) +#define MXC_CCM_RCSR_NFC_4K BIT(9) +#define MXC_CCM_RCSR_NFC_FMS BIT(8) /* Bit definitions for both MCU, PERIPHERAL PLL control registers */ #define MXC_CCM_PCTL_BRM 0x80000000 @@ -225,8 +225,8 @@ #define MXC_CCM_COSR_CLKOSEL_MASK 0x1F #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 -#define MXC_CCM_COSR_CLKOEN (1 << 5) -#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOEN BIT(5) +#define MXC_CCM_COSR_CLKOUTDIV_1 BIT(6) #define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) #define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) @@ -237,7 +237,7 @@ #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 -#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_EN BIT(24) #define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) #define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 28a47ed..99e4408 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -172,21 +172,21 @@ * CSPI register definitions */ #define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_EN BIT(0) +#define MXC_CSPICTRL_MODE BIT(1) +#define MXC_CSPICTRL_XCH BIT(2) +#define MXC_CSPICTRL_SMC BIT(3) +#define MXC_CSPICTRL_POL BIT(4) +#define MXC_CSPICTRL_PHA BIT(5) +#define MXC_CSPICTRL_SSCTL BIT(6) +#define MXC_CSPICTRL_SSPOL BIT(7) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_TC BIT(7) +#define MXC_CSPICTRL_RXOVF BIT(6) #define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 4 #define MXC_SPI_BASE_ADDRESSES \ @@ -304,11 +304,11 @@ struct esdc_regs { u32 esdcdlyl; }; -#define ESDC_MISC_RST (1 << 1) -#define ESDC_MISC_MDDR_EN (1 << 2) -#define ESDC_MISC_MDDR_DL_RST (1 << 3) -#define ESDC_MISC_DDR_EN (1 << 8) -#define ESDC_MISC_DDR2_EN (1 << 9) +#define ESDC_MISC_RST BIT(1) +#define ESDC_MISC_MDDR_EN BIT(2) +#define ESDC_MISC_MDDR_DL_RST BIT(3) +#define ESDC_MISC_DDR_EN BIT(8) +#define ESDC_MISC_DDR2_EN BIT(9) /* Multi-Layer AHB Crossbar Switch (MAX) registers */ struct max_regs { @@ -369,7 +369,7 @@ struct aips_regs { #define NFMS_NF_DWIDTH 14 #define NFMS_NF_PG_SZ 8 -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +#define CCM_RCSR_NF_16BIT_SEL BIT(14) #endif diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S index b55d2ef..4dbe956 100644 --- a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -85,7 +85,7 @@ * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[6] = IPU1 on priority list BIT(6) = 0x00000040 * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 * ------------ * 0x00000040 diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index b61c7b9..709f2e5 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -306,7 +306,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) /* Define the bits in register CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE BIT(4) /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 @@ -593,8 +593,8 @@ struct mxc_ccm_reg { /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -#define MXC_DPLLC_CTL_HFSM (1 << 7) -#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) +#define MXC_DPLLC_CTL_HFSM BIT(7) +#define MXC_DPLLC_CTL_DPDCK0_2_EN BIT(12) #define MXC_DPLLC_OP_PDF_MASK 0xf #define MXC_DPLLC_OP_MFI_OFFSET 4 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..3729bcb 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -132,23 +132,23 @@ * WEIM CSnGCR1 */ #define CSEN 1 -#define SWR (1 << 1) -#define SRD (1 << 2) -#define MUM (1 << 3) -#define WFL (1 << 4) -#define RFL (1 << 5) -#define CRE (1 << 6) -#define CREP (1 << 7) +#define SWR BIT(1) +#define SRD BIT(2) +#define MUM BIT(3) +#define WFL BIT(4) +#define RFL BIT(5) +#define CRE BIT(6) +#define CREP BIT(7) #define BL(x) (((x) & 0x7) << 8) -#define WC (1 << 11) +#define WC BIT(11) #define BCD(x) (((x) & 0x3) << 12) #define BCS(x) (((x) & 0x3) << 14) #define DSZ(x) (((x) & 0x7) << 16) -#define SP (1 << 19) +#define SP BIT(19) #define CSREC(x) (((x) & 0x7) << 20) -#define AUS (1 << 23) +#define AUS BIT(23) #define GBC(x) (((x) & 0x7) << 24) -#define WP (1 << 27) +#define WP BIT(27) #define PSZ(x) (((x) & 0x0f << 28) /* @@ -156,9 +156,9 @@ */ #define ADH(x) (((x) & 0x3)) #define DAPS(x) (((x) & 0x0f << 4) -#define DAE (1 << 8) -#define DAP (1 << 9) -#define MUX16_BYP (1 << 12) +#define DAE BIT(8) +#define DAP BIT(9) +#define MUX16_BYP BIT(12) /* * WEIM CSnRCR1 @@ -168,7 +168,7 @@ #define OEN(x) (((x) & 0x7) << 8) #define OEA(x) (((x) & 0x7) << 12) #define RADVN(x) (((x) & 0x7) << 16) -#define RAL (1 << 19) +#define RAL BIT(19) #define RADVA(x) (((x) & 0x7) << 20) #define RWSC(x) (((x) & 0x3f) << 24) @@ -176,11 +176,11 @@ * WEIM CSnRCR2 */ #define RBEN(x) (((x) & 0x7)) -#define RBE (1 << 3) +#define RBE BIT(3) #define RBEA(x) (((x) & 0x7) << 4) #define RL(x) (((x) & 0x3) << 8) #define PAT(x) (((x) & 0x7) << 12) -#define APR (1 << 15) +#define APR BIT(15) /* * WEIM CSnWCR1 @@ -194,8 +194,8 @@ #define WADVN(x) (((x) & 0x7) << 18) #define WADVA(x) (((x) & 0x7) << 21) #define WWSC(x) (((x) & 0x3f) << 24) -#define WBED1 (1 << 30) -#define WAL (1 << 31) +#define WBED1 BIT(30) +#define WAL BIT(31) /* * WEIM CSnWCR2 @@ -206,9 +206,9 @@ * CSPI register definitions */ #define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_EN BIT(0) +#define MXC_CSPICTRL_MODE BIT(1) +#define MXC_CSPICTRL_XCH BIT(2) #define MXC_CSPICTRL_MODE_MASK (0xf << 4) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) @@ -216,9 +216,9 @@ #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) #define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MXC_CSPICTRL_TC BIT(7) +#define MXC_CSPICTRL_RXOVF BIT(6) +#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 32 /* Bit position inside CTRL register to be associated with SS */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 0592ce0..88320b4 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -107,12 +107,12 @@ struct mxc_ccm_reg { #endif /* Define the bits in register CCR */ -#define MXC_CCM_CCR_RBC_EN (1 << 27) +#define MXC_CCM_CCR_RBC_EN BIT(27) #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 -#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) -#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_WB_COUNT_OFFSET BIT(16) +#define MXC_CCM_CCR_COSC_EN BIT(12) #ifdef CONFIG_MX6SX #define MXC_CCM_CCR_OSCNT_MASK 0x7F #else @@ -121,25 +121,25 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) -#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK BIT(16) +#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK BIT(17) /* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSC_READY (1 << 5) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) +#define MXC_CCM_CSR_COSC_READY BIT(5) +#define MXC_CCM_CSR_REF_EN_B BIT(0) /* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) -#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) -#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) -#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) -#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) -#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) -#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) -#define MXC_CCM_CCSR_STEP_SEL (1 << 8) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) +#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS BIT(15) +#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS BIT(14) +#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS BIT(13) +#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS BIT(12) +#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS BIT(11) +#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS BIT(10) +#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS BIT(9) +#define MXC_CCM_CCSR_STEP_SEL BIT(8) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL BIT(2) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL BIT(1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL BIT(0) /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 @@ -148,8 +148,8 @@ struct mxc_ccm_reg { /* Define the bits in register CBCDR */ #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) +#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL BIT(26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL BIT(25) #ifndef CONFIG_MX6SX #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 @@ -160,8 +160,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) -#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) +#define MXC_CCM_CBCDR_AXI_ALT_SEL BIT(7) +#define MXC_CCM_CBCDR_AXI_SEL BIT(6) #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) @@ -176,7 +176,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL BIT(20) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 #ifndef CONFIG_MX6SX @@ -188,16 +188,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 #ifndef CONFIG_MX6SX -#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) +#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL BIT(11) #endif -#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) +#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL BIT(10) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #ifndef CONFIG_MX6SX -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) +#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL BIT(1) +#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL BIT(0) #endif /* Define the bits in register CSCMR1 */ @@ -215,10 +215,10 @@ struct mxc_ccm_reg { /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 -#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) -#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) -#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) -#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) +#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL BIT(19) +#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL BIT(18) +#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL BIT(17) +#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL BIT(16) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) @@ -230,7 +230,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 #endif #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK BIT(6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F @@ -242,8 +242,8 @@ struct mxc_ccm_reg { #endif #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 -#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) -#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) +#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV BIT(11) +#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV BIT(10) #ifdef CONFIG_MX6SX #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 @@ -275,11 +275,11 @@ struct mxc_ccm_reg { #endif #ifdef CONFIG_MX6SL #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_SEL BIT(6) #else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F #ifdef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_SEL BIT(6) #endif #endif #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 @@ -333,7 +333,7 @@ struct mxc_ccm_reg { #ifndef CONFIG_MX6SX #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL BIT(28) #endif #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 @@ -410,74 +410,74 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 /* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY BIT(16) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY BIT(5) #ifndef CONFIG_MX6SX -#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY BIT(4) #endif -#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY BIT(3) +#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY BIT(2) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY BIT(1) #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 /* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) -#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) +#define MXC_CCM_CLPCR_MASK_L2CC_IDLE BIT(27) +#define MXC_CCM_CLPCR_MASK_SCU_IDLE BIT(26) #ifndef CONFIG_MX6SX -#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) -#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) -#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) +#define MXC_CCM_CLPCR_MASK_CORE3_WFI BIT(25) +#define MXC_CCM_CLPCR_MASK_CORE2_WFI BIT(24) +#define MXC_CCM_CLPCR_MASK_CORE1_WFI BIT(23) #endif -#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) -#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) +#define MXC_CCM_CLPCR_MASK_CORE0_WFI BIT(22) +#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS BIT(21) #ifndef CONFIG_MX6SX -#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) -#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) +#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS BIT(19) +#define MXC_CCM_CLPCR_WB_CORE_AT_LPM BIT(17) #endif -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) +#define MXC_CCM_CLPCR_WB_PER_AT_LPM BIT(16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN BIT(11) #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 -#define MXC_CCM_CLPCR_VSTBY (1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) -#define MXC_CCM_CLPCR_SBYOS (1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) +#define MXC_CCM_CLPCR_VSTBY BIT(8) +#define MXC_CCM_CLPCR_DIS_REF_OSC BIT(7) +#define MXC_CCM_CLPCR_SBYOS BIT(6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM BIT(5) #ifndef CONFIG_MX6SX #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 -#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY BIT(2) #endif #define MXC_CCM_CLPCR_LPM_MASK 0x3 #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) +#define MXC_CCM_CISR_ARM_PODF_LOADED BIT(26) #ifndef CONFIG_MX6SX -#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) +#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED BIT(23) #endif -#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CISR_COSC_READY (1 << 6) +#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED BIT(22) +#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED BIT(21) +#define MXC_CCM_CISR_AHB_PODF_LOADED BIT(20) +#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED BIT(19) +#define MXC_CCM_CISR_AXI_PODF_LOADED BIT(17) +#define MXC_CCM_CISR_COSC_READY BIT(6) #define MXC_CCM_CISR_LRF_PLL 1 /* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED BIT(26) #ifndef CONFIG_MX6SX -#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) +#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED BIT(23) #endif -#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) +#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED BIT(22) +#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED BIT(21) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED BIT(20) +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED BIT(19) +#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED BIT(17) +#define MXC_CCM_CIMR_MASK_COSC_READY BIT(6) #define MXC_CCM_CIMR_MASK_LRF_PLL 1 /* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET BIT(24) #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 @@ -490,9 +490,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) -#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) +#define MXC_CCM_CGPR_FAST_PLL_EN BIT(16) +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE BIT(4) +#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS BIT(2) #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 /* Define the bits in registers CCGRx */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 9a4ad8b..a98c654 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -551,9 +551,9 @@ struct cspi_regs { * CSPI register definitions */ #define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_EN BIT(0) +#define MXC_CSPICTRL_MODE BIT(1) +#define MXC_CSPICTRL_XCH BIT(2) #define MXC_CSPICTRL_MODE_MASK (0xf << 4) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) @@ -561,9 +561,9 @@ struct cspi_regs { #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) #define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MXC_CSPICTRL_TC BIT(7) +#define MXC_CSPICTRL_RXOVF BIT(6) +#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MAX_SPI_BYTES 32 #define SPI_MAX_NUM 4 @@ -843,12 +843,12 @@ struct wdog_regs { }; #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) -#define PWMCR_DOZEEN (1 << 24) -#define PWMCR_WAITEN (1 << 23) -#define PWMCR_DBGEN (1 << 22) +#define PWMCR_DOZEEN BIT(24) +#define PWMCR_WAITEN BIT(23) +#define PWMCR_DBGEN BIT(22) #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) -#define PWMCR_CLKSRC_IPG (1 << 16) -#define PWMCR_EN (1 << 0) +#define PWMCR_CLKSRC_IPG BIT(16) +#define PWMCR_EN BIT(0) struct pwm_regs { u32 cr; diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index 9b3a91f..474faed 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,14 +15,14 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) -#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) -#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) +#define IOMUXC_GPR1_REF_SSP_EN BIT(16) +#define IOMUXC_GPR1_TEST_POWERDOWN BIT(18) /* * IOMUXC_GPR5 bit fields */ -#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) -#define IOMUXC_GPR5_PCIE_PERST (1 << 18) +#define IOMUXC_GPR5_PCIE_BTNRST BIT(19) +#define IOMUXC_GPR5_PCIE_PERST BIT(18) /* * IOMUXC_GPR8 bit fields @@ -45,11 +45,11 @@ #define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) -#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE BIT(10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) -#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) +#define IOMUXC_GPR12_TEST_POWERDOWN BIT(30) /* * IOMUXC_GPR13 bit fields diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h index d155e3a..17519c9 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h @@ -62,34 +62,34 @@ struct mxs_clkctrl_regs { #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS BIT(18) +#define CLKCTRL_PLL0CTRL0_POWER BIT(16) -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK BIT(31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK BIT(30) #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_BUSY_REF_XTAL BIT(29) +#define CLKCTRL_CPU_BUSY_REF_CPU BIT(28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN BIT(26) #define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) #define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_INTERRUPT_WAIT BIT(12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN BIT(10) #define CLKCTRL_CPU_DIV_CPU_MASK 0x3f #define CLKCTRL_CPU_DIV_CPU_OFFSET 0 -#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) +#define CLKCTRL_HBUS_BUSY BIT(29) +#define CLKCTRL_HBUS_DCP_AS_ENABLE BIT(28) +#define CLKCTRL_HBUS_PXP_AS_ENABLE BIT(27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE BIT(26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE BIT(25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE BIT(24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE BIT(23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE BIT(22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE BIT(21) +#define CLKCTRL_HBUS_AUTO_SLOW_MODE BIT(20) #define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) #define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 #define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) @@ -98,83 +98,83 @@ struct mxs_clkctrl_regs { #define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) #define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) #define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_FRAC_EN BIT(5) #define CLKCTRL_HBUS_DIV_MASK 0x1f #define CLKCTRL_HBUS_DIV_OFFSET 0 -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_BUSY BIT(31) +#define CLKCTRL_XBUS_DIV_FRAC_EN BIT(10) #define CLKCTRL_XBUS_DIV_MASK 0x3ff #define CLKCTRL_XBUS_DIV_OFFSET 0 -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_UART_CLK_GATE BIT(31) +#define CLKCTRL_XTAL_FILT_CLK24M_GATE BIT(30) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE BIT(29) +#define CLKCTRL_XTAL_DRI_CLK24M_GATE BIT(28) +#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE BIT(27) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE BIT(26) #define CLKCTRL_XTAL_DIV_UART_MASK 0x3 #define CLKCTRL_XTAL_DIV_UART_OFFSET 0 -#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) +#define CLKCTRL_PIX_CLKGATE BIT(31) +#define CLKCTRL_PIX_BUSY BIT(29) +#define CLKCTRL_PIX_DIV_FRAC_EN BIT(12) #define CLKCTRL_PIX_DIV_MASK 0xfff #define CLKCTRL_PIX_DIV_OFFSET 0 -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_CLKGATE BIT(31) +#define CLKCTRL_SSP_BUSY BIT(29) +#define CLKCTRL_SSP_DIV_FRAC_EN BIT(9) #define CLKCTRL_SSP_DIV_MASK 0x1ff #define CLKCTRL_SSP_DIV_OFFSET 0 -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_CLKGATE BIT(31) +#define CLKCTRL_GPMI_BUSY BIT(29) +#define CLKCTRL_GPMI_DIV_FRAC_EN BIT(10) #define CLKCTRL_GPMI_DIV_MASK 0x3ff #define CLKCTRL_GPMI_DIV_OFFSET 0 -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) +#define CLKCTRL_SPDIF_CLKGATE BIT(31) -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_CLKGATE BIT(31) +#define CLKCTRL_EMI_SYNC_MODE_EN BIT(30) +#define CLKCTRL_EMI_BUSY_REF_XTAL BIT(29) +#define CLKCTRL_EMI_BUSY_REF_EMI BIT(28) +#define CLKCTRL_EMI_BUSY_REF_CPU BIT(27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE BIT(26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC BIT(17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE BIT(16) #define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) #define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 #define CLKCTRL_EMI_DIV_EMI_MASK 0x3f #define CLKCTRL_EMI_DIV_EMI_OFFSET 0 -#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) +#define CLKCTRL_IR_CLKGATE BIT(31) +#define CLKCTRL_IR_AUTO_DIV BIT(29) +#define CLKCTRL_IR_IR_BUSY BIT(28) +#define CLKCTRL_IR_IROV_BUSY BIT(27) #define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) #define CLKCTRL_IR_IROV_DIV_OFFSET 16 #define CLKCTRL_IR_IR_DIV_MASK 0x3ff #define CLKCTRL_IR_IR_DIV_OFFSET 0 -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_CLKGATE BIT(31) +#define CLKCTRL_SAIF0_BUSY BIT(29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN BIT(16) #define CLKCTRL_SAIF0_DIV_MASK 0xffff #define CLKCTRL_SAIF0_DIV_OFFSET 0 -#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) +#define CLKCTRL_TV_CLK_TV108M_GATE BIT(31) +#define CLKCTRL_TV_CLK_TV_GATE BIT(30) -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) +#define CLKCTRL_ETM_CLKGATE BIT(31) +#define CLKCTRL_ETM_BUSY BIT(29) +#define CLKCTRL_ETM_DIV_FRAC_EN BIT(6) #define CLKCTRL_ETM_DIV_MASK 0x3f #define CLKCTRL_ETM_DIV_OFFSET 0 -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_CLKGATE BIT(7) +#define CLKCTRL_FRAC_STABLE BIT(6) #define CLKCTRL_FRAC_FRAC_MASK 0x3f #define CLKCTRL_FRAC_FRAC_OFFSET 0 #define CLKCTRL_FRAC0_CPU 0 @@ -183,17 +183,17 @@ struct mxs_clkctrl_regs { #define CLKCTRL_FRAC0_IO0 3 #define CLKCTRL_FRAC1_VID 3 -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) - -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) +#define CLKCTRL_CLKSEQ_BYPASS_ETM BIT(8) +#define CLKCTRL_CLKSEQ_BYPASS_CPU BIT(7) +#define CLKCTRL_CLKSEQ_BYPASS_EMI BIT(6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 BIT(5) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI BIT(4) +#define CLKCTRL_CLKSEQ_BYPASS_IR BIT(3) +#define CLKCTRL_CLKSEQ_BYPASS_PIX BIT(1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF BIT(0) + +#define CLKCTRL_RESET_CHIP BIT(1) +#define CLKCTRL_RESET_DIG BIT(0) #define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h index 1490ffd..4ededb3 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h @@ -72,15 +72,15 @@ struct mxs_clkctrl_regs { #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS BIT(18) +#define CLKCTRL_PLL0CTRL0_POWER BIT(17) -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK BIT(31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK BIT(30) #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI BIT(31) #define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) #define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 #define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) @@ -99,44 +99,44 @@ struct mxs_clkctrl_regs { #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) #define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS BIT(18) +#define CLKCTRL_PLL1CTRL0_POWER BIT(17) -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK BIT(31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK BIT(30) #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_CLKGATE BIT(31) #define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) #define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B BIT(26) #define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) #define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) +#define CLKCTRL_PLL2CTRL0_POWER BIT(23) -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_BUSY_REF_XTAL BIT(29) +#define CLKCTRL_CPU_BUSY_REF_CPU BIT(28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN BIT(26) #define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) #define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_INTERRUPT_WAIT BIT(12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN BIT(10) #define CLKCTRL_CPU_DIV_CPU_MASK 0x3f #define CLKCTRL_CPU_DIV_CPU_OFFSET 0 -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_ASM_BUSY BIT(31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE BIT(30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE BIT(29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE BIT(27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE BIT(26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE BIT(25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE BIT(24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE BIT(23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE BIT(22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE BIT(21) +#define CLKCTRL_HBUS_ASM_ENABLE BIT(20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE BIT(19) #define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) #define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 #define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) @@ -145,77 +145,77 @@ struct mxs_clkctrl_regs { #define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) #define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) #define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_FRAC_EN BIT(5) #define CLKCTRL_HBUS_DIV_MASK 0x1f #define CLKCTRL_HBUS_DIV_OFFSET 0 -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_BUSY BIT(31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE BIT(11) +#define CLKCTRL_XBUS_DIV_FRAC_EN BIT(10) #define CLKCTRL_XBUS_DIV_MASK 0x3ff #define CLKCTRL_XBUS_DIV_OFFSET 0 -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_UART_CLK_GATE BIT(31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE BIT(29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE BIT(26) #define CLKCTRL_XTAL_DIV_UART_MASK 0x3 #define CLKCTRL_XTAL_DIV_UART_OFFSET 0 -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_CLKGATE BIT(31) +#define CLKCTRL_SSP_BUSY BIT(29) +#define CLKCTRL_SSP_DIV_FRAC_EN BIT(9) #define CLKCTRL_SSP_DIV_MASK 0x1ff #define CLKCTRL_SSP_DIV_OFFSET 0 -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_CLKGATE BIT(31) +#define CLKCTRL_GPMI_BUSY BIT(29) +#define CLKCTRL_GPMI_DIV_FRAC_EN BIT(10) #define CLKCTRL_GPMI_DIV_MASK 0x3ff #define CLKCTRL_GPMI_DIV_OFFSET 0 -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) +#define CLKCTRL_SPDIF_CLKGATE BIT(31) -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_CLKGATE BIT(31) +#define CLKCTRL_EMI_SYNC_MODE_EN BIT(30) +#define CLKCTRL_EMI_BUSY_REF_XTAL BIT(29) +#define CLKCTRL_EMI_BUSY_REF_EMI BIT(28) +#define CLKCTRL_EMI_BUSY_REF_CPU BIT(27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE BIT(26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC BIT(17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE BIT(16) #define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) #define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 #define CLKCTRL_EMI_DIV_EMI_MASK 0x3f #define CLKCTRL_EMI_DIV_EMI_OFFSET 0 -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_CLKGATE BIT(31) +#define CLKCTRL_SAIF0_BUSY BIT(29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN BIT(16) #define CLKCTRL_SAIF0_DIV_MASK 0xffff #define CLKCTRL_SAIF0_DIV_OFFSET 0 -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_CLKGATE BIT(31) +#define CLKCTRL_SAIF1_BUSY BIT(29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN BIT(16) #define CLKCTRL_SAIF1_DIV_MASK 0xffff #define CLKCTRL_SAIF1_DIV_OFFSET 0 -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_CLKGATE BIT(31) +#define CLKCTRL_DIS_LCDIF_BUSY BIT(29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN BIT(13) #define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff #define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_CLKGATE BIT(31) +#define CLKCTRL_ETM_BUSY BIT(29) +#define CLKCTRL_ETM_DIV_FRAC_EN BIT(7) #define CLKCTRL_ETM_DIV_MASK 0x7f #define CLKCTRL_ETM_DIV_OFFSET 0 -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_SLEEP BIT(31) +#define CLKCTRL_ENET_DISABLE BIT(30) +#define CLKCTRL_ENET_STATUS BIT(29) +#define CLKCTRL_ENET_BUSY_TIME BIT(27) #define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) #define CLKCTRL_ENET_DIV_TIME_OFFSET 21 #define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) @@ -224,21 +224,21 @@ struct mxs_clkctrl_regs { #define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) #define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) #define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) +#define CLKCTRL_ENET_CLK_OUT_EN BIT(18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP BIT(17) +#define CLKCTRL_ENET_RESET_BY_SW BIT(16) -#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_RESETB BIT(30) #define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) #define CLKCTRL_HSADC_FREQDIV_OFFSET 28 -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) +#define CLKCTRL_FLEXCAN_STOP_CAN0 BIT(30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS BIT(29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 BIT(28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS BIT(27) -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_CLKGATE BIT(7) +#define CLKCTRL_FRAC_STABLE BIT(6) #define CLKCTRL_FRAC_FRAC_MASK 0x3f #define CLKCTRL_FRAC_FRAC_OFFSET 0 #define CLKCTRL_FRAC0_CPU 0 @@ -249,26 +249,26 @@ struct mxs_clkctrl_regs { #define CLKCTRL_FRAC1_HSADC 1 #define CLKCTRL_FRAC1_GPMI 2 -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_CPU BIT(18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF BIT(14) #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) +#define CLKCTRL_CLKSEQ_BYPASS_ETM BIT(8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI BIT(7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 BIT(6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 BIT(5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 BIT(4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 BIT(3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI BIT(2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 BIT(1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 BIT(0) -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) +#define CLKCTRL_RESET_WDOG_POR_DISABLE BIT(5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE BIT(4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE BIT(3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT BIT(2) +#define CLKCTRL_RESET_CHIP BIT(1) +#define CLKCTRL_RESET_DIG BIT(0) #define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h index a58303e..4c62730 100644 --- a/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h @@ -31,20 +31,20 @@ struct mxs_i2c_regs { }; #endif -#define I2C_CTRL_SFTRST (1 << 31) -#define I2C_CTRL_CLKGATE (1 << 30) -#define I2C_CTRL_RUN (1 << 29) -#define I2C_CTRL_PREACK (1 << 27) -#define I2C_CTRL_ACKNOWLEDGE (1 << 26) -#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) -#define I2C_CTRL_MULTI_MASTER (1 << 23) -#define I2C_CTRL_CLOCK_HELD (1 << 22) -#define I2C_CTRL_RETAIN_CLOCK (1 << 21) -#define I2C_CTRL_POST_SEND_STOP (1 << 20) -#define I2C_CTRL_PRE_SEND_START (1 << 19) -#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_CTRL_MASTER_MODE (1 << 17) -#define I2C_CTRL_DIRECTION (1 << 16) +#define I2C_CTRL_SFTRST BIT(31) +#define I2C_CTRL_CLKGATE BIT(30) +#define I2C_CTRL_RUN BIT(29) +#define I2C_CTRL_PREACK BIT(27) +#define I2C_CTRL_ACKNOWLEDGE BIT(26) +#define I2C_CTRL_SEND_NAK_ON_LAST BIT(25) +#define I2C_CTRL_MULTI_MASTER BIT(23) +#define I2C_CTRL_CLOCK_HELD BIT(22) +#define I2C_CTRL_RETAIN_CLOCK BIT(21) +#define I2C_CTRL_POST_SEND_STOP BIT(20) +#define I2C_CTRL_PRE_SEND_START BIT(19) +#define I2C_CTRL_SLAVE_ADDRESS_ENABLE BIT(18) +#define I2C_CTRL_MASTER_MODE BIT(17) +#define I2C_CTRL_DIRECTION BIT(16) #define I2C_CTRL_XFER_COUNT_MASK 0xffff #define I2C_CTRL_XFER_COUNT_OFFSET 0 @@ -63,86 +63,86 @@ struct mxs_i2c_regs { #define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff #define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 -#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) -#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) -#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) -#define I2C_CTRL1_ACK_MODE (1 << 27) -#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) -#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) -#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) +#define I2C_CTRL1_RD_QUEUE_IRQ BIT(30) +#define I2C_CTRL1_WR_QUEUE_IRQ BIT(29) +#define I2C_CTRL1_CLR_GOT_A_NAK BIT(28) +#define I2C_CTRL1_ACK_MODE BIT(27) +#define I2C_CTRL1_FORCE_DATA_IDLE BIT(26) +#define I2C_CTRL1_FORCE_CLK_IDLE BIT(25) +#define I2C_CTRL1_BCAST_SLAVE_EN BIT(24) #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) #define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 -#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) -#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) -#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) -#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) -#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) -#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) -#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) -#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) -#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) -#define I2C_CTRL1_SLAVE_IRQ (1 << 0) - -#define I2C_STAT_MASTER_PRESENT (1 << 31) -#define I2C_STAT_SLAVE_PRESENT (1 << 30) -#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) -#define I2C_STAT_GOT_A_NAK (1 << 28) +#define I2C_CTRL1_BUS_FREE_IRQ_EN BIT(15) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN BIT(14) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN BIT(13) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN BIT(12) +#define I2C_CTRL1_EARLY_TERM_IRQ_EN BIT(11) +#define I2C_CTRL1_MASTER_LOSS_IRQ_EN BIT(10) +#define I2C_CTRL1_SLAVE_STOP_IRQ_EN BIT(9) +#define I2C_CTRL1_SLAVE_IRQ_EN BIT(8) +#define I2C_CTRL1_BUS_FREE_IRQ BIT(7) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ BIT(6) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ BIT(5) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ BIT(4) +#define I2C_CTRL1_EARLY_TERM_IRQ BIT(3) +#define I2C_CTRL1_MASTER_LOSS_IRQ BIT(2) +#define I2C_CTRL1_SLAVE_STOP_IRQ BIT(1) +#define I2C_CTRL1_SLAVE_IRQ BIT(0) + +#define I2C_STAT_MASTER_PRESENT BIT(31) +#define I2C_STAT_SLAVE_PRESENT BIT(30) +#define I2C_STAT_ANY_ENABLED_IRQ BIT(29) +#define I2C_STAT_GOT_A_NAK BIT(28) #define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) #define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 -#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) -#define I2C_STAT_SLAVE_FOUND (1 << 14) -#define I2C_STAT_SLAVE_SEARCHING (1 << 13) -#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) -#define I2C_STAT_BUS_BUSY (1 << 11) -#define I2C_STAT_CLK_GEN_BUSY (1 << 10) -#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) -#define I2C_STAT_SLAVE_BUSY (1 << 8) -#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) -#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) -#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) -#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) -#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) -#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) -#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) -#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) +#define I2C_STAT_SLAVE_ADDR_EQ_ZERO BIT(15) +#define I2C_STAT_SLAVE_FOUND BIT(14) +#define I2C_STAT_SLAVE_SEARCHING BIT(13) +#define I2C_STAT_DATA_ENGING_DMA_WAIT BIT(12) +#define I2C_STAT_BUS_BUSY BIT(11) +#define I2C_STAT_CLK_GEN_BUSY BIT(10) +#define I2C_STAT_DATA_ENGINE_BUSY BIT(9) +#define I2C_STAT_SLAVE_BUSY BIT(8) +#define I2C_STAT_BUS_FREE_IRQ_SUMMARY BIT(7) +#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY BIT(6) +#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY BIT(5) +#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY BIT(4) +#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY BIT(3) +#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY BIT(2) +#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY BIT(1) +#define I2C_STAT_SLAVE_IRQ_SUMMARY BIT(0) #define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) #define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 #define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) #define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 -#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) -#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) -#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) -#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) -#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) -#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) - -#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) -#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) +#define I2C_QUEUECTRL_QUEUE_RUN BIT(5) +#define I2C_QUEUECTRL_RD_CLEAR BIT(4) +#define I2C_QUEUECTRL_WR_CLEAR BIT(3) +#define I2C_QUEUECTRL_PIO_QUEUE_MODE BIT(2) +#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN BIT(1) +#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN BIT(0) + +#define I2C_QUEUESTAT_RD_QUEUE_FULL BIT(14) +#define I2C_QUEUESTAT_RD_QUEUE_EMPTY BIT(13) #define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) #define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 -#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) -#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) +#define I2C_QUEUESTAT_WR_QUEUE_FULL BIT(6) +#define I2C_QUEUESTAT_WR_QUEUE_EMPTY BIT(5) #define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f #define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 -#define I2C_QUEUECMD_PREACK (1 << 27) -#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) -#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) -#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) -#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) -#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) -#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) -#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) -#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_QUEUECMD_MASTER_MODE (1 << 17) -#define I2C_QUEUECMD_DIRECTION (1 << 16) +#define I2C_QUEUECMD_PREACK BIT(27) +#define I2C_QUEUECMD_ACKNOWLEDGE BIT(26) +#define I2C_QUEUECMD_SEND_NAK_ON_LAST BIT(25) +#define I2C_QUEUECMD_MULTI_MASTER BIT(23) +#define I2C_QUEUECMD_CLOCK_HELD BIT(22) +#define I2C_QUEUECMD_RETAIN_CLOCK BIT(21) +#define I2C_QUEUECMD_POST_SEND_STOP BIT(20) +#define I2C_QUEUECMD_PRE_SEND_START BIT(19) +#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE BIT(18) +#define I2C_QUEUECMD_MASTER_MODE BIT(17) +#define I2C_QUEUECMD_DIRECTION BIT(16) #define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff #define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 @@ -152,37 +152,37 @@ struct mxs_i2c_regs { #define I2C_DATA_DATA_MASK 0xffffffff #define I2C_DATA_DATA_OFFSET 0 -#define I2C_DEBUG0_DMAREQ (1 << 31) -#define I2C_DEBUG0_DMAENDCMD (1 << 30) -#define I2C_DEBUG0_DMAKICK (1 << 29) -#define I2C_DEBUG0_DMATERMINATE (1 << 28) +#define I2C_DEBUG0_DMAREQ BIT(31) +#define I2C_DEBUG0_DMAENDCMD BIT(30) +#define I2C_DEBUG0_DMAKICK BIT(29) +#define I2C_DEBUG0_DMATERMINATE BIT(28) #define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) #define I2C_DEBUG0_STATE_VALUE_OFFSET 26 #define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) #define I2C_DEBUG0_DMA_STATE_OFFSET 16 -#define I2C_DEBUG0_START_TOGGLE (1 << 15) -#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) -#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) -#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) -#define I2C_DEBUG0_STATE_LATCH (1 << 11) -#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) +#define I2C_DEBUG0_START_TOGGLE BIT(15) +#define I2C_DEBUG0_STOP_TOGGLE BIT(14) +#define I2C_DEBUG0_GRAB_TOGGLE BIT(13) +#define I2C_DEBUG0_CHANGE_TOGGLE BIT(12) +#define I2C_DEBUG0_STATE_LATCH BIT(11) +#define I2C_DEBUG0_SLAVE_HOLD_CLK BIT(10) #define I2C_DEBUG0_STATE_STATE_MASK 0x3ff #define I2C_DEBUG0_STATE_STATE_OFFSET 0 -#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) -#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) +#define I2C_DEBUG1_I2C_CLK_IN BIT(31) +#define I2C_DEBUG1_I2C_DATA_IN BIT(30) #define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) #define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 #define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) #define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 #define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) #define I2C_DEBUG1_LST_MODE_OFFSET 9 -#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) -#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) -#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) -#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) -#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) -#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) +#define I2C_DEBUG1_LOCAL_SLAVE_TEST BIT(8) +#define I2C_DEBUG1_FORCE_CLK_ON BIT(4) +#define I2C_DEBUG1_FORCE_ABR_LOSS BIT(3) +#define I2C_DEBUG1_FORCE_RCV_ACK BIT(2) +#define I2C_DEBUG1_FORCE_I2C_DATA_OE BIT(1) +#define I2C_DEBUG1_FORCE_I2C_CLK_OE BIT(0) #define I2C_VERSION_MAJOR_MASK (0xff << 24) #define I2C_VERSION_MAJOR_OFFSET 24 diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h index 8915d84..ce282a0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h @@ -65,19 +65,19 @@ struct mxs_lcdif_regs { }; #endif -#define LCDIF_CTRL_SFTRST (1 << 31) -#define LCDIF_CTRL_CLKGATE (1 << 30) -#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) -#define LCDIF_CTRL_READ_WRITEB (1 << 28) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) -#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) +#define LCDIF_CTRL_SFTRST BIT(31) +#define LCDIF_CTRL_CLKGATE BIT(30) +#define LCDIF_CTRL_YCBCR422_INPUT BIT(29) +#define LCDIF_CTRL_READ_WRITEB BIT(28) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE BIT(27) +#define LCDIF_CTRL_DATA_SHIFT_DIR BIT(26) #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 -#define LCDIF_CTRL_DVI_MODE (1 << 20) -#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) -#define LCDIF_CTRL_VSYNC_MODE (1 << 18) -#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) -#define LCDIF_CTRL_DATA_SELECT (1 << 16) +#define LCDIF_CTRL_DVI_MODE BIT(20) +#define LCDIF_CTRL_BYPASS_COUNT BIT(19) +#define LCDIF_CTRL_VSYNC_MODE BIT(18) +#define LCDIF_CTRL_DOTCLK_MODE BIT(17) +#define LCDIF_CTRL_DATA_SELECT BIT(16) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) @@ -85,43 +85,43 @@ struct mxs_lcdif_regs { #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT BIT(10) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) -#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) +#define LCDIF_CTRL_WORD_LENGTH_8BIT BIT(8) #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) -#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) -#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) -#define LCDIF_CTRL_RUN (1 << 0) - -#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) -#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) -#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) -#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC BIT(7) +#define LCDIF_CTRL_LCDIF_MASTER BIT(5) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT BIT(3) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT BIT(2) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT BIT(1) +#define LCDIF_CTRL_RUN BIT(0) + +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB BIT(27) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN BIT(26) +#define LCDIF_CTRL1_BM_ERROR_IRQ BIT(25) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW BIT(24) +#define LCDIF_CTRL1_INTERLACE_FIELDS BIT(23) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD BIT(22) +#define LCDIF_CTRL1_FIFO_CLEAR BIT(21) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS BIT(20) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) -#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) -#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) -#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) -#define LCDIF_CTRL1_MODE86 (1 << 1) -#define LCDIF_CTRL1_RESET (1 << 0) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN BIT(15) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN BIT(14) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN BIT(12) +#define LCDIF_CTRL1_OVERFLOW_IRQ BIT(11) +#define LCDIF_CTRL1_UNDERFLOW_IRQ BIT(10) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ BIT(9) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ BIT(8) +#define LCDIF_CTRL1_BUSY_ENABLE BIT(2) +#define LCDIF_CTRL1_MODE86 BIT(1) +#define LCDIF_CTRL1_RESET BIT(0) #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 @@ -130,7 +130,7 @@ struct mxs_lcdif_regs { #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) -#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) +#define LCDIF_CTRL2_BURST_LEN_8 BIT(20) #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) @@ -147,9 +147,9 @@ struct mxs_lcdif_regs { #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) -#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) -#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) -#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) +#define LCDIF_CTRL2_READ_PACK_DIR BIT(10) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT BIT(9) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT BIT(8) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) @@ -175,16 +175,16 @@ struct mxs_lcdif_regs { #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) #define LCDIF_TIMING_DATA_SETUP_OFFSET 0 -#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) -#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) -#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) -#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) -#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) -#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) -#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) -#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) +#define LCDIF_VDCTRL0_VSYNC_OEB BIT(29) +#define LCDIF_VDCTRL0_ENABLE_PRESENT BIT(28) +#define LCDIF_VDCTRL0_VSYNC_POL BIT(27) +#define LCDIF_VDCTRL0_HSYNC_POL BIT(26) +#define LCDIF_VDCTRL0_DOTCLK_POL BIT(25) +#define LCDIF_VDCTRL0_ENABLE_POL BIT(24) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT BIT(21) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20) +#define LCDIF_VDCTRL0_HALF_LINE BIT(19) +#define LCDIF_VDCTRL0_HALF_LINE_MODE BIT(18) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 @@ -201,8 +201,8 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) -#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS BIT(29) +#define LCDIF_VDCTRL3_VSYNC_ONLY BIT(28) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) @@ -210,7 +210,7 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON BIT(18) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h index 74f9f76..5b2b1a9 100644 --- a/arch/arm/include/asm/arch-mxs/regs-lradc.h +++ b/arch/arm/include/asm/arch-mxs/regs-lradc.h @@ -44,57 +44,57 @@ struct mxs_lradc_regs { }; #endif -#define LRADC_CTRL0_SFTRST (1 << 31) -#define LRADC_CTRL0_CLKGATE (1 << 30) -#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) -#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) -#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) -#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) -#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) -#define LRADC_CTRL0_YNLRSW (1 << 21) +#define LRADC_CTRL0_SFTRST BIT(31) +#define LRADC_CTRL0_CLKGATE BIT(30) +#define LRADC_CTRL0_ONCHIP_GROUNDREF BIT(26) +#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE BIT(25) +#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE BIT(24) +#define LRADC_CTRL0_TOUCH_DETECT_ENABLE BIT(23) +#define LRADC_CTRL0_TOUCH_SCREEN_TYPE BIT(22) +#define LRADC_CTRL0_YNLRSW BIT(21) #define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) #define LRADC_CTRL0_YPLLSW_OFFSET 19 #define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) #define LRADC_CTRL0_XNURSW_OFFSET 17 -#define LRADC_CTRL0_XPULSW (1 << 16) +#define LRADC_CTRL0_XPULSW BIT(16) #define LRADC_CTRL0_SCHEDULE_MASK 0xff #define LRADC_CTRL0_SCHEDULE_OFFSET 0 -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) -#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) -#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) -#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) -#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) -#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) -#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) -#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) -#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) -#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) -#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) -#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) -#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) -#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) -#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) -#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) -#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN BIT(28) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN BIT(27) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN BIT(26) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN BIT(25) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24) +#define LRADC_CTRL1_LRADC7_IRQ_EN BIT(23) +#define LRADC_CTRL1_LRADC6_IRQ_EN BIT(22) +#define LRADC_CTRL1_LRADC5_IRQ_EN BIT(21) +#define LRADC_CTRL1_LRADC4_IRQ_EN BIT(20) +#define LRADC_CTRL1_LRADC3_IRQ_EN BIT(19) +#define LRADC_CTRL1_LRADC2_IRQ_EN BIT(18) +#define LRADC_CTRL1_LRADC1_IRQ_EN BIT(17) +#define LRADC_CTRL1_LRADC0_IRQ_EN BIT(16) +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ BIT(12) +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ BIT(11) +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ BIT(10) +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ BIT(9) +#define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8) +#define LRADC_CTRL1_LRADC7_IRQ BIT(7) +#define LRADC_CTRL1_LRADC6_IRQ BIT(6) +#define LRADC_CTRL1_LRADC5_IRQ BIT(5) +#define LRADC_CTRL1_LRADC4_IRQ BIT(4) +#define LRADC_CTRL1_LRADC3_IRQ BIT(3) +#define LRADC_CTRL1_LRADC2_IRQ BIT(2) +#define LRADC_CTRL1_LRADC1_IRQ BIT(1) +#define LRADC_CTRL1_LRADC0_IRQ BIT(0) #define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 -#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) +#define LRADC_CTRL2_TEMPSENSE_PWD BIT(15) #define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) #define LRADC_CTRL2_VTHSENSE_OFFSET 13 -#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) +#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS BIT(12) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 BIT(9) +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 BIT(8) #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) #define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 #define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) @@ -137,8 +137,8 @@ struct mxs_lradc_regs { #define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) #define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) #define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) -#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) -#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) +#define LRADC_CTRL3_FORCE_ANALOG_PWUP BIT(23) +#define LRADC_CTRL3_FORCE_ANALOG_PWDN BIT(22) #define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) #define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 #define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) @@ -151,29 +151,29 @@ struct mxs_lradc_regs { #define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) #define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) #define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) -#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) -#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) +#define LRADC_CTRL3_DELAY_CLOCK BIT(1) +#define LRADC_CTRL3_INVERT_CLOCK BIT(0) -#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) -#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) -#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) -#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) -#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) -#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) -#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) -#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) -#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) -#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) -#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) -#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) -#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) -#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) -#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) -#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) +#define LRADC_STATUS_BUTTON1_PRESENT BIT(28) +#define LRADC_STATUS_BUTTON0_PRESENT BIT(27) +#define LRADC_STATUS_TEMP1_PRESENT BIT(26) +#define LRADC_STATUS_TEMP0_PRESENT BIT(25) +#define LRADC_STATUS_TOUCH_PANEL_PRESENT BIT(24) +#define LRADC_STATUS_CHANNEL7_PRESENT BIT(23) +#define LRADC_STATUS_CHANNEL6_PRESENT BIT(22) +#define LRADC_STATUS_CHANNEL5_PRESENT BIT(21) +#define LRADC_STATUS_CHANNEL4_PRESENT BIT(20) +#define LRADC_STATUS_CHANNEL3_PRESENT BIT(19) +#define LRADC_STATUS_CHANNEL2_PRESENT BIT(18) +#define LRADC_STATUS_CHANNEL1_PRESENT BIT(17) +#define LRADC_STATUS_CHANNEL0_PRESENT BIT(16) +#define LRADC_STATUS_BUTTON1_DETECT_RAW BIT(2) +#define LRADC_STATUS_BUTTON0_DETECT_RAW BIT(1) +#define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0) -#define LRADC_CH_TOGGLE (1 << 31) -#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) -#define LRADC_CH_ACCUMULATE (1 << 29) +#define LRADC_CH_TOGGLE BIT(31) +#define LRADC_CH7_TESTMODE_TOGGLE BIT(30) +#define LRADC_CH_ACCUMULATE BIT(29) #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) #define LRADC_CH_NUM_SAMPLES_OFFSET 24 #define LRADC_CH_VALUE_MASK 0x3ffff @@ -181,7 +181,7 @@ struct mxs_lradc_regs { #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 -#define LRADC_DELAY_KICK (1 << 20) +#define LRADC_DELAY_KICK BIT(20) #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) @@ -198,11 +198,11 @@ struct mxs_lradc_regs { #define LRADC_DEBUG1_REQUEST_OFFSET 16 #define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) #define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 -#define LRADC_DEBUG1_TESTMODE6 (1 << 2) -#define LRADC_DEBUG1_TESTMODE5 (1 << 1) -#define LRADC_DEBUG1_TESTMODE (1 << 0) +#define LRADC_DEBUG1_TESTMODE6 BIT(2) +#define LRADC_DEBUG1_TESTMODE5 BIT(1) +#define LRADC_DEBUG1_TESTMODE BIT(0) -#define LRADC_CONVERSION_AUTOMATIC (1 << 20) +#define LRADC_CONVERSION_AUTOMATIC BIT(20) #define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) #define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 #define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) @@ -356,8 +356,8 @@ struct mxs_lradc_regs { #define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) #define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) -#define LRADC_THRESHOLD_ENABLE (1 << 24) -#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) +#define LRADC_THRESHOLD_ENABLE BIT(24) +#define LRADC_THRESHOLD_BATTCHRG_DISABLE BIT(23) #define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) #define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 #define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h index bd80ac7..430fd8f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h @@ -66,10 +66,10 @@ struct mxs_ocotp_regs { #define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) #define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 #define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) -#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -#define OCOTP_CTRL_ERROR (1 << 9) -#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_RELOAD_SHADOWS BIT(13) +#define OCOTP_CTRL_RD_BANK_OPEN BIT(12) +#define OCOTP_CTRL_ERROR BIT(9) +#define OCOTP_CTRL_BUSY BIT(8) #define OCOTP_CTRL_ADDR_MASK 0x3f #define OCOTP_CTRL_ADDR_OFFSET 0 @@ -88,40 +88,40 @@ struct mxs_ocotp_regs { #define OCOTP_SWCAP_BITS_MASK 0xffffffff #define OCOTP_SWCAP_BITS_OFFSET 0 -#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) -#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) - -#define OCOTP_LOCK_ROM7 (1 << 31) -#define OCOTP_LOCK_ROM6 (1 << 30) -#define OCOTP_LOCK_ROM5 (1 << 29) -#define OCOTP_LOCK_ROM4 (1 << 28) -#define OCOTP_LOCK_ROM3 (1 << 27) -#define OCOTP_LOCK_ROM2 (1 << 26) -#define OCOTP_LOCK_ROM1 (1 << 25) -#define OCOTP_LOCK_ROM0 (1 << 24) -#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) -#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) -#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) -#define OCOTP_LOCK_PIN (1 << 20) -#define OCOTP_LOCK_OPS (1 << 19) -#define OCOTP_LOCK_UN2 (1 << 18) -#define OCOTP_LOCK_UN1 (1 << 17) -#define OCOTP_LOCK_UN0 (1 << 16) -#define OCOTP_LOCK_SRK (1 << 15) +#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT BIT(2) +#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT BIT(1) + +#define OCOTP_LOCK_ROM7 BIT(31) +#define OCOTP_LOCK_ROM6 BIT(30) +#define OCOTP_LOCK_ROM5 BIT(29) +#define OCOTP_LOCK_ROM4 BIT(28) +#define OCOTP_LOCK_ROM3 BIT(27) +#define OCOTP_LOCK_ROM2 BIT(26) +#define OCOTP_LOCK_ROM1 BIT(25) +#define OCOTP_LOCK_ROM0 BIT(24) +#define OCOTP_LOCK_HWSW_SHADOW_ALT BIT(23) +#define OCOTP_LOCK_CRYPTODCP_ALT BIT(22) +#define OCOTP_LOCK_CRYPTOKEY_ALT BIT(21) +#define OCOTP_LOCK_PIN BIT(20) +#define OCOTP_LOCK_OPS BIT(19) +#define OCOTP_LOCK_UN2 BIT(18) +#define OCOTP_LOCK_UN1 BIT(17) +#define OCOTP_LOCK_UN0 BIT(16) +#define OCOTP_LOCK_SRK BIT(15) #define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) #define OCOTP_LOCK_UNALLOCATED_OFFSET 12 -#define OCOTP_LOCK_SRK_SHADOW (1 << 11) -#define OCOTP_LOCK_ROM_SHADOW (1 << 10) -#define OCOTP_LOCK_CUSTCAP (1 << 9) -#define OCOTP_LOCK_HWSW (1 << 8) -#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) -#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) -#define OCOTP_LOCK_CRYPTODCP (1 << 5) -#define OCOTP_LOCK_CRYPTOKEY (1 << 4) -#define OCOTP_LOCK_CUST3 (1 << 3) -#define OCOTP_LOCK_CUST2 (1 << 2) -#define OCOTP_LOCK_CUST1 (1 << 1) -#define OCOTP_LOCK_CUST0 (1 << 0) +#define OCOTP_LOCK_SRK_SHADOW BIT(11) +#define OCOTP_LOCK_ROM_SHADOW BIT(10) +#define OCOTP_LOCK_CUSTCAP BIT(9) +#define OCOTP_LOCK_HWSW BIT(8) +#define OCOTP_LOCK_CUSTCAP_SHADOW BIT(7) +#define OCOTP_LOCK_HWSW_SHADOW BIT(6) +#define OCOTP_LOCK_CRYPTODCP BIT(5) +#define OCOTP_LOCK_CRYPTOKEY BIT(4) +#define OCOTP_LOCK_CUST3 BIT(3) +#define OCOTP_LOCK_CUST2 BIT(2) +#define OCOTP_LOCK_CUST1 BIT(1) +#define OCOTP_LOCK_CUST0 BIT(0) #define OCOTP_OPS_BITS_MASK 0xffffffff #define OCOTP_OPS_BITS_OFFSET 0 @@ -141,11 +141,11 @@ struct mxs_ocotp_regs { #define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 #define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) #define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 -#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) -#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) -#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) -#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) -#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) +#define OCOTP_ROM_EMMC_USE_DDR BIT(7) +#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ BIT(6) +#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM BIT(5) +#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT BIT(4) +#define OCOTP_ROM_SD_MBR_BOOT BIT(3) #define OCOTP_SRK_BITS_MASK 0xffffffff #define OCOTP_SRK_BITS_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h index 251fe66..235c824 100644 --- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h @@ -143,18 +143,18 @@ struct mxs_pinctrl_regs { }; #endif -#define PINCTRL_CTRL_SFTRST (1 << 31) -#define PINCTRL_CTRL_CLKGATE (1 << 30) -#define PINCTRL_CTRL_PRESENT4 (1 << 24) -#define PINCTRL_CTRL_PRESENT3 (1 << 23) -#define PINCTRL_CTRL_PRESENT2 (1 << 22) -#define PINCTRL_CTRL_PRESENT1 (1 << 21) -#define PINCTRL_CTRL_PRESENT0 (1 << 20) -#define PINCTRL_CTRL_IRQOUT4 (1 << 4) -#define PINCTRL_CTRL_IRQOUT3 (1 << 3) -#define PINCTRL_CTRL_IRQOUT2 (1 << 2) -#define PINCTRL_CTRL_IRQOUT1 (1 << 1) -#define PINCTRL_CTRL_IRQOUT0 (1 << 0) +#define PINCTRL_CTRL_SFTRST BIT(31) +#define PINCTRL_CTRL_CLKGATE BIT(30) +#define PINCTRL_CTRL_PRESENT4 BIT(24) +#define PINCTRL_CTRL_PRESENT3 BIT(23) +#define PINCTRL_CTRL_PRESENT2 BIT(22) +#define PINCTRL_CTRL_PRESENT1 BIT(21) +#define PINCTRL_CTRL_PRESENT0 BIT(20) +#define PINCTRL_CTRL_IRQOUT4 BIT(4) +#define PINCTRL_CTRL_IRQOUT3 BIT(3) +#define PINCTRL_CTRL_IRQOUT2 BIT(2) +#define PINCTRL_CTRL_IRQOUT1 BIT(1) +#define PINCTRL_CTRL_IRQOUT0 BIT(0) #define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) #define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 @@ -520,583 +520,583 @@ struct mxs_pinctrl_regs { #define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) #define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 -#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) +#define PINCTRL_DRIVE0_BANK0_PIN07_V BIT(30) #define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) +#define PINCTRL_DRIVE0_BANK0_PIN06_V BIT(26) #define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) +#define PINCTRL_DRIVE0_BANK0_PIN05_V BIT(22) #define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) +#define PINCTRL_DRIVE0_BANK0_PIN04_V BIT(18) #define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) +#define PINCTRL_DRIVE0_BANK0_PIN03_V BIT(14) #define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) +#define PINCTRL_DRIVE0_BANK0_PIN02_V BIT(10) #define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) +#define PINCTRL_DRIVE0_BANK0_PIN01_V BIT(6) #define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) +#define PINCTRL_DRIVE0_BANK0_PIN00_V BIT(2) #define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 -#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) +#define PINCTRL_DRIVE2_BANK0_PIN23_V BIT(30) #define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) +#define PINCTRL_DRIVE2_BANK0_PIN22_V BIT(26) #define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) +#define PINCTRL_DRIVE2_BANK0_PIN21_V BIT(22) #define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) +#define PINCTRL_DRIVE2_BANK0_PIN20_V BIT(18) #define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) +#define PINCTRL_DRIVE2_BANK0_PIN19_V BIT(14) #define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) +#define PINCTRL_DRIVE2_BANK0_PIN18_V BIT(10) #define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) +#define PINCTRL_DRIVE2_BANK0_PIN17_V BIT(6) #define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) +#define PINCTRL_DRIVE2_BANK0_PIN16_V BIT(2) #define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 -#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) +#define PINCTRL_DRIVE3_BANK0_PIN28_V BIT(18) #define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) +#define PINCTRL_DRIVE3_BANK0_PIN27_V BIT(14) #define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) +#define PINCTRL_DRIVE3_BANK0_PIN26_V BIT(10) #define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) +#define PINCTRL_DRIVE3_BANK0_PIN25_V BIT(6) #define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) +#define PINCTRL_DRIVE3_BANK0_PIN24_V BIT(2) #define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 -#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) +#define PINCTRL_DRIVE4_BANK1_PIN07_V BIT(30) #define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) +#define PINCTRL_DRIVE4_BANK1_PIN06_V BIT(26) #define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) +#define PINCTRL_DRIVE4_BANK1_PIN05_V BIT(22) #define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) +#define PINCTRL_DRIVE4_BANK1_PIN04_V BIT(18) #define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) +#define PINCTRL_DRIVE4_BANK1_PIN03_V BIT(14) #define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) +#define PINCTRL_DRIVE4_BANK1_PIN02_V BIT(10) #define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) +#define PINCTRL_DRIVE4_BANK1_PIN01_V BIT(6) #define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) +#define PINCTRL_DRIVE4_BANK1_PIN00_V BIT(2) #define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 -#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) +#define PINCTRL_DRIVE5_BANK1_PIN15_V BIT(30) #define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) +#define PINCTRL_DRIVE5_BANK1_PIN14_V BIT(26) #define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) +#define PINCTRL_DRIVE5_BANK1_PIN13_V BIT(22) #define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) +#define PINCTRL_DRIVE5_BANK1_PIN12_V BIT(18) #define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) +#define PINCTRL_DRIVE5_BANK1_PIN11_V BIT(14) #define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) +#define PINCTRL_DRIVE5_BANK1_PIN10_V BIT(10) #define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) +#define PINCTRL_DRIVE5_BANK1_PIN09_V BIT(6) #define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) +#define PINCTRL_DRIVE5_BANK1_PIN08_V BIT(2) #define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 -#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) +#define PINCTRL_DRIVE6_BANK1_PIN23_V BIT(30) #define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) +#define PINCTRL_DRIVE6_BANK1_PIN22_V BIT(26) #define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) +#define PINCTRL_DRIVE6_BANK1_PIN21_V BIT(22) #define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) +#define PINCTRL_DRIVE6_BANK1_PIN20_V BIT(18) #define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) +#define PINCTRL_DRIVE6_BANK1_PIN19_V BIT(14) #define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) +#define PINCTRL_DRIVE6_BANK1_PIN18_V BIT(10) #define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) +#define PINCTRL_DRIVE6_BANK1_PIN17_V BIT(6) #define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) +#define PINCTRL_DRIVE6_BANK1_PIN16_V BIT(2) #define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 -#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) +#define PINCTRL_DRIVE7_BANK1_PIN31_V BIT(30) #define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 -#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) +#define PINCTRL_DRIVE7_BANK1_PIN30_V BIT(26) #define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) +#define PINCTRL_DRIVE7_BANK1_PIN29_V BIT(22) #define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) +#define PINCTRL_DRIVE7_BANK1_PIN28_V BIT(18) #define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) +#define PINCTRL_DRIVE7_BANK1_PIN27_V BIT(14) #define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) +#define PINCTRL_DRIVE7_BANK1_PIN26_V BIT(10) #define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) +#define PINCTRL_DRIVE7_BANK1_PIN25_V BIT(6) #define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) +#define PINCTRL_DRIVE7_BANK1_PIN24_V BIT(2) #define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 -#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) +#define PINCTRL_DRIVE8_BANK2_PIN07_V BIT(30) #define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) +#define PINCTRL_DRIVE8_BANK2_PIN06_V BIT(26) #define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) +#define PINCTRL_DRIVE8_BANK2_PIN05_V BIT(22) #define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) +#define PINCTRL_DRIVE8_BANK2_PIN04_V BIT(18) #define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) +#define PINCTRL_DRIVE8_BANK2_PIN03_V BIT(14) #define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) +#define PINCTRL_DRIVE8_BANK2_PIN02_V BIT(10) #define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) +#define PINCTRL_DRIVE8_BANK2_PIN01_V BIT(6) #define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) +#define PINCTRL_DRIVE8_BANK2_PIN00_V BIT(2) #define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 -#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) +#define PINCTRL_DRIVE9_BANK2_PIN15_V BIT(30) #define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) +#define PINCTRL_DRIVE9_BANK2_PIN14_V BIT(26) #define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) +#define PINCTRL_DRIVE9_BANK2_PIN13_V BIT(22) #define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) +#define PINCTRL_DRIVE9_BANK2_PIN12_V BIT(18) #define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) +#define PINCTRL_DRIVE9_BANK2_PIN10_V BIT(10) #define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) +#define PINCTRL_DRIVE9_BANK2_PIN09_V BIT(6) #define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) +#define PINCTRL_DRIVE9_BANK2_PIN08_V BIT(2) #define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 -#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) +#define PINCTRL_DRIVE10_BANK2_PIN21_V BIT(22) #define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) +#define PINCTRL_DRIVE10_BANK2_PIN20_V BIT(18) #define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) +#define PINCTRL_DRIVE10_BANK2_PIN19_V BIT(14) #define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) +#define PINCTRL_DRIVE10_BANK2_PIN18_V BIT(10) #define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) +#define PINCTRL_DRIVE10_BANK2_PIN17_V BIT(6) #define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) +#define PINCTRL_DRIVE10_BANK2_PIN16_V BIT(2) #define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 -#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) +#define PINCTRL_DRIVE11_BANK2_PIN27_V BIT(14) #define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) +#define PINCTRL_DRIVE11_BANK2_PIN26_V BIT(10) #define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) +#define PINCTRL_DRIVE11_BANK2_PIN25_V BIT(6) #define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) +#define PINCTRL_DRIVE11_BANK2_PIN24_V BIT(2) #define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 -#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) +#define PINCTRL_DRIVE12_BANK3_PIN07_V BIT(30) #define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) +#define PINCTRL_DRIVE12_BANK3_PIN06_V BIT(26) #define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) +#define PINCTRL_DRIVE12_BANK3_PIN05_V BIT(22) #define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) +#define PINCTRL_DRIVE12_BANK3_PIN04_V BIT(18) #define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) +#define PINCTRL_DRIVE12_BANK3_PIN03_V BIT(14) #define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) +#define PINCTRL_DRIVE12_BANK3_PIN02_V BIT(10) #define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) +#define PINCTRL_DRIVE12_BANK3_PIN01_V BIT(6) #define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) +#define PINCTRL_DRIVE12_BANK3_PIN00_V BIT(2) #define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 -#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) +#define PINCTRL_DRIVE13_BANK3_PIN15_V BIT(30) #define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) +#define PINCTRL_DRIVE13_BANK3_PIN14_V BIT(26) #define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) +#define PINCTRL_DRIVE13_BANK3_PIN13_V BIT(22) #define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) +#define PINCTRL_DRIVE13_BANK3_PIN12_V BIT(18) #define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) +#define PINCTRL_DRIVE13_BANK3_PIN11_V BIT(14) #define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) +#define PINCTRL_DRIVE13_BANK3_PIN10_V BIT(10) #define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) +#define PINCTRL_DRIVE13_BANK3_PIN09_V BIT(6) #define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) +#define PINCTRL_DRIVE13_BANK3_PIN08_V BIT(2) #define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 -#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) +#define PINCTRL_DRIVE14_BANK3_PIN23_V BIT(30) #define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) +#define PINCTRL_DRIVE14_BANK3_PIN22_V BIT(26) #define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) +#define PINCTRL_DRIVE14_BANK3_PIN21_V BIT(22) #define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) +#define PINCTRL_DRIVE14_BANK3_PIN20_V BIT(18) #define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) +#define PINCTRL_DRIVE14_BANK3_PIN18_V BIT(10) #define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) +#define PINCTRL_DRIVE14_BANK3_PIN17_V BIT(6) #define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) +#define PINCTRL_DRIVE14_BANK3_PIN16_V BIT(2) #define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 -#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) +#define PINCTRL_DRIVE15_BANK3_PIN30_V BIT(26) #define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) +#define PINCTRL_DRIVE15_BANK3_PIN29_V BIT(22) #define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) +#define PINCTRL_DRIVE15_BANK3_PIN28_V BIT(18) #define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) +#define PINCTRL_DRIVE15_BANK3_PIN27_V BIT(14) #define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) +#define PINCTRL_DRIVE15_BANK3_PIN26_V BIT(10) #define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) +#define PINCTRL_DRIVE15_BANK3_PIN25_V BIT(6) #define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) +#define PINCTRL_DRIVE15_BANK3_PIN24_V BIT(2) #define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 -#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) +#define PINCTRL_DRIVE16_BANK4_PIN07_V BIT(30) #define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) +#define PINCTRL_DRIVE16_BANK4_PIN06_V BIT(26) #define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) +#define PINCTRL_DRIVE16_BANK4_PIN05_V BIT(22) #define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) +#define PINCTRL_DRIVE16_BANK4_PIN04_V BIT(18) #define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) +#define PINCTRL_DRIVE16_BANK4_PIN03_V BIT(14) #define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) +#define PINCTRL_DRIVE16_BANK4_PIN02_V BIT(10) #define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) +#define PINCTRL_DRIVE16_BANK4_PIN01_V BIT(6) #define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) +#define PINCTRL_DRIVE16_BANK4_PIN00_V BIT(2) #define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 -#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) +#define PINCTRL_DRIVE17_BANK4_PIN15_V BIT(30) #define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) #define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) +#define PINCTRL_DRIVE17_BANK4_PIN14_V BIT(26) #define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) #define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) +#define PINCTRL_DRIVE17_BANK4_PIN13_V BIT(22) #define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) #define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) +#define PINCTRL_DRIVE17_BANK4_PIN12_V BIT(18) #define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) +#define PINCTRL_DRIVE17_BANK4_PIN11_V BIT(14) #define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) #define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) +#define PINCTRL_DRIVE17_BANK4_PIN10_V BIT(10) #define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) #define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) +#define PINCTRL_DRIVE17_BANK4_PIN09_V BIT(6) #define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) #define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) +#define PINCTRL_DRIVE17_BANK4_PIN08_V BIT(2) #define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 -#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) +#define PINCTRL_DRIVE18_BANK4_PIN20_V BIT(18) #define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) #define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) +#define PINCTRL_DRIVE18_BANK4_PIN16_V BIT(2) #define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) #define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 -#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) -#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) -#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) -#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) -#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) -#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) -#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) -#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) -#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) -#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) -#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) -#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) -#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) -#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) -#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) -#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) -#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) -#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) -#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) -#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) -#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) - -#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) -#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) -#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) -#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) -#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) -#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) -#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) -#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) -#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) -#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) -#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) -#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) -#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) -#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) -#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) -#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) -#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) -#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) -#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) -#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) -#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) -#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) -#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) -#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) -#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) -#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) -#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) -#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) -#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) -#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) -#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) -#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) - -#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) -#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) -#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) -#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) -#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) -#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) -#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) -#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) -#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) -#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) -#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) -#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) -#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) -#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) -#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) -#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) -#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) -#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) -#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) -#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) -#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) -#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) -#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) -#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) -#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) - -#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) -#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) -#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) -#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) -#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) -#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) -#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) -#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) -#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) -#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) -#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) -#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) -#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) -#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) -#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) -#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) -#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) -#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) -#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) -#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) -#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) -#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) -#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) -#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) -#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) -#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) -#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) -#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) -#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) -#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) - -#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) -#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) -#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) -#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) -#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) -#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) -#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) -#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) -#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) -#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) -#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) -#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) -#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) -#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) -#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) -#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) -#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) -#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) - -#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) -#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) -#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) -#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) -#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) -#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) -#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) -#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) -#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) -#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) -#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) -#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) -#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) -#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) -#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) -#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) -#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) -#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) -#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) -#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) -#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) -#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) -#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) -#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) -#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) - -#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) -#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) -#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) -#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) -#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) -#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) -#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) -#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) -#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) -#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) -#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) -#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) -#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) -#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) -#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) -#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) -#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) -#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) -#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) -#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) -#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) -#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) -#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) -#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) +#define PINCTRL_PULL0_BANK0_PIN28 BIT(28) +#define PINCTRL_PULL0_BANK0_PIN27 BIT(27) +#define PINCTRL_PULL0_BANK0_PIN26 BIT(26) +#define PINCTRL_PULL0_BANK0_PIN25 BIT(25) +#define PINCTRL_PULL0_BANK0_PIN24 BIT(24) +#define PINCTRL_PULL0_BANK0_PIN23 BIT(23) +#define PINCTRL_PULL0_BANK0_PIN22 BIT(22) +#define PINCTRL_PULL0_BANK0_PIN21 BIT(21) +#define PINCTRL_PULL0_BANK0_PIN20 BIT(20) +#define PINCTRL_PULL0_BANK0_PIN19 BIT(19) +#define PINCTRL_PULL0_BANK0_PIN18 BIT(18) +#define PINCTRL_PULL0_BANK0_PIN17 BIT(17) +#define PINCTRL_PULL0_BANK0_PIN16 BIT(16) +#define PINCTRL_PULL0_BANK0_PIN07 BIT(7) +#define PINCTRL_PULL0_BANK0_PIN06 BIT(6) +#define PINCTRL_PULL0_BANK0_PIN05 BIT(5) +#define PINCTRL_PULL0_BANK0_PIN04 BIT(4) +#define PINCTRL_PULL0_BANK0_PIN03 BIT(3) +#define PINCTRL_PULL0_BANK0_PIN02 BIT(2) +#define PINCTRL_PULL0_BANK0_PIN01 BIT(1) +#define PINCTRL_PULL0_BANK0_PIN00 BIT(0) + +#define PINCTRL_PULL1_BANK1_PIN31 BIT(31) +#define PINCTRL_PULL1_BANK1_PIN30 BIT(30) +#define PINCTRL_PULL1_BANK1_PIN29 BIT(29) +#define PINCTRL_PULL1_BANK1_PIN28 BIT(28) +#define PINCTRL_PULL1_BANK1_PIN27 BIT(27) +#define PINCTRL_PULL1_BANK1_PIN26 BIT(26) +#define PINCTRL_PULL1_BANK1_PIN25 BIT(25) +#define PINCTRL_PULL1_BANK1_PIN24 BIT(24) +#define PINCTRL_PULL1_BANK1_PIN23 BIT(23) +#define PINCTRL_PULL1_BANK1_PIN22 BIT(22) +#define PINCTRL_PULL1_BANK1_PIN21 BIT(21) +#define PINCTRL_PULL1_BANK1_PIN20 BIT(20) +#define PINCTRL_PULL1_BANK1_PIN19 BIT(19) +#define PINCTRL_PULL1_BANK1_PIN18 BIT(18) +#define PINCTRL_PULL1_BANK1_PIN17 BIT(17) +#define PINCTRL_PULL1_BANK1_PIN16 BIT(16) +#define PINCTRL_PULL1_BANK1_PIN15 BIT(15) +#define PINCTRL_PULL1_BANK1_PIN14 BIT(14) +#define PINCTRL_PULL1_BANK1_PIN13 BIT(13) +#define PINCTRL_PULL1_BANK1_PIN12 BIT(12) +#define PINCTRL_PULL1_BANK1_PIN11 BIT(11) +#define PINCTRL_PULL1_BANK1_PIN10 BIT(10) +#define PINCTRL_PULL1_BANK1_PIN09 BIT(9) +#define PINCTRL_PULL1_BANK1_PIN08 BIT(8) +#define PINCTRL_PULL1_BANK1_PIN07 BIT(7) +#define PINCTRL_PULL1_BANK1_PIN06 BIT(6) +#define PINCTRL_PULL1_BANK1_PIN05 BIT(5) +#define PINCTRL_PULL1_BANK1_PIN04 BIT(4) +#define PINCTRL_PULL1_BANK1_PIN03 BIT(3) +#define PINCTRL_PULL1_BANK1_PIN02 BIT(2) +#define PINCTRL_PULL1_BANK1_PIN01 BIT(1) +#define PINCTRL_PULL1_BANK1_PIN00 BIT(0) + +#define PINCTRL_PULL2_BANK2_PIN27 BIT(27) +#define PINCTRL_PULL2_BANK2_PIN26 BIT(26) +#define PINCTRL_PULL2_BANK2_PIN25 BIT(25) +#define PINCTRL_PULL2_BANK2_PIN24 BIT(24) +#define PINCTRL_PULL2_BANK2_PIN21 BIT(21) +#define PINCTRL_PULL2_BANK2_PIN20 BIT(20) +#define PINCTRL_PULL2_BANK2_PIN19 BIT(19) +#define PINCTRL_PULL2_BANK2_PIN18 BIT(18) +#define PINCTRL_PULL2_BANK2_PIN17 BIT(17) +#define PINCTRL_PULL2_BANK2_PIN16 BIT(16) +#define PINCTRL_PULL2_BANK2_PIN15 BIT(15) +#define PINCTRL_PULL2_BANK2_PIN14 BIT(14) +#define PINCTRL_PULL2_BANK2_PIN13 BIT(13) +#define PINCTRL_PULL2_BANK2_PIN12 BIT(12) +#define PINCTRL_PULL2_BANK2_PIN10 BIT(10) +#define PINCTRL_PULL2_BANK2_PIN09 BIT(9) +#define PINCTRL_PULL2_BANK2_PIN08 BIT(8) +#define PINCTRL_PULL2_BANK2_PIN07 BIT(7) +#define PINCTRL_PULL2_BANK2_PIN06 BIT(6) +#define PINCTRL_PULL2_BANK2_PIN05 BIT(5) +#define PINCTRL_PULL2_BANK2_PIN04 BIT(4) +#define PINCTRL_PULL2_BANK2_PIN03 BIT(3) +#define PINCTRL_PULL2_BANK2_PIN02 BIT(2) +#define PINCTRL_PULL2_BANK2_PIN01 BIT(1) +#define PINCTRL_PULL2_BANK2_PIN00 BIT(0) + +#define PINCTRL_PULL3_BANK3_PIN30 BIT(30) +#define PINCTRL_PULL3_BANK3_PIN29 BIT(29) +#define PINCTRL_PULL3_BANK3_PIN28 BIT(28) +#define PINCTRL_PULL3_BANK3_PIN27 BIT(27) +#define PINCTRL_PULL3_BANK3_PIN26 BIT(26) +#define PINCTRL_PULL3_BANK3_PIN25 BIT(25) +#define PINCTRL_PULL3_BANK3_PIN24 BIT(24) +#define PINCTRL_PULL3_BANK3_PIN23 BIT(23) +#define PINCTRL_PULL3_BANK3_PIN22 BIT(22) +#define PINCTRL_PULL3_BANK3_PIN21 BIT(21) +#define PINCTRL_PULL3_BANK3_PIN20 BIT(20) +#define PINCTRL_PULL3_BANK3_PIN18 BIT(18) +#define PINCTRL_PULL3_BANK3_PIN17 BIT(17) +#define PINCTRL_PULL3_BANK3_PIN16 BIT(16) +#define PINCTRL_PULL3_BANK3_PIN15 BIT(15) +#define PINCTRL_PULL3_BANK3_PIN14 BIT(14) +#define PINCTRL_PULL3_BANK3_PIN13 BIT(13) +#define PINCTRL_PULL3_BANK3_PIN12 BIT(12) +#define PINCTRL_PULL3_BANK3_PIN11 BIT(11) +#define PINCTRL_PULL3_BANK3_PIN10 BIT(10) +#define PINCTRL_PULL3_BANK3_PIN09 BIT(9) +#define PINCTRL_PULL3_BANK3_PIN08 BIT(8) +#define PINCTRL_PULL3_BANK3_PIN07 BIT(7) +#define PINCTRL_PULL3_BANK3_PIN06 BIT(6) +#define PINCTRL_PULL3_BANK3_PIN05 BIT(5) +#define PINCTRL_PULL3_BANK3_PIN04 BIT(4) +#define PINCTRL_PULL3_BANK3_PIN03 BIT(3) +#define PINCTRL_PULL3_BANK3_PIN02 BIT(2) +#define PINCTRL_PULL3_BANK3_PIN01 BIT(1) +#define PINCTRL_PULL3_BANK3_PIN00 BIT(0) + +#define PINCTRL_PULL4_BANK4_PIN20 BIT(20) +#define PINCTRL_PULL4_BANK4_PIN16 BIT(16) +#define PINCTRL_PULL4_BANK4_PIN15 BIT(15) +#define PINCTRL_PULL4_BANK4_PIN14 BIT(14) +#define PINCTRL_PULL4_BANK4_PIN13 BIT(13) +#define PINCTRL_PULL4_BANK4_PIN12 BIT(12) +#define PINCTRL_PULL4_BANK4_PIN11 BIT(11) +#define PINCTRL_PULL4_BANK4_PIN10 BIT(10) +#define PINCTRL_PULL4_BANK4_PIN09 BIT(9) +#define PINCTRL_PULL4_BANK4_PIN08 BIT(8) +#define PINCTRL_PULL4_BANK4_PIN07 BIT(7) +#define PINCTRL_PULL4_BANK4_PIN06 BIT(6) +#define PINCTRL_PULL4_BANK4_PIN05 BIT(5) +#define PINCTRL_PULL4_BANK4_PIN04 BIT(4) +#define PINCTRL_PULL4_BANK4_PIN03 BIT(3) +#define PINCTRL_PULL4_BANK4_PIN02 BIT(2) +#define PINCTRL_PULL4_BANK4_PIN01 BIT(1) +#define PINCTRL_PULL4_BANK4_PIN00 BIT(0) + +#define PINCTRL_PULL5_BANK5_PIN26 BIT(26) +#define PINCTRL_PULL5_BANK5_PIN23 BIT(23) +#define PINCTRL_PULL5_BANK5_PIN22 BIT(22) +#define PINCTRL_PULL5_BANK5_PIN21 BIT(21) +#define PINCTRL_PULL5_BANK5_PIN20 BIT(20) +#define PINCTRL_PULL5_BANK5_PIN19 BIT(19) +#define PINCTRL_PULL5_BANK5_PIN18 BIT(18) +#define PINCTRL_PULL5_BANK5_PIN17 BIT(17) +#define PINCTRL_PULL5_BANK5_PIN16 BIT(16) +#define PINCTRL_PULL5_BANK5_PIN15 BIT(15) +#define PINCTRL_PULL5_BANK5_PIN14 BIT(14) +#define PINCTRL_PULL5_BANK5_PIN13 BIT(13) +#define PINCTRL_PULL5_BANK5_PIN12 BIT(12) +#define PINCTRL_PULL5_BANK5_PIN11 BIT(11) +#define PINCTRL_PULL5_BANK5_PIN10 BIT(10) +#define PINCTRL_PULL5_BANK5_PIN09 BIT(9) +#define PINCTRL_PULL5_BANK5_PIN08 BIT(8) +#define PINCTRL_PULL5_BANK5_PIN07 BIT(7) +#define PINCTRL_PULL5_BANK5_PIN06 BIT(6) +#define PINCTRL_PULL5_BANK5_PIN05 BIT(5) +#define PINCTRL_PULL5_BANK5_PIN04 BIT(4) +#define PINCTRL_PULL5_BANK5_PIN03 BIT(3) +#define PINCTRL_PULL5_BANK5_PIN02 BIT(2) +#define PINCTRL_PULL5_BANK5_PIN01 BIT(1) +#define PINCTRL_PULL5_BANK5_PIN00 BIT(0) + +#define PINCTRL_PULL6_BANK6_PIN24 BIT(24) +#define PINCTRL_PULL6_BANK6_PIN23 BIT(23) +#define PINCTRL_PULL6_BANK6_PIN22 BIT(22) +#define PINCTRL_PULL6_BANK6_PIN21 BIT(21) +#define PINCTRL_PULL6_BANK6_PIN20 BIT(20) +#define PINCTRL_PULL6_BANK6_PIN19 BIT(19) +#define PINCTRL_PULL6_BANK6_PIN18 BIT(18) +#define PINCTRL_PULL6_BANK6_PIN17 BIT(17) +#define PINCTRL_PULL6_BANK6_PIN16 BIT(16) +#define PINCTRL_PULL6_BANK6_PIN14 BIT(14) +#define PINCTRL_PULL6_BANK6_PIN13 BIT(13) +#define PINCTRL_PULL6_BANK6_PIN12 BIT(12) +#define PINCTRL_PULL6_BANK6_PIN11 BIT(11) +#define PINCTRL_PULL6_BANK6_PIN10 BIT(10) +#define PINCTRL_PULL6_BANK6_PIN09 BIT(9) +#define PINCTRL_PULL6_BANK6_PIN08 BIT(8) +#define PINCTRL_PULL6_BANK6_PIN07 BIT(7) +#define PINCTRL_PULL6_BANK6_PIN06 BIT(6) +#define PINCTRL_PULL6_BANK6_PIN05 BIT(5) +#define PINCTRL_PULL6_BANK6_PIN04 BIT(4) +#define PINCTRL_PULL6_BANK6_PIN03 BIT(3) +#define PINCTRL_PULL6_BANK6_PIN02 BIT(2) +#define PINCTRL_PULL6_BANK6_PIN01 BIT(1) +#define PINCTRL_PULL6_BANK6_PIN00 BIT(0) #define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff #define PINCTRL_DOUT0_DOUT_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h index ce2f425..993af7e 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h @@ -49,33 +49,33 @@ struct mxs_power_regs { }; #endif -#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) +#define POWER_CTRL_CLKGATE BIT(30) +#define POWER_CTRL_PSWITCH_MID_TRAN BIT(27) +#define POWER_CTRL_DCDC4P2_BO_IRQ BIT(24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO BIT(23) +#define POWER_CTRL_VDD5V_DROOP_IRQ BIT(22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP BIT(21) +#define POWER_CTRL_PSWITCH_IRQ BIT(20) +#define POWER_CTRL_PSWITCH_IRQ_SRC BIT(19) +#define POWER_CTRL_POLARITY_PSWITCH BIT(18) +#define POWER_CTRL_ENIRQ_PSWITCH BIT(17) +#define POWER_CTRL_POLARITY_DC_OK BIT(16) +#define POWER_CTRL_DC_OK_IRQ BIT(15) +#define POWER_CTRL_ENIRQ_DC_OK BIT(14) +#define POWER_CTRL_BATT_BO_IRQ BIT(13) +#define POWER_CTRL_ENIRQ_BATT_BO BIT(12) +#define POWER_CTRL_VDDIO_BO_IRQ BIT(11) +#define POWER_CTRL_ENIRQ_VDDIO_BO BIT(10) +#define POWER_CTRL_VDDA_BO_IRQ BIT(9) +#define POWER_CTRL_ENIRQ_VDDA_BO BIT(8) +#define POWER_CTRL_VDDD_BO_IRQ BIT(7) +#define POWER_CTRL_ENIRQ_VDDD_BO BIT(6) +#define POWER_CTRL_POLARITY_VBUSVALID BIT(5) +#define POWER_CTRL_VBUS_VALID_IRQ BIT(4) +#define POWER_CTRL_ENIRQ_VBUS_VALID BIT(3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO BIT(2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ BIT(1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO BIT(0) #define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) #define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 @@ -99,30 +99,30 @@ struct mxs_power_regs { #define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) #define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) #define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) +#define POWER_5VCTRL_PWDN_5VBRNOUT BIT(7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT BIT(6) +#define POWER_5VCTRL_DCDC_XFER BIT(5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT BIT(4) +#define POWER_5VCTRL_VBUSVALID_TO_B BIT(3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO BIT(2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS BIT(1) +#define POWER_5VCTRL_ENABLE_DCDC BIT(0) -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) +#define POWER_MINPWR_LOWPWR_4P2 BIT(14) +#define POWER_MINPWR_VDAC_DUMP_CTRL BIT(13) +#define POWER_MINPWR_PWD_BO BIT(12) +#define POWER_MINPWR_USE_VDDXTAL_VBG BIT(11) +#define POWER_MINPWR_PWD_ANA_CMPS BIT(10) +#define POWER_MINPWR_ENABLE_OSC BIT(9) +#define POWER_MINPWR_SELECT_OSC BIT(8) +#define POWER_MINPWR_VBG_OFF BIT(7) +#define POWER_MINPWR_DOUBLE_FETS BIT(6) +#define POWER_MINPWR_HALFFETS BIT(5) +#define POWER_MINPWR_LESSANA_I BIT(4) +#define POWER_MINPWR_PWD_XTAL24 BIT(3) +#define POWER_MINPWR_DC_STOPCLK BIT(2) +#define POWER_MINPWR_EN_DC_PFM BIT(1) +#define POWER_MINPWR_DC_HALFCLK BIT(0) #define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) #define POWER_CHARGE_ADJ_VOLT_OFFSET 24 @@ -133,12 +133,12 @@ struct mxs_power_regs { #define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) #define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) #define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_ENABLE_LOAD BIT(22) +#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS BIT(21) +#define POWER_CHARGE_ENABLE_FAULT_DETECT BIT(20) +#define POWER_CHARGE_CHRG_STS_OFF BIT(19) +#define POWER_CHARGE_USE_EXTERN_R BIT(17) +#define POWER_CHARGE_PWD_BATTCHRG BIT(16) #define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) #define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 #define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) @@ -156,10 +156,10 @@ struct mxs_power_regs { #define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) #define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_PWDN_BRNOUT BIT(23) +#define POWER_VDDDCTRL_DISABLE_STEPPING BIT(22) +#define POWER_VDDDCTRL_ENABLE_LINREG BIT(21) +#define POWER_VDDDCTRL_DISABLE_FET BIT(20) #define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) #define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 #define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) @@ -171,10 +171,10 @@ struct mxs_power_regs { #define POWER_VDDDCTRL_TRG_MASK 0x1f #define POWER_VDDDCTRL_TRG_OFFSET 0 -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_PWDN_BRNOUT BIT(19) +#define POWER_VDDACTRL_DISABLE_STEPPING BIT(18) +#define POWER_VDDACTRL_ENABLE_LINREG BIT(17) +#define POWER_VDDACTRL_DISABLE_FET BIT(16) #define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) #define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 #define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) @@ -188,9 +188,9 @@ struct mxs_power_regs { #define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) #define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_PWDN_BRNOUT BIT(18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING BIT(17) +#define POWER_VDDIOCTRL_DISABLE_FET BIT(16) #define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) #define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 #define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) @@ -202,9 +202,9 @@ struct mxs_power_regs { #define POWER_VDDIOCTRL_TRG_MASK 0x1f #define POWER_VDDIOCTRL_TRG_OFFSET 0 -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE BIT(10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT BIT(9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG BIT(8) #define POWER_VDDMEMCTRL_TRG_MASK 0x1f #define POWER_VDDMEMCTRL_TRG_OFFSET 0 @@ -219,10 +219,10 @@ struct mxs_power_regs { #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) #define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) #define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_ENABLE_4P2 BIT(23) +#define POWER_DCDC4P2_ENABLE_DCDC BIT(22) +#define POWER_DCDC4P2_HYST_DIR BIT(21) +#define POWER_DCDC4P2_HYST_THRESH BIT(20) #define POWER_DCDC4P2_TRG_MASK (0x7 << 16) #define POWER_DCDC4P2_TRG_OFFSET 16 #define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) @@ -244,23 +244,23 @@ struct mxs_power_regs { #define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) #define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) #define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) +#define POWER_MISC_DISABLE_FET_BO_LOGIC BIT(3) +#define POWER_MISC_DELAY_TIMING BIT(2) +#define POWER_MISC_TEST BIT(1) +#define POWER_MISC_SEL_PLLCLK BIT(0) #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f #define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_TOGGLE_DIF BIT(20) +#define POWER_LOOPCTRL_HYST_SIGN BIT(19) +#define POWER_LOOPCTRL_EN_CM_HYST BIT(18) +#define POWER_LOOPCTRL_EN_DF_HYST BIT(17) +#define POWER_LOOPCTRL_CM_HYST_THRESH BIT(16) +#define POWER_LOOPCTRL_DF_HYST_THRESH BIT(15) +#define POWER_LOOPCTRL_RCSCALE_THRESH BIT(14) #define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) #define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 #define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) @@ -286,24 +286,24 @@ struct mxs_power_regs { #define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) #define POWER_STS_PSWITCH_MASK (0x3 << 20) #define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) +#define POWER_STS_AVALID0_STATUS BIT(17) +#define POWER_STS_BVALID0_STATUS BIT(16) +#define POWER_STS_VBUSVALID0_STATUS BIT(15) +#define POWER_STS_SESSEND0_STATUS BIT(14) +#define POWER_STS_BATT_BO BIT(13) +#define POWER_STS_VDD5V_FAULT BIT(12) +#define POWER_STS_CHRGSTS BIT(11) +#define POWER_STS_DCDC_4P2_BO BIT(10) +#define POWER_STS_DC_OK BIT(9) +#define POWER_STS_VDDIO_BO BIT(8) +#define POWER_STS_VDDA_BO BIT(7) +#define POWER_STS_VDDD_BO BIT(6) +#define POWER_STS_VDD5V_GT_VDDIO BIT(5) +#define POWER_STS_VDD5V_DROOP BIT(4) +#define POWER_STS_AVALID0 BIT(3) +#define POWER_STS_BVALID0 BIT(2) +#define POWER_STS_VBUSVALID0 BIT(1) +#define POWER_STS_SESSEND0 BIT(0) #define POWER_SPEED_STATUS_MASK (0xff << 16) #define POWER_SPEED_STATUS_OFFSET 16 @@ -315,22 +315,22 @@ struct mxs_power_regs { #define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) #define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_EN_BATADJ BIT(10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT BIT(9) +#define POWER_BATTMONITOR_BRWNOUT_PWD BIT(8) #define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f #define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 #define POWER_RESET_UNLOCK_MASK (0xffff << 16) #define POWER_RESET_UNLOCK_OFFSET 16 #define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) +#define POWER_RESET_PWD_OFF BIT(1) +#define POWER_RESET_PWD BIT(0) -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) +#define POWER_DEBUG_VBUSVALIDPIOLOCK BIT(3) +#define POWER_DEBUG_AVALIDPIOLOCK BIT(2) +#define POWER_DEBUG_BVALIDPIOLOCK BIT(1) +#define POWER_DEBUG_SESSENDPIOLOCK BIT(0) #define POWER_SPECIAL_TEST_MASK 0xffffffff #define POWER_SPECIAL_TEST_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h index 9528e3c..cf44dfb 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h +++ b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h @@ -51,32 +51,32 @@ struct mxs_power_regs { }; #endif -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) +#define POWER_CTRL_PSWITCH_MID_TRAN BIT(27) +#define POWER_CTRL_DCDC4P2_BO_IRQ BIT(24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO BIT(23) +#define POWER_CTRL_VDD5V_DROOP_IRQ BIT(22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP BIT(21) +#define POWER_CTRL_PSWITCH_IRQ BIT(20) +#define POWER_CTRL_PSWITCH_IRQ_SRC BIT(19) +#define POWER_CTRL_POLARITY_PSWITCH BIT(18) +#define POWER_CTRL_ENIRQ_PSWITCH BIT(17) +#define POWER_CTRL_POLARITY_DC_OK BIT(16) +#define POWER_CTRL_DC_OK_IRQ BIT(15) +#define POWER_CTRL_ENIRQ_DC_OK BIT(14) +#define POWER_CTRL_BATT_BO_IRQ BIT(13) +#define POWER_CTRL_ENIRQ_BATT_BO BIT(12) +#define POWER_CTRL_VDDIO_BO_IRQ BIT(11) +#define POWER_CTRL_ENIRQ_VDDIO_BO BIT(10) +#define POWER_CTRL_VDDA_BO_IRQ BIT(9) +#define POWER_CTRL_ENIRQ_VDDA_BO BIT(8) +#define POWER_CTRL_VDDD_BO_IRQ BIT(7) +#define POWER_CTRL_ENIRQ_VDDD_BO BIT(6) +#define POWER_CTRL_POLARITY_VBUSVALID BIT(5) +#define POWER_CTRL_VBUS_VALID_IRQ BIT(4) +#define POWER_CTRL_ENIRQ_VBUS_VALID BIT(3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO BIT(2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ BIT(1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO BIT(0) #define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) #define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 @@ -100,29 +100,29 @@ struct mxs_power_regs { #define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) #define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) #define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) +#define POWER_5VCTRL_PWDN_5VBRNOUT BIT(7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT BIT(6) +#define POWER_5VCTRL_DCDC_XFER BIT(5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT BIT(4) +#define POWER_5VCTRL_VBUSVALID_TO_B BIT(3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO BIT(2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS BIT(1) +#define POWER_5VCTRL_ENABLE_DCDC BIT(0) -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) +#define POWER_MINPWR_LOWPWR_4P2 BIT(14) +#define POWER_MINPWR_PWD_BO BIT(12) +#define POWER_MINPWR_USE_VDDXTAL_VBG BIT(11) +#define POWER_MINPWR_PWD_ANA_CMPS BIT(10) +#define POWER_MINPWR_ENABLE_OSC BIT(9) +#define POWER_MINPWR_SELECT_OSC BIT(8) +#define POWER_MINPWR_VBG_OFF BIT(7) +#define POWER_MINPWR_DOUBLE_FETS BIT(6) +#define POWER_MINPWR_HALFFETS BIT(5) +#define POWER_MINPWR_LESSANA_I BIT(4) +#define POWER_MINPWR_PWD_XTAL24 BIT(3) +#define POWER_MINPWR_DC_STOPCLK BIT(2) +#define POWER_MINPWR_EN_DC_PFM BIT(1) +#define POWER_MINPWR_DC_HALFCLK BIT(0) #define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) #define POWER_CHARGE_ADJ_VOLT_OFFSET 24 @@ -133,13 +133,13 @@ struct mxs_power_regs { #define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) #define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) #define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_LIION_4P1 (1 << 18) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) -#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_ENABLE_LOAD BIT(22) +#define POWER_CHARGE_ENABLE_FAULT_DETECT BIT(20) +#define POWER_CHARGE_CHRG_STS_OFF BIT(19) +#define POWER_CHARGE_LIION_4P1 BIT(18) +#define POWER_CHARGE_PWD_BATTCHRG BIT(16) +#define POWER_CHARGE_ENABLE_CHARGER_USB1 BIT(13) +#define POWER_CHARGE_ENABLE_CHARGER_USB0 BIT(12) #define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) #define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 #define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) @@ -157,10 +157,10 @@ struct mxs_power_regs { #define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) #define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_PWDN_BRNOUT BIT(23) +#define POWER_VDDDCTRL_DISABLE_STEPPING BIT(22) +#define POWER_VDDDCTRL_ENABLE_LINREG BIT(21) +#define POWER_VDDDCTRL_DISABLE_FET BIT(20) #define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) #define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 #define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) @@ -172,10 +172,10 @@ struct mxs_power_regs { #define POWER_VDDDCTRL_TRG_MASK 0x1f #define POWER_VDDDCTRL_TRG_OFFSET 0 -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_PWDN_BRNOUT BIT(19) +#define POWER_VDDACTRL_DISABLE_STEPPING BIT(18) +#define POWER_VDDACTRL_ENABLE_LINREG BIT(17) +#define POWER_VDDACTRL_DISABLE_FET BIT(16) #define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) #define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 #define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) @@ -189,9 +189,9 @@ struct mxs_power_regs { #define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) #define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_PWDN_BRNOUT BIT(18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING BIT(17) +#define POWER_VDDIOCTRL_DISABLE_FET BIT(16) #define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) #define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 #define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) @@ -203,9 +203,9 @@ struct mxs_power_regs { #define POWER_VDDIOCTRL_TRG_MASK 0x1f #define POWER_VDDIOCTRL_TRG_OFFSET 0 -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE BIT(10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT BIT(9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG BIT(8) #define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) #define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 #define POWER_VDDMEMCTRL_TRG_MASK 0x1f @@ -222,10 +222,10 @@ struct mxs_power_regs { #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) #define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) #define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_ENABLE_4P2 BIT(23) +#define POWER_DCDC4P2_ENABLE_DCDC BIT(22) +#define POWER_DCDC4P2_HYST_DIR BIT(21) +#define POWER_DCDC4P2_HYST_THRESH BIT(20) #define POWER_DCDC4P2_TRG_MASK (0x7 << 16) #define POWER_DCDC4P2_TRG_OFFSET 16 #define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) @@ -247,23 +247,23 @@ struct mxs_power_regs { #define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) #define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) #define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) +#define POWER_MISC_DISABLE_FET_BO_LOGIC BIT(3) +#define POWER_MISC_DELAY_TIMING BIT(2) +#define POWER_MISC_TEST BIT(1) +#define POWER_MISC_SEL_PLLCLK BIT(0) #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f #define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_TOGGLE_DIF BIT(20) +#define POWER_LOOPCTRL_HYST_SIGN BIT(19) +#define POWER_LOOPCTRL_EN_CM_HYST BIT(18) +#define POWER_LOOPCTRL_EN_DF_HYST BIT(17) +#define POWER_LOOPCTRL_CM_HYST_THRESH BIT(16) +#define POWER_LOOPCTRL_DF_HYST_THRESH BIT(15) +#define POWER_LOOPCTRL_RCSCALE_THRESH BIT(14) #define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) #define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 #define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) @@ -289,26 +289,26 @@ struct mxs_power_regs { #define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) #define POWER_STS_PSWITCH_MASK (0x3 << 20) #define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_THERMAL_WARNING (1 << 19) -#define POWER_STS_VDDMEM_BO (1 << 18) -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) +#define POWER_STS_THERMAL_WARNING BIT(19) +#define POWER_STS_VDDMEM_BO BIT(18) +#define POWER_STS_AVALID0_STATUS BIT(17) +#define POWER_STS_BVALID0_STATUS BIT(16) +#define POWER_STS_VBUSVALID0_STATUS BIT(15) +#define POWER_STS_SESSEND0_STATUS BIT(14) +#define POWER_STS_BATT_BO BIT(13) +#define POWER_STS_VDD5V_FAULT BIT(12) +#define POWER_STS_CHRGSTS BIT(11) +#define POWER_STS_DCDC_4P2_BO BIT(10) +#define POWER_STS_DC_OK BIT(9) +#define POWER_STS_VDDIO_BO BIT(8) +#define POWER_STS_VDDA_BO BIT(7) +#define POWER_STS_VDDD_BO BIT(6) +#define POWER_STS_VDD5V_GT_VDDIO BIT(5) +#define POWER_STS_VDD5V_DROOP BIT(4) +#define POWER_STS_AVALID0 BIT(3) +#define POWER_STS_BVALID0 BIT(2) +#define POWER_STS_VBUSVALID0 BIT(1) +#define POWER_STS_SESSEND0 BIT(0) #define POWER_SPEED_STATUS_MASK (0xffff << 8) #define POWER_SPEED_STATUS_OFFSET 8 @@ -325,38 +325,38 @@ struct mxs_power_regs { #define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) #define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN BIT(11) +#define POWER_BATTMONITOR_EN_BATADJ BIT(10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT BIT(9) +#define POWER_BATTMONITOR_BRWNOUT_PWD BIT(8) #define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f #define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 #define POWER_RESET_UNLOCK_MASK (0xffff << 16) #define POWER_RESET_UNLOCK_OFFSET 16 #define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) +#define POWER_RESET_FASTFALL_PSWITCH_OFF BIT(2) +#define POWER_RESET_PWD_OFF BIT(1) +#define POWER_RESET_PWD BIT(0) -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) +#define POWER_DEBUG_VBUSVALIDPIOLOCK BIT(3) +#define POWER_DEBUG_AVALIDPIOLOCK BIT(2) +#define POWER_DEBUG_BVALIDPIOLOCK BIT(1) +#define POWER_DEBUG_SESSENDPIOLOCK BIT(0) -#define POWER_THERMAL_TEST (1 << 8) -#define POWER_THERMAL_PWD (1 << 7) -#define POWER_THERMAL_LOW_POWER (1 << 6) +#define POWER_THERMAL_TEST BIT(8) +#define POWER_THERMAL_PWD BIT(7) +#define POWER_THERMAL_LOW_POWER BIT(6) #define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) #define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 -#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define POWER_THERMAL_OFFSET_ADJ_ENABLE BIT(3) #define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 #define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 -#define POWER_USB1CTRL_AVALID1 (1 << 3) -#define POWER_USB1CTRL_BVALID1 (1 << 2) -#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) -#define POWER_USB1CTRL_SESSEND1 (1 << 0) +#define POWER_USB1CTRL_AVALID1 BIT(3) +#define POWER_USB1CTRL_BVALID1 BIT(2) +#define POWER_USB1CTRL_VBUSVALID1 BIT(1) +#define POWER_USB1CTRL_SESSEND1 BIT(0) #define POWER_SPECIAL_TEST_MASK 0xffffffff #define POWER_SPECIAL_TEST_OFFSET 0 @@ -368,30 +368,30 @@ struct mxs_power_regs { #define POWER_VERSION_STEP_MASK 0xffff #define POWER_VERSION_STEP_OFFSET 0 -#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define POWER_ANACLKCTRL_CLKGATE_0 BIT(31) #define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) #define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 -#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) -#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) -#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) -#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) -#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define POWER_ANACLKCTRL_INVERT_OUTCLK BIT(27) +#define POWER_ANACLKCTRL_CLKGATE_I BIT(26) +#define POWER_ANACLKCTRL_DITHER_OFF BIT(10) +#define POWER_ANACLKCTRL_SLOW_DITHER BIT(9) +#define POWER_ANACLKCTRL_INVERT_INCLK BIT(8) #define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) #define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 #define POWER_ANACLKCTRL_INDIV_MASK 0x7 #define POWER_ANACLKCTRL_INDIV_OFFSET 0 -#define POWER_REFCTRL_FASTSETTLING (1 << 26) -#define POWER_REFCTRL_RAISE_REF (1 << 25) -#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define POWER_REFCTRL_FASTSETTLING BIT(26) +#define POWER_REFCTRL_RAISE_REF BIT(25) +#define POWER_REFCTRL_XTAL_BGR_BIAS BIT(24) #define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) #define POWER_REFCTRL_VBG_ADJ_OFFSET 20 -#define POWER_REFCTRL_LOW_PWR (1 << 19) +#define POWER_REFCTRL_LOW_PWR BIT(19) #define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) #define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 -#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) -#define POWER_REFCTRL_ADJ_ANA (1 << 13) -#define POWER_REFCTRL_ADJ_VAG (1 << 12) +#define POWER_REFCTRL_VDDXTAL_TO_VDDD BIT(14) +#define POWER_REFCTRL_ADJ_ANA BIT(13) +#define POWER_REFCTRL_ADJ_VAG BIT(12) #define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) #define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 #define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h index 03e2e5d..253bdd7 100644 --- a/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h @@ -31,21 +31,21 @@ struct mxs_rtc_regs { }; #endif -#define RTC_CTRL_SFTRST (1 << 31) -#define RTC_CTRL_CLKGATE (1 << 30) -#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) -#define RTC_CTRL_FORCE_UPDATE (1 << 5) -#define RTC_CTRL_WATCHDOGEN (1 << 4) -#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) -#define RTC_CTRL_ALARM_IRQ (1 << 2) -#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) -#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) - -#define RTC_STAT_RTC_PRESENT (1 << 31) -#define RTC_STAT_ALARM_PRESENT (1 << 30) -#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) -#define RTC_STAT_XTAL32000_PRESENT (1 << 28) -#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_CTRL_SFTRST BIT(31) +#define RTC_CTRL_CLKGATE BIT(30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG BIT(6) +#define RTC_CTRL_FORCE_UPDATE BIT(5) +#define RTC_CTRL_WATCHDOGEN BIT(4) +#define RTC_CTRL_ONEMSEC_IRQ BIT(3) +#define RTC_CTRL_ALARM_IRQ BIT(2) +#define RTC_CTRL_ONEMSEC_IRQ_EN BIT(1) +#define RTC_CTRL_ALARM_IRQ_EN BIT(0) + +#define RTC_STAT_RTC_PRESENT BIT(31) +#define RTC_STAT_ALARM_PRESENT BIT(30) +#define RTC_STAT_WATCHDOG_PRESENT BIT(29) +#define RTC_STAT_XTAL32000_PRESENT BIT(28) +#define RTC_STAT_XTAL32768_PRESENT BIT(27) #define RTC_STAT_STALE_REGS_MASK (0xff << 16) #define RTC_STAT_STALE_REGS_OFFSET 16 #define RTC_STAT_NEW_REGS_MASK (0xff << 8) @@ -73,17 +73,17 @@ struct mxs_rtc_regs { #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) #define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) -#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) -#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) -#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) -#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) -#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_EXTERNAL_RESET BIT(21) +#define RTC_PERSISTENT0_THERMAL_RESET BIT(20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP BIT(18) +#define RTC_PERSISTENT0_AUTO_RESTART BIT(17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH BIT(16) #define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) #define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 #define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) #define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) #define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) -#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_DISABLE_XTALOK BIT(13) #define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) #define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 #define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) @@ -91,14 +91,14 @@ struct mxs_rtc_regs { #define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) #define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) #define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) -#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) -#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) -#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) -#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) -#define RTC_PERSISTENT0_LCK_SECS (1 << 3) -#define RTC_PERSISTENT0_ALARM_EN (1 << 2) -#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) -#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) +#define RTC_PERSISTENT0_ALARM_WAKE BIT(7) +#define RTC_PERSISTENT0_XTAL32_FREQ BIT(6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP BIT(5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP BIT(4) +#define RTC_PERSISTENT0_LCK_SECS BIT(3) +#define RTC_PERSISTENT0_ALARM_EN BIT(2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN BIT(1) +#define RTC_PERSISTENT0_CLOCKSOURCE BIT(0) #define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff #define RTC_PERSISTENT1_GENERAL_OFFSET 0 @@ -121,8 +121,8 @@ struct mxs_rtc_regs { #define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff #define RTC_PERSISTENT5_GENERAL_OFFSET 0 -#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) -#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) +#define RTC_DEBUG_WATCHDOG_RESET_MASK BIT(1) +#define RTC_DEBUG_WATCHDOG_RESET BIT(0) #define RTC_VERSION_MAJOR_MASK (0xff << 24) #define RTC_VERSION_MAJOR_OFFSET 24 diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index e991216..6f304d1 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -106,38 +106,38 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) } #endif -#define SSP_CTRL0_SFTRST (1 << 31) -#define SSP_CTRL0_CLKGATE (1 << 30) -#define SSP_CTRL0_RUN (1 << 29) -#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) -#define SSP_CTRL0_LOCK_CS (1 << 27) -#define SSP_CTRL0_IGNORE_CRC (1 << 26) -#define SSP_CTRL0_READ (1 << 25) -#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_SFTRST BIT(31) +#define SSP_CTRL0_CLKGATE BIT(30) +#define SSP_CTRL0_RUN BIT(29) +#define SSP_CTRL0_SDIO_IRQ_CHECK BIT(28) +#define SSP_CTRL0_LOCK_CS BIT(27) +#define SSP_CTRL0_IGNORE_CRC BIT(26) +#define SSP_CTRL0_READ BIT(25) +#define SSP_CTRL0_DATA_XFER BIT(24) #define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) #define SSP_CTRL0_BUS_WIDTH_OFFSET 22 #define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) #define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) #define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) -#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) -#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) -#define SSP_CTRL0_LONG_RESP (1 << 19) -#define SSP_CTRL0_CHECK_RESP (1 << 18) -#define SSP_CTRL0_GET_RESP (1 << 17) -#define SSP_CTRL0_ENABLE (1 << 16) +#define SSP_CTRL0_WAIT_FOR_IRQ BIT(21) +#define SSP_CTRL0_WAIT_FOR_CMD BIT(20) +#define SSP_CTRL0_LONG_RESP BIT(19) +#define SSP_CTRL0_CHECK_RESP BIT(18) +#define SSP_CTRL0_GET_RESP BIT(17) +#define SSP_CTRL0_ENABLE BIT(16) #ifdef CONFIG_MX23 #define SSP_CTRL0_XFER_COUNT_OFFSET 0 #define SSP_CTRL0_XFER_COUNT_MASK 0xffff #endif -#define SSP_CMD0_SOFT_TERMINATE (1 << 26) -#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) -#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) -#define SSP_CMD0_BOOT_ACK_EN (1 << 23) -#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) -#define SSP_CMD0_CONT_CLKING_EN (1 << 21) -#define SSP_CMD0_APPEND_8CYC (1 << 20) +#define SSP_CMD0_SOFT_TERMINATE BIT(26) +#define SSP_CMD0_DBL_DATA_RATE_EN BIT(25) +#define SSP_CMD0_PRIM_BOOT_OP_EN BIT(24) +#define SSP_CMD0_BOOT_ACK_EN BIT(23) +#define SSP_CMD0_SLOW_CLKING_EN BIT(22) +#define SSP_CMD0_CONT_CLKING_EN BIT(21) +#define SSP_CMD0_APPEND_8CYC BIT(20) #if defined(CONFIG_MX23) #define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) #define SSP_CMD0_BLOCK_SIZE_OFFSET 16 @@ -240,30 +240,30 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_TIMING_CLOCK_RATE_MASK 0xff #define SSP_TIMING_CLOCK_RATE_OFFSET 0 -#define SSP_CTRL1_SDIO_IRQ (1 << 31) -#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) -#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) -#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) -#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) -#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) -#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) -#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) -#define SSP_CTRL1_DMA_ENABLE (1 << 13) -#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) -#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) -#define SSP_CTRL1_PHASE (1 << 10) -#define SSP_CTRL1_POLARITY (1 << 9) -#define SSP_CTRL1_SLAVE_MODE (1 << 8) +#define SSP_CTRL1_SDIO_IRQ BIT(31) +#define SSP_CTRL1_SDIO_IRQ_EN BIT(30) +#define SSP_CTRL1_RESP_ERR_IRQ BIT(29) +#define SSP_CTRL1_RESP_ERR_IRQ_EN BIT(28) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ BIT(27) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN BIT(26) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ BIT(25) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN BIT(24) +#define SSP_CTRL1_DATA_CRC_IRQ BIT(23) +#define SSP_CTRL1_DATA_CRC_IRQ_EN BIT(22) +#define SSP_CTRL1_FIFO_UNDERRUN_IRQ BIT(21) +#define SSP_CTRL1_FIFO_UNDERRUN_EN BIT(20) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ BIT(19) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN BIT(18) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ BIT(17) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN BIT(16) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ BIT(15) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN BIT(14) +#define SSP_CTRL1_DMA_ENABLE BIT(13) +#define SSP_CTRL1_CEATA_CCS_ERR_EN BIT(12) +#define SSP_CTRL1_SLAVE_OUT_DISABLE BIT(11) +#define SSP_CTRL1_PHASE BIT(10) +#define SSP_CTRL1_POLARITY BIT(9) +#define SSP_CTRL1_SLAVE_MODE BIT(8) #define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) #define SSP_CTRL1_WORD_LENGTH_OFFSET 4 #define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) @@ -296,8 +296,8 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) #define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 -#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) -#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) +#define SSP_DDR_CTRL_NIBBLE_POS BIT(1) +#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE BIT(0) #define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) #define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 @@ -305,49 +305,49 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 -#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) -#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) +#define SSP_DLL_CTRL_SLV_OVERRIDE BIT(9) +#define SSP_DLL_CTRL_GATE_UPDATE BIT(7) #define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) #define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 -#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) -#define SSP_DLL_CTRL_RESET (1 << 1) -#define SSP_DLL_CTRL_ENABLE (1 << 0) - -#define SSP_STATUS_PRESENT (1 << 31) -#define SSP_STATUS_MS_PRESENT (1 << 30) -#define SSP_STATUS_SD_PRESENT (1 << 29) -#define SSP_STATUS_CARD_DETECT (1 << 28) -#define SSP_STATUS_DMABURST (1 << 22) -#define SSP_STATUS_DMASENSE (1 << 21) -#define SSP_STATUS_DMATERM (1 << 20) -#define SSP_STATUS_DMAREQ (1 << 19) -#define SSP_STATUS_DMAEND (1 << 18) -#define SSP_STATUS_SDIO_IRQ (1 << 17) -#define SSP_STATUS_RESP_CRC_ERR (1 << 16) -#define SSP_STATUS_RESP_ERR (1 << 15) -#define SSP_STATUS_RESP_TIMEOUT (1 << 14) -#define SSP_STATUS_DATA_CRC_ERR (1 << 13) -#define SSP_STATUS_TIMEOUT (1 << 12) -#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) -#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) -#define SSP_STATUS_FIFO_OVRFLW (1 << 9) -#define SSP_STATUS_FIFO_FULL (1 << 8) -#define SSP_STATUS_FIFO_EMPTY (1 << 5) -#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) -#define SSP_STATUS_CMD_BUSY (1 << 3) -#define SSP_STATUS_DATA_BUSY (1 << 2) -#define SSP_STATUS_BUSY (1 << 0) +#define SSP_DLL_CTRL_SLV_FORCE_UPD BIT(2) +#define SSP_DLL_CTRL_RESET BIT(1) +#define SSP_DLL_CTRL_ENABLE BIT(0) + +#define SSP_STATUS_PRESENT BIT(31) +#define SSP_STATUS_MS_PRESENT BIT(30) +#define SSP_STATUS_SD_PRESENT BIT(29) +#define SSP_STATUS_CARD_DETECT BIT(28) +#define SSP_STATUS_DMABURST BIT(22) +#define SSP_STATUS_DMASENSE BIT(21) +#define SSP_STATUS_DMATERM BIT(20) +#define SSP_STATUS_DMAREQ BIT(19) +#define SSP_STATUS_DMAEND BIT(18) +#define SSP_STATUS_SDIO_IRQ BIT(17) +#define SSP_STATUS_RESP_CRC_ERR BIT(16) +#define SSP_STATUS_RESP_ERR BIT(15) +#define SSP_STATUS_RESP_TIMEOUT BIT(14) +#define SSP_STATUS_DATA_CRC_ERR BIT(13) +#define SSP_STATUS_TIMEOUT BIT(12) +#define SSP_STATUS_RECV_TIMEOUT_STAT BIT(11) +#define SSP_STATUS_CEATA_CCS_ERR BIT(10) +#define SSP_STATUS_FIFO_OVRFLW BIT(9) +#define SSP_STATUS_FIFO_FULL BIT(8) +#define SSP_STATUS_FIFO_EMPTY BIT(5) +#define SSP_STATUS_FIFO_UNDRFLW BIT(4) +#define SSP_STATUS_CMD_BUSY BIT(3) +#define SSP_STATUS_DATA_BUSY BIT(2) +#define SSP_STATUS_BUSY BIT(0) #define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) #define SSP_DLL_STS_REF_SEL_OFFSET 8 #define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) #define SSP_DLL_STS_SLV_SEL_OFFSET 2 -#define SSP_DLL_STS_REF_LOCK (1 << 1) -#define SSP_DLL_STS_SLV_LOCK (1 << 0) +#define SSP_DLL_STS_REF_LOCK BIT(1) +#define SSP_DLL_STS_SLV_LOCK BIT(0) #define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) #define SSP_DEBUG_DATACRC_ERR_OFFSET 28 -#define SSP_DEBUG_DATA_STALL (1 << 27) +#define SSP_DEBUG_DATA_STALL BIT(27) #define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) #define SSP_DEBUG_DAT_SM_OFFSET 24 #define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) @@ -372,7 +372,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) #define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) #define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) -#define SSP_DEBUG_CMD_OE (1 << 19) +#define SSP_DEBUG_CMD_OE BIT(19) #define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) #define SSP_DEBUG_DMA_SM_OFFSET 16 #define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) @@ -401,8 +401,8 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) #define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) #define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) #define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) -#define SSP_DEBUG_SSP_CMD (1 << 9) -#define SSP_DEBUG_SSP_RESP (1 << 8) +#define SSP_DEBUG_SSP_CMD BIT(9) +#define SSP_DEBUG_SSP_RESP BIT(8) #define SSP_DEBUG_SSP_RXD_MASK 0xff #define SSP_DEBUG_SSP_RXD_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 713c630..ff9463b 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -49,26 +49,26 @@ struct mxs_timrot_regs { }; #endif -#define TIMROT_ROTCTRL_SFTRST (1 << 31) -#define TIMROT_ROTCTRL_CLKGATE (1 << 30) -#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) -#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) -#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) -#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) -#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) +#define TIMROT_ROTCTRL_SFTRST BIT(31) +#define TIMROT_ROTCTRL_CLKGATE BIT(30) +#define TIMROT_ROTCTRL_ROTARY_PRESENT BIT(29) +#define TIMROT_ROTCTRL_TIM3_PRESENT BIT(28) +#define TIMROT_ROTCTRL_TIM2_PRESENT BIT(27) +#define TIMROT_ROTCTRL_TIM1_PRESENT BIT(26) +#define TIMROT_ROTCTRL_TIM0_PRESENT BIT(25) #define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) #define TIMROT_ROTCTRL_STATE_OFFSET 22 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 -#define TIMROT_ROTCTRL_RELATIVE (1 << 12) +#define TIMROT_ROTCTRL_RELATIVE BIT(12) #define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) #define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 #define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) #define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) #define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) -#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) -#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#define TIMROT_ROTCTRL_POLARITY_B BIT(9) +#define TIMROT_ROTCTRL_POLARITY_A BIT(8) #if defined(CONFIG_MX23) #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) #elif defined(CONFIG_MX28) @@ -117,14 +117,14 @@ struct mxs_timrot_regs { #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 -#define TIMROT_TIMCTRLn_IRQ (1 << 15) -#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRLn_IRQ BIT(15) +#define TIMROT_TIMCTRLn_IRQ_EN BIT(14) #if defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#define TIMROT_TIMCTRLn_MATCH_MODE BIT(11) #endif -#define TIMROT_TIMCTRLn_POLARITY (1 << 8) -#define TIMROT_TIMCTRLn_UPDATE (1 << 7) -#define TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define TIMROT_TIMCTRLn_POLARITY BIT(8) +#define TIMROT_TIMCTRLn_UPDATE BIT(7) +#define TIMROT_TIMCTRLn_RELOAD BIT(6) #define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) #define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 #define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) @@ -210,18 +210,18 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) #endif #if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) +#define TIMROT_TIMCTRL3_IRQ BIT(15) +#define TIMROT_TIMCTRL3_IRQ_EN BIT(14) +#define TIMROT_TIMCTRL3_DUTU_VALID BIT(10) #endif -#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) +#define TIMROT_TIMCTRL3_DUTY_CYCLE BIT(9) #if defined(CONFIG_MX23) #define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) #define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 #define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) #define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) +#define TIMROT_TIMCTRL3_UPDATE BIT(7) +#define TIMROT_TIMCTRL3_RELOAD BIT(6) #define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) #define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 #define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h index 7ceb810..513d7fc 100644 --- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -30,29 +30,29 @@ struct mxs_uartapp_regs { }; #endif -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_SFTRST_MASK BIT(31) +#define UARTAPP_CTRL0_CLKGATE_MASK BIT(30) +#define UARTAPP_CTRL0_RUN_MASK BIT(29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK BIT(28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK BIT(27) #define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 #define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) #define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 #define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) +#define UARTAPP_CTRL1_RUN_MASK BIT(28) #define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 #define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_INVERT_RTS_MASK BIT(31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK BIT(30) +#define UARTAPP_CTRL2_INVERT_TX_MASK BIT(29) +#define UARTAPP_CTRL2_INVERT_RX_MASK BIT(28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK BIT(27) +#define UARTAPP_CTRL2_DMAONERR_MASK BIT(26) +#define UARTAPP_CTRL2_TXDMAE_MASK BIT(25) +#define UARTAPP_CTRL2_RXDMAE_MASK BIT(24) #define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 #define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) @@ -74,19 +74,19 @@ struct mxs_uartapp_regs { #define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) #define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) #define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_CTSEN_MASK BIT(15) +#define UARTAPP_CTRL2_RTSEN_MASK BIT(14) +#define UARTAPP_CTRL2_OUT2_MASK BIT(13) +#define UARTAPP_CTRL2_OUT1_MASK BIT(12) +#define UARTAPP_CTRL2_RTS_MASK BIT(11) +#define UARTAPP_CTRL2_DTR_MASK BIT(10) +#define UARTAPP_CTRL2_RXE_MASK BIT(9) +#define UARTAPP_CTRL2_TXE_MASK BIT(8) +#define UARTAPP_CTRL2_LBE_MASK BIT(7) +#define UARTAPP_CTRL2_USE_LCR2_MASK BIT(6) + +#define UARTAPP_CTRL2_SIRLP_MASK BIT(2) +#define UARTAPP_CTRL2_SIREN_MASK BIT(1) #define UARTAPP_CTRL2_UARTEN_MASK 0x01 #define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 @@ -97,7 +97,7 @@ struct mxs_uartapp_regs { #define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) #define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_SPS_MASK BIT(7) #define UARTAPP_LINECTRL_WLEN_OFFSET 5 #define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) #define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) @@ -105,10 +105,10 @@ struct mxs_uartapp_regs { #define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) #define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_FEN_MASK BIT(4) +#define UARTAPP_LINECTRL_STP2_MASK BIT(3) +#define UARTAPP_LINECTRL_EPS_MASK BIT(2) +#define UARTAPP_LINECTRL_PEN_MASK BIT(1) #define UARTAPP_LINECTRL_BRK_MASK 1 #define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 @@ -119,7 +119,7 @@ struct mxs_uartapp_regs { #define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) #define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_SPS_MASK BIT(7) #define UARTAPP_LINECTRL2_WLEN_OFFSET 5 #define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) #define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) @@ -127,60 +127,60 @@ struct mxs_uartapp_regs { #define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) #define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_LINECTRL2_FEN_MASK BIT(4) +#define UARTAPP_LINECTRL2_STP2_MASK BIT(3) +#define UARTAPP_LINECTRL2_EPS_MASK BIT(2) +#define UARTAPP_LINECTRL2_PEN_MASK BIT(1) + +#define UARTAPP_INTR_ABDIEN_MASK BIT(27) +#define UARTAPP_INTR_OEIEN_MASK BIT(26) +#define UARTAPP_INTR_BEIEN_MASK BIT(25) +#define UARTAPP_INTR_PEIEN_MASK BIT(24) +#define UARTAPP_INTR_FEIEN_MASK BIT(23) +#define UARTAPP_INTR_RTIEN_MASK BIT(22) +#define UARTAPP_INTR_TXIEN_MASK BIT(21) +#define UARTAPP_INTR_RXIEN_MASK BIT(20) +#define UARTAPP_INTR_DSRMIEN_MASK BIT(19) +#define UARTAPP_INTR_DCDMIEN_MASK BIT(18) +#define UARTAPP_INTR_CTSMIEN_MASK BIT(17) +#define UARTAPP_INTR_RIMIEN_MASK BIT(16) + +#define UARTAPP_INTR_ABDIS_MASK BIT(11) +#define UARTAPP_INTR_OEIS_MASK BIT(10) +#define UARTAPP_INTR_BEIS_MASK BIT(9) +#define UARTAPP_INTR_PEIS_MASK BIT(8) +#define UARTAPP_INTR_FEIS_MASK BIT(7) +#define UARTAPP_INTR_RTIS_MASK BIT(6) +#define UARTAPP_INTR_TXIS_MASK BIT(5) +#define UARTAPP_INTR_RXIS_MASK BIT(4) +#define UARTAPP_INTR_DSRMIS_MASK BIT(3) +#define UARTAPP_INTR_DCDMIS_MASK BIT(2) +#define UARTAPP_INTR_CTSMIS_MASK BIT(1) #define UARTAPP_INTR_RIMIS_MASK 0x1 #define UARTAPP_DATA_DATA_OFFSET 0 #define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_MASK BIT(31) #define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) #define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_MASK BIT(30) #define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) #define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_BUSY_MASK BIT(29) +#define UARTAPP_STAT_CTS_MASK BIT(28) +#define UARTAPP_STAT_TXFE_MASK BIT(27) +#define UARTAPP_STAT_RXFF_MASK BIT(26) +#define UARTAPP_STAT_TXFF_MASK BIT(25) +#define UARTAPP_STAT_RXFE_MASK BIT(24) #define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 #define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_OERR_MASK BIT(19) +#define UARTAPP_STAT_BERR_MASK BIT(18) +#define UARTAPP_STAT_PERR_MASK BIT(17) +#define UARTAPP_STAT_FERR_MASK BIT(16) #define UARTAPP_STAT_RXCOUNT_OFFSET 0 #define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF @@ -190,11 +190,11 @@ struct mxs_uartapp_regs { #define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 #define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_TXDMARUN_MASK BIT(5) +#define UARTAPP_DEBUG_RXDMARUN_MASK BIT(4) +#define UARTAPP_DEBUG_TXCMDEND_MASK BIT(3) +#define UARTAPP_DEBUG_RXCMDEND_MASK BIT(2) +#define UARTAPP_DEBUG_TXDMARQ_MASK BIT(1) #define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 #define UARTAPP_VERSION_MAJOR_OFFSET 24 @@ -212,9 +212,9 @@ struct mxs_uartapp_regs { #define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 #define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK BIT(4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK BIT(3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK BIT(2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK BIT(1) #define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 #endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usb.h b/arch/arm/include/asm/arch-mxs/regs-usb.h index 8313bec..29c8cc8 100644 --- a/arch/arm/include/asm/arch-mxs/regs-usb.h +++ b/arch/arm/include/asm/arch-mxs/regs-usb.h @@ -113,10 +113,10 @@ struct mxs_usb_regs { #define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) #define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 #define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) -#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) +#define HW_USBCTRL_HWGENERAL_BWT BIT(3) #define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 #define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) -#define HW_USBCTRL_HWGENERAL_RT (1 << 0) +#define HW_USBCTRL_HWGENERAL_RT BIT(0) #define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 #define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) @@ -124,13 +124,13 @@ struct mxs_usb_regs { #define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) #define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 #define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) -#define HW_USBCTRL_HWHOST_HC (1 << 0) +#define HW_USBCTRL_HWHOST_HC BIT(0) #define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 #define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) -#define HW_USBCTRL_HWDEVICE_DC (1 << 0) +#define HW_USBCTRL_HWDEVICE_DC BIT(0) -#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) +#define HW_USBCTRL_HWTXBUF_TXLCR BIT(31) #define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 #define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) #define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 @@ -146,9 +146,9 @@ struct mxs_usb_regs { #define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 #define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff -#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) -#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) -#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) +#define HW_USBCTRL_GPTIMERCTRL_GPTRUN BIT(31) +#define HW_USBCTRL_GPTIMERCTRL_GPTRST BIT(30) +#define HW_USBCTRL_GPTIMERCTRL_GPTMODE BIT(24) #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h index eabefc6..127e11f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ b/arch/arm/include/asm/arch-mxs/regs-usbphy.h @@ -23,84 +23,84 @@ struct mxs_usbphy_regs { mxs_reg_32(hw_usbphy_ip) }; -#define USBPHY_PWD_RXPWDRX (1 << 20) -#define USBPHY_PWD_RXPWDDIFF (1 << 19) -#define USBPHY_PWD_RXPWD1PT1 (1 << 18) -#define USBPHY_PWD_RXPWDENV (1 << 17) -#define USBPHY_PWD_TXPWDV2I (1 << 12) -#define USBPHY_PWD_TXPWDIBIAS (1 << 11) -#define USBPHY_PWD_TXPWDFS (1 << 10) +#define USBPHY_PWD_RXPWDRX BIT(20) +#define USBPHY_PWD_RXPWDDIFF BIT(19) +#define USBPHY_PWD_RXPWD1PT1 BIT(18) +#define USBPHY_PWD_RXPWDENV BIT(17) +#define USBPHY_PWD_TXPWDV2I BIT(12) +#define USBPHY_PWD_TXPWDIBIAS BIT(11) +#define USBPHY_PWD_TXPWDFS BIT(10) #define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) -#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) -#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) -#define USBPHY_TX_TXENCAL45DP (1 << 21) +#define USBPHY_TX_USBPHY_TX_SYNC_INVERT BIT(25) +#define USBPHY_TX_USBPHY_TX_SYNC_MUX BIT(24) +#define USBPHY_TX_TXENCAL45DP BIT(21) #define USBPHY_TX_TXCAL45DP_OFFSET 16 #define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) -#define USBPHY_TX_TXENCAL45DM (1 << 13) +#define USBPHY_TX_TXENCAL45DM BIT(13) #define USBPHY_TX_TXCAL45DM_OFFSET 8 #define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) #define USBPHY_TX_D_CAL_OFFSET 0 #define USBPHY_TX_D_CAL_MASK 0xf -#define USBPHY_RX_RXDBYPASS (1 << 22) +#define USBPHY_RX_RXDBYPASS BIT(22) #define USBPHY_RX_DISCONADJ_OFFSET 4 #define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) #define USBPHY_RX_ENVADJ_OFFSET 0 #define USBPHY_RX_ENVADJ_MASK 0x7 -#define USBPHY_CTRL_SFTRST (1 << 31) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) -#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) -#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) -#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) -#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) -#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) -#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) -#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) -#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) -#define USBPHY_CTRL_RESUME_IRQ (1 << 10) -#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) -#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) -#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) -#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) -#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) -#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) +#define USBPHY_CTRL_SFTRST BIT(31) +#define USBPHY_CTRL_CLKGATE BIT(30) +#define USBPHY_CTRL_UTMI_SUSPENDM BIT(29) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0 BIT(28) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) +#define USBPHY_CTRL_FSDLL_RST_EN BIT(24) +#define USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) +#define USBPHY_CTRL_ENIDCHG_WKUP BIT(22) +#define USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) +#define USBPHY_CTRL_WAKEUP_IRQ BIT(17) +#define USBPHY_CTRL_ENIRQWAKEUP BIT(16) +#define USBPHY_CTRL_ENUTMILEVEL3 BIT(15) +#define USBPHY_CTRL_ENUTMILEVEL2 BIT(14) +#define USBPHY_CTRL_DATA_ON_LRADC BIT(13) +#define USBPHY_CTRL_DEVPLUGIN_IRQ BIT(12) +#define USBPHY_CTRL_ENIRQDEVPLUGIN BIT(11) +#define USBPHY_CTRL_RESUME_IRQ BIT(10) +#define USBPHY_CTRL_ENIRQRESUMEDETECT BIT(9) +#define USBPHY_CTRL_RESUMEIRQSTICKY BIT(8) +#define USBPHY_CTRL_ENOTGIDDETECT BIT(7) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY BIT(5) +#define USBPHY_CTRL_ENDEVPLUGINDETECT BIT(4) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ BIT(3) +#define USBPHY_CTRL_ENIRQHOSTDISCON BIT(2) +#define USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) +#define USBPHY_STATUS_RESUME_STATUS BIT(10) +#define USBPHY_STATUS_OTGID_STATUS BIT(8) +#define USBPHY_STATUS_DEVPLUGIN_STATUS BIT(6) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS BIT(3) -#define USBPHY_DEBUG_CLKGATE (1 << 30) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) +#define USBPHY_DEBUG_CLKGATE BIT(30) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG BIT(29) #define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) -#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) +#define USBPHY_DEBUG_ENSQUELCHRESET BIT(24) #define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) -#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) +#define USBPHY_DEBUG_ENTX2RXCOUNT BIT(12) #define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) #define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) #define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) -#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD BIT(1) +#define USBPHY_DEBUG_OTGIDPIDLOCK BIT(0) #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) @@ -111,7 +111,7 @@ struct mxs_usbphy_regs { #define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) -#define USBPHY_DEBUG1_ENTX2TX (1 << 12) +#define USBPHY_DEBUG1_ENTX2TX BIT(12) #define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 #define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf @@ -128,11 +128,11 @@ struct mxs_usbphy_regs { #define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) #define USBPHY_IP_CP_SEL_OFFSET 19 #define USBPHY_IP_CP_SEL_MASK (0x3 << 19) -#define USBPHY_IP_TSTI_TX_DP (1 << 18) -#define USBPHY_IP_TSTI_TX_DM (1 << 17) -#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) -#define USBPHY_IP_EN_USB_CLKS (1 << 2) -#define USBPHY_IP_PLL_LOCKED (1 << 1) -#define USBPHY_IP_PLL_POWER (1 << 0) +#define USBPHY_IP_TSTI_TX_DP BIT(18) +#define USBPHY_IP_TSTI_TX_DM BIT(17) +#define USBPHY_IP_ANALOG_TESTMODE BIT(16) +#define USBPHY_IP_EN_USB_CLKS BIT(2) +#define USBPHY_IP_PLL_LOCKED BIT(1) +#define USBPHY_IP_PLL_POWER BIT(0) #endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index 9d001ff..39e0833 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -21,32 +21,32 @@ #ifndef __ASSEMBLY__ /* LVL_INTR_CLEAR bits */ -#define USBOTGSS_INT_CLR (1 << 4) +#define USBOTGSS_INT_CLR BIT(4) /* IP_SW_RESET bits */ -#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ -#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ +#define USBOTGSS_SW_RST BIT(0) /* reset USBOTG */ +#define CPGMACSS_SW_RST BIT(1) /* reset CPGMAC */ /* DEVCONF2 bits */ -#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_PHY_GPIOMODE BIT(23) #define CONF2_OTGMODE (3 << 14) #define CONF2_NO_OVERRIDE (0 << 14) -#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_HOST BIT(14) #define CONF2_FORCE_DEVICE (2 << 14) #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) -#define CONF2_SESENDEN (1 << 13) -#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_SESENDEN BIT(13) +#define CONF2_VBDTCTEN BIT(12) #define CONF2_REFFREQ_24MHZ (2 << 8) #define CONF2_REFFREQ_26MHZ (7 << 8) #define CONF2_REFFREQ_13MHZ (6 << 8) #define CONF2_REFFREQ (0xf << 8) -#define CONF2_PHYCLKGD (1 << 7) -#define CONF2_VBUSSENSE (1 << 6) -#define CONF2_PHY_PLLON (1 << 5) -#define CONF2_RESET (1 << 4) -#define CONF2_PHYPWRDN (1 << 3) -#define CONF2_OTGPWRDN (1 << 2) -#define CONF2_DATPOL (1 << 1) +#define CONF2_PHYCLKGD BIT(7) +#define CONF2_VBUSSENSE BIT(6) +#define CONF2_PHY_PLLON BIT(5) +#define CONF2_RESET BIT(4) +#define CONF2_PHYPWRDN BIT(3) +#define CONF2_OTGPWRDN BIT(2) +#define CONF2_DATPOL BIT(1) /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 diff --git a/arch/arm/include/asm/arch-omap3/dma.h b/arch/arm/include/asm/arch-omap3/dma.h index 5f0ad35..f10606c 100644 --- a/arch/arm/include/asm/arch-omap3/dma.h +++ b/arch/arm/include/asm/arch-omap3/dma.h @@ -50,12 +50,12 @@ int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); #define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) #define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) -#define CCR_RD_ACTIVE_MASK (1 << 9) -#define CCR_WR_ACTIVE_MASK (1 << 10) +#define CCR_RD_ACTIVE_MASK BIT(9) +#define CCR_WR_ACTIVE_MASK BIT(10) -#define CSR_TRANS_ERR (1 << 8) -#define CSR_SUPERVISOR_ERR (1 << 10) -#define CSR_MISALIGNED_ADRS_ERR (1 << 11) +#define CSR_TRANS_ERR BIT(8) +#define CSR_SUPERVISOR_ERR BIT(10) +#define CSR_MISALIGNED_ADRS_ERR BIT(11) /* others */ #define CHAN_NR_MIN 0 diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index 8bf6b48..e0d41f2 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -149,22 +149,22 @@ struct venc_regs { #define GFX_FORMAT_SHIFT 1 #define LOADMODE_SHIFT 1 -#define DSS_SOFTRESET (1 << 1) +#define DSS_SOFTRESET BIT(1) #define DSS_RESETDONE 1 /* Enabling Display controller */ #define LCD_ENABLE 1 -#define DIG_ENABLE (1 << 1) -#define GO_LCD (1 << 5) -#define GO_DIG (1 << 6) -#define GP_OUT0 (1 << 15) -#define GP_OUT1 (1 << 16) +#define DIG_ENABLE BIT(1) +#define GO_LCD BIT(5) +#define GO_DIG BIT(6) +#define GP_OUT0 BIT(15) +#define GP_OUT1 BIT(16) /* Configure VENC DSS Params */ -#define VENC_CLK_ENABLE (1 << 3) -#define DAC_DEMEN (1 << 4) -#define DAC_POWERDN (1 << 5) -#define VENC_OUT_SEL (1 << 6) +#define VENC_CLK_ENABLE BIT(3) +#define DAC_DEMEN BIT(4) +#define DAC_POWERDN BIT(5) +#define VENC_OUT_SEL BIT(6) #define DIG_LPP_SHIFT 16 /* LCD display type */ @@ -178,11 +178,11 @@ struct venc_regs { #define LCD_INTERFACE_24_BIT 3 /* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) -#define DSS_ONOFF (1 << 17) +#define DSS_IVS BIT(12) +#define DSS_IHS BIT(13) +#define DSS_IPC BIT(14) +#define DSS_IEO BIT(15) +#define DSS_ONOFF BIT(17) /* GFX format */ #define GFXFORMAT_BITMAP1 (0x0 << 1) diff --git a/arch/arm/include/asm/arch-omap3/ehci.h b/arch/arm/include/asm/arch-omap3/ehci.h index d962755..822c4ae 100644 --- a/arch/arm/include/asm/arch-omap3/ehci.h +++ b/arch/arm/include/asm/arch-omap3/ehci.h @@ -17,19 +17,19 @@ #define OMAP_EHCI_BASE 0x48064800UL /* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY BIT(8) #define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 /* UHH Register Set */ -#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) +#define OMAP_UHH_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_UHH_SYSCONFIG_CACTIVITY BIT(8) +#define OMAP_UHH_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_UHH_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_UHH_SYSCONFIG_MIDLEMODE BIT(12) +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE BIT(2) #define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_CACTIVITY | \ OMAP_UHH_SYSCONFIG_SIDLEMODE | \ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 9f2896c..c83aa69 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -41,19 +41,19 @@ typedef struct t2 { unsigned int pbias_lite; /* 0x520 */ } t2_t; -#define MMCSDIO1ADPCLKISEL (1 << 24) -#define MMCSDIO2ADPCLKISEL (1 << 6) +#define MMCSDIO1ADPCLKISEL BIT(24) +#define MMCSDIO2ADPCLKISEL BIT(6) -#define EN_MMC1 (1 << 24) -#define EN_MMC2 (1 << 25) -#define EN_MMC3 (1 << 30) +#define EN_MMC1 BIT(24) +#define EN_MMC2 BIT(25) +#define EN_MMC3 BIT(30) -#define PBIASLITEPWRDNZ0 (1 << 1) -#define PBIASSPEEDCTRL0 (1 << 2) -#define PBIASLITEPWRDNZ1 (1 << 9) -#define PBIASLITEVMODE0 (1 << 0) +#define PBIASLITEPWRDNZ0 BIT(1) +#define PBIASSPEEDCTRL0 BIT(2) +#define PBIASLITEPWRDNZ1 BIT(9) +#define PBIASLITEVMODE0 BIT(0) -#define CTLPROGIO1SPEEDCTRL (1 << 20) +#define CTLPROGIO1SPEEDCTRL BIT(20) /* * OMAP HSMMC register definitions diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 3277b40..66f84ae 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -24,20 +24,20 @@ * M0 - Mode 0 */ -#define IEN (1 << 8) +#define IEN BIT(8) #define IDIS (0 << 8) -#define PTU (1 << 4) +#define PTU BIT(4) #define PTD (0 << 4) -#define EN (1 << 3) +#define EN BIT(3) #define DIS (0 << 3) -#define SB_LOW (1 << 9) +#define SB_LOW BIT(9) #define SB_HI (5 << 9) #define SB_HIZ (2 << 9) -#define SB_PD (1 << 12) +#define SB_PD BIT(12) #define SB_PU (3 << 12) -#define WKEN (1 << 14) +#define WKEN BIT(14) #define M0 0 #define M1 1 diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h index 002ef7e..48dde76 100644 --- a/arch/arm/include/asm/arch-omap3/omap3-regs.h +++ b/arch/arm/include/asm/arch-omap3/omap3-regs.h @@ -16,15 +16,15 @@ */ /* Values for GPMC_CONFIG1 - signal control parameters */ -#define WRAPBURST (1 << 31) -#define READMULTIPLE (1 << 30) -#define READTYPE (1 << 29) -#define WRITEMULTIPLE (1 << 28) -#define WRITETYPE (1 << 27) +#define WRAPBURST BIT(31) +#define READMULTIPLE BIT(30) +#define READTYPE BIT(29) +#define WRITEMULTIPLE BIT(28) +#define WRITETYPE BIT(27) #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) -#define WAITREADMONITORING (1 << 22) -#define WAITWRITEMONITORING (1 << 21) +#define WAITREADMONITORING BIT(22) +#define WAITWRITEMONITORING BIT(21) #define WAITMONITORINGTIME(x) (((x) & 3) << 18) #define WAITPINSELECT(x) (((x) & 3) << 16) #define DEVICESIZE(x) (((x) & 3) << 12) @@ -33,28 +33,28 @@ #define DEVICETYPE(x) (((x) & 3) << 10) #define DEVICETYPE_NOR DEVICETYPE(0) #define DEVICETYPE_NAND DEVICETYPE(2) -#define MUXADDDATA (1 << 9) -#define TIMEPARAGRANULARITY (1 << 4) +#define MUXADDDATA BIT(9) +#define TIMEPARAGRANULARITY BIT(4) #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) /* Values for GPMC_CONFIG2 - CS timing */ #define CSWROFFTIME(x) (((x) & 0x1f) << 16) #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) -#define CSEXTRADELAY (1 << 7) +#define CSEXTRADELAY BIT(7) #define CSONTIME(x) (((x) & 0xf) << 0) /* Values for GPMC_CONFIG3 - nADV timing */ #define ADVWROFFTIME(x) (((x) & 0x1f) << 16) #define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) -#define ADVEXTRADELAY (1 << 7) +#define ADVEXTRADELAY BIT(7) #define ADVONTIME(x) (((x) & 0xf) << 0) /* Values for GPMC_CONFIG4 - nWE and nOE timing */ #define WEOFFTIME(x) (((x) & 0x1f) << 24) -#define WEEXTRADELAY (1 << 23) +#define WEEXTRADELAY BIT(23) #define WEONTIME(x) (((x) & 0xf) << 16) #define OEOFFTIME(x) (((x) & 0x1f) << 8) -#define OEEXTRADELAY (1 << 7) +#define OEEXTRADELAY BIT(7) #define OEONTIME(x) (((x) & 0xf) << 0) /* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ @@ -67,13 +67,13 @@ #define WRACCESSTIME(x) (((x) & 0x1f) << 24) #define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) #define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) -#define CYCLE2CYCLESAMECSEN (1 << 7) -#define CYCLE2CYCLEDIFFCSEN (1 << 6) +#define CYCLE2CYCLESAMECSEN BIT(7) +#define CYCLE2CYCLEDIFFCSEN BIT(6) #define BUSTURNAROUND(x) (((x) & 0xf) << 0) /* Values for GPMC_CONFIG7 - CS address mapping configuration */ #define MASKADDRESS(x) (((x) & 0xf) << 8) -#define CSVALID (1 << 6) +#define CSVALID BIT(6) #define BASEADDRESS(x) (((x) & 0x3f) << 0) #endif /* _OMAP3_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index f3a682a..8227436 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -20,18 +20,18 @@ /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_OVERRIDE_MASK BIT(0) #define CM_DLL_CTRL_NO_OVERRIDE 0 /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_REGM4XEN_MASK BIT(11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK BIT(10) #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK BIT(9) #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK BIT(8) #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) #define CM_CLKMODE_DPLL_EN_SHIFT 0 @@ -57,7 +57,7 @@ #define CM_CLKSEL_DPLL_N_SHIFT 0 #define CM_CLKSEL_DPLL_N_MASK 0x7F #define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) +#define CM_CLKSEL_DCC_EN_MASK BIT(22) /* CM_SYS_CLKSEL */ #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 @@ -120,16 +120,16 @@ #define MODULE_CLKCTRL_IDLEST_DISABLED 3 /* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK BIT(8) /* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) +#define HSMMC_CLKCTRL_CLKSEL_MASK BIT(24) /* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) +#define GPTIMER1_CLKCTRL_CLKSEL_MASK BIT(24) /* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) +#define ISS_CLKCTRL_OPTFCLKEN_MASK BIT(8) /* CM_DSS_DSS_CLKCTRL */ #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 @@ -139,9 +139,9 @@ /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK BIT(24) #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK BIT(25) /* Clock frequencies */ #define OMAP_SYS_CLK_IND_38_4_MHZ 6 @@ -179,7 +179,7 @@ #define TPS62361_VSEL0_GPIO 7 /* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_ENABLE_MASK BIT(8) #define AUXCLK_SRCSELECT_SHIFT 1 #define AUXCLK_SRCSELECT_MASK (3 << 1) #define AUXCLK_CLKDIV_SHIFT 16 diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h index 984c8b9..6524dbd 100644 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -29,19 +29,19 @@ /* UHH, TLL and opt clocks */ #define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL -#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24) +#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK BIT(24) /* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY BIT(8) #define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 #define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOIDLE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY BIT(4) #define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ OMAP_UHH_SYSCONFIG_NOSTDBY) diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h index b222778..adb6403 100644 --- a/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -21,13 +21,13 @@ struct pad_conf_entry { }; #ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) +#define OFF_PD BIT(12) #define OFF_PU (3 << 12) #define OFF_OUT_PTD (0 << 10) #define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) +#define OFF_IN BIT(10) #define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) +#define OFF_EN BIT(9) #else #define OFF_PD (0 << 12) #define OFF_PU (0 << 12) @@ -38,11 +38,11 @@ struct pad_conf_entry { #define OFF_EN (0 << 9) #endif -#define IEN (1 << 8) +#define IEN BIT(8) #define IDIS (0 << 8) #define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) +#define PTD BIT(3) +#define EN BIT(3) #define DIS (0 << 3) #define M0 0 diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index d43dc26..2e63dad 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -89,9 +89,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) +#define MMC1_PWRDNZ BIT(26) +#define MMC1_PBIASLITE_PWRDNZ BIT(22) +#define MMC1_PBIASLITE_VMODE BIT(21) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f8e5630..371c08f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -21,18 +21,18 @@ /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_OVERRIDE_MASK BIT(0) #define CM_DLL_CTRL_NO_OVERRIDE 0 /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_REGM4XEN_MASK BIT(11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK BIT(10) #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK BIT(9) #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK BIT(8) #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) #define CM_CLKMODE_DPLL_EN_SHIFT 0 @@ -51,8 +51,8 @@ #define ST_DPLL_CLK_MASK 1 /* SGX */ -#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) -#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) +#define CLKSEL_GPU_HYD_GCLK_MASK BIT(25) +#define CLKSEL_GPU_CORE_GCLK_MASK BIT(24) /* CM_CLKSEL_DPLL */ #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 @@ -62,7 +62,7 @@ #define CM_CLKSEL_DPLL_N_SHIFT 0 #define CM_CLKSEL_DPLL_N_MASK 0x7F #define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) +#define CM_CLKSEL_DCC_EN_MASK BIT(22) /* CM_SYS_CLKSEL */ #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 @@ -131,20 +131,20 @@ #define MODULE_CLKCTRL_IDLEST_DISABLED 3 /* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK BIT(8) /* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +#define HSMMC_CLKCTRL_CLKSEL_MASK BIT(24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK BIT(25) /* CM_L3INIT_SATA_CLKCTRL */ -#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) +#define SATA_CLKCTRL_OPTFCLKEN_MASK BIT(8) /* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) +#define GPTIMER1_CLKCTRL_CLKSEL_MASK BIT(24) /* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) +#define ISS_CLKCTRL_OPTFCLKEN_MASK BIT(8) /* CM_DSS_DSS_CLKCTRL */ #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 @@ -153,47 +153,47 @@ #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */ -#define OPTFCLKEN_FUNC48M_CLK (1 << 15) -#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) -#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) -#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) -#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) -#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) -#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) -#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) -#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) -#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) +#define OPTFCLKEN_FUNC48M_CLK BIT(15) +#define OPTFCLKEN_HSIC480M_P2_CLK BIT(14) +#define OPTFCLKEN_HSIC480M_P1_CLK BIT(13) +#define OPTFCLKEN_HSIC60M_P2_CLK BIT(12) +#define OPTFCLKEN_HSIC60M_P1_CLK BIT(11) +#define OPTFCLKEN_UTMI_P3_CLK BIT(10) +#define OPTFCLKEN_UTMI_P2_CLK BIT(9) +#define OPTFCLKEN_UTMI_P1_CLK BIT(8) +#define OPTFCLKEN_HSIC480M_P3_CLK BIT(7) +#define OPTFCLKEN_HSIC60M_P3_CLK BIT(6) /* CM_L3INIT_USB_TLL_HS_CLKCTRL */ -#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) -#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) -#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) +#define OPTFCLKEN_USB_CH0_CLK_ENABLE BIT(8) +#define OPTFCLKEN_USB_CH1_CLK_ENABLE BIT(9) +#define OPTFCLKEN_USB_CH2_CLK_ENABLE BIT(10) /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ -#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K BIT(8) /* CM_L3INIT_USB_OTG_SS_CLKCTRL */ -#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) -#define OPTFCLKEN_REFCLK960M (1 << 8) +#define OTG_SS_CLKCTRL_MODULEMODE_HW BIT(0) +#define OPTFCLKEN_REFCLK960M BIT(8) /* CM_L3INIT_OCP2SCP1_CLKCTRL */ -#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) +#define OCP2SCP1_CLKCTRL_MODULEMODE_HW BIT(0) /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK BIT(26) /* CM_WKUPAON_SCRM_CLKCTRL */ #define OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) +#define OPTFCLKEN_SCRM_PER_MASK BIT(9) #define OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) +#define OPTFCLKEN_SCRM_CORE_MASK BIT(8) /* CM_COREAON_IO_SRCOMP_CLKCTRL */ #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 -#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) +#define OPTFCLKEN_SRCOMP_FCLK_MASK BIT(8) /* PRM_RSTTIME */ #define RSTTIME1_SHIFT 0 @@ -206,8 +206,8 @@ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 /* CTRL_CORE_SRCOMP_NORTH_SIDE */ -#define USB2PHY_DISCHGDET (1 << 29) -#define USB2PHY_AUTORESUME_EN (1 << 30) +#define USB2PHY_DISCHGDET BIT(29) +#define USB2PHY_AUTORESUME_EN BIT(30) /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 @@ -337,10 +337,10 @@ #define V_SCLK V_OSCK /* CKO buffer control */ -#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) +#define CKOBUFFER_CLK_ENABLE_MASK BIT(28) /* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) +#define AUXCLK_ENABLE_MASK BIT(8) #define AUXCLK_SRCSELECT_SHIFT 1 #define AUXCLK_SRCSELECT_MASK (3 << 1) #define AUXCLK_CLKDIV_SHIFT 16 diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h index 63aaa02..16f462a 100644 --- a/arch/arm/include/asm/arch-omap5/ehci.h +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -13,16 +13,16 @@ #define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) /* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY BIT(8) #define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 #define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOIDLE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY BIT(4) #define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ OMAP_UHH_SYSCONFIG_NOSTDBY) diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index e155387..6f41797 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -12,18 +12,18 @@ #include -#define FSC (1 << 19) +#define FSC BIT(19) #define SSC (0 << 19) -#define IEN (1 << 18) +#define IEN BIT(18) #define IDIS (0 << 18) -#define PTU (1 << 17) +#define PTU BIT(17) #define PTD (0 << 17) -#define PEN (1 << 16) +#define PEN BIT(16) #define PDIS (0 << 16) -#define WKEN (1 << 24) +#define WKEN BIT(24) #define WKDIS (0 << 24) #define M0 0 diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h index 3e93a15..1c9df36 100644 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -13,13 +13,13 @@ #include #ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) +#define OFF_PD BIT(12) #define OFF_PU (3 << 12) #define OFF_OUT_PTD (0 << 10) #define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) +#define OFF_IN BIT(10) #define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) +#define OFF_EN BIT(9) #else #define OFF_PD (0 << 12) #define OFF_PU (0 << 12) @@ -30,11 +30,11 @@ #define OFF_EN (0 << 9) #endif -#define IEN (1 << 8) +#define IEN BIT(8) #define IDIS (0 << 8) #define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) +#define PTD BIT(3) +#define EN BIT(3) #define DIS (0 << 3) #define M0 0 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e844bfb..90acfdf 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -103,10 +103,10 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 -#define SDCARD_BIAS_PWRDNZ (1 << 27) -#define SDCARD_PWRDNZ (1 << 26) -#define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_PBIASLITE_VMODE (1 << 21) +#define SDCARD_BIAS_PWRDNZ BIT(27) +#define SDCARD_PWRDNZ BIT(26) +#define SDCARD_BIAS_HIZ_MODE BIT(25) +#define SDCARD_PBIASLITE_VMODE BIT(21) #ifndef __ASSEMBLY__ @@ -189,17 +189,17 @@ struct s32ktimer { /* CONTROL_SRCOMP_XXX_SIDE */ #define OVERRIDE_XS_SHIFT 30 -#define OVERRIDE_XS_MASK (1 << 30) +#define OVERRIDE_XS_MASK BIT(30) #define SRCODE_READ_XS_SHIFT 12 #define SRCODE_READ_XS_MASK (0xff << 12) #define PWRDWN_XS_SHIFT 11 -#define PWRDWN_XS_MASK (1 << 11) +#define PWRDWN_XS_MASK BIT(11) #define DIVIDE_FACTOR_XS_SHIFT 4 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) #define MULTIPLY_FACTOR_XS_SHIFT 1 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 -#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) +#define SRCODE_OVERRIDE_SEL_XS_MASK BIT(0) /* ABB settings */ #define OMAP_ABB_SETTLING_TIME 50 diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h index b69165b..976c721 100644 --- a/arch/arm/include/asm/arch-omap5/sata.h +++ b/arch/arm/include/asm/arch-omap5/sata.h @@ -20,7 +20,7 @@ #define TI_SATA_CDRLOCK 0x04 /* Register Set */ -#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) +#define TI_SATA_SYSCONFIG_OVERRIDE0 BIT(16) #define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) #define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index b81b42c..c9b5967 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -130,25 +130,25 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR(x) (0x40000000 | ((x) << 2)) -#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ -#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ -#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define DCSR_RUN BIT(31) /* Run Bit (read / write) */ +#define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ +#define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */ #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ -#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ -#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ -#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ -#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ -#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ +#define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */ +#define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ +#define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ +#define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ +#define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ +#define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ +#define DCSR_ENRINTR BIT(9) /* The end of Receive */ #endif -#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ -#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ -#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ -#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ -#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ +#define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ +#define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ +#define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ +#define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ +#define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ #define DINT 0x400000f0 /* DMA Interrupt Register */ @@ -217,7 +217,7 @@ typedef void (*ExcpHndlr) (void) ; #define DRCMRRXMMC DRCMR21 #define DRCMRTXMMC DRCMR22 -#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ +#define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ #define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */ @@ -291,19 +291,19 @@ typedef void (*ExcpHndlr) (void) ; #define DCMD(x) (0x4000020c | ((x) << 4)) #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ -#define DDADR_STOP (1 << 0) /* Stop (read / write) */ - -#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ -#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ -#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ -#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ -#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ -#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ -#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ -#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ +#define DDADR_STOP BIT(0) /* Stop (read / write) */ + +#define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ +#define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ +#define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ +#define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ +#define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ +#define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ +#define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ +#define DCMD_BURST8 BIT(16) /* 8 byte burst */ #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ -#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ +#define DCMD_WIDTH1 BIT(14) /* 1 byte width */ #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ @@ -362,70 +362,70 @@ typedef void (*ExcpHndlr) (void) ; * AC97 Controller registers */ #define POCR 0x40500000 /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FEIE BIT(3) /* FIFO Error Interrupt Enable */ #define PICR 0x40500004 /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FEIE BIT(3) /* FIFO Error Interrupt Enable */ #define MCCR 0x40500008 /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FEIE BIT(3) /* FIFO Error Interrupt Enable */ #define GCR 0x4050000C /* Global Control Register */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ +#define GCR_CDONE_IE BIT(19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE BIT(18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN BIT(9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN BIT(8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN BIT(5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN BIT(4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF BIT(3) /* AC-link Shut Off */ +#define GCR_WARM_RST BIT(2) /* AC97 Warm Reset */ +#define GCR_COLD_RST BIT(1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE BIT(0) /* Codec GPI Interrupt Enable */ #define POSR 0x40500010 /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FIFOE BIT(4) /* FIFO error */ #define PISR 0x40500014 /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_FIFOE BIT(4) /* FIFO error */ #define MCSR 0x40500018 /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_FIFOE BIT(4) /* FIFO error */ #define GSR 0x4050001C /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ +#define GSR_CDONE BIT(19) /* Command Done */ +#define GSR_SDONE BIT(18) /* Status Done */ +#define GSR_RDCS BIT(15) /* Read Completion Status */ +#define GSR_BIT3SLT12 BIT(14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 BIT(13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 BIT(12) /* Bit 1 of slot 12 */ +#define GSR_SECRES BIT(11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES BIT(10) /* Primary Resume Interrupt */ +#define GSR_SCR BIT(9) /* Secondary Codec Ready */ +#define GSR_PCR BIT(8) /* Primary Codec Ready */ +#define GSR_MINT BIT(7) /* Mic In Interrupt */ +#define GSR_POINT BIT(6) /* PCM Out Interrupt */ +#define GSR_PIINT BIT(5) /* PCM In Interrupt */ +#define GSR_MOINT BIT(2) /* Modem Out Interrupt */ +#define GSR_MIINT BIT(1) /* Modem In Interrupt */ +#define GSR_GSCI BIT(0) /* Codec GPI Status Change Interrupt */ #define CAR 0x40500020 /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ +#define CAR_CAIP BIT(0) /* Codec Access In Progress */ #define PCDR 0x40500040 /* PCM FIFO Data Register */ #define MCDR 0x40500060 /* Mic-in FIFO Data Register */ #define MOCR 0x40500100 /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FEIE BIT(3) /* FIFO Error */ #define MICR 0x40500108 /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FEIE BIT(3) /* FIFO Error */ #define MOSR 0x40500110 /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FIFOE BIT(4) /* FIFO error */ #define MISR 0x40500118 /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_FIFOE BIT(4) /* FIFO error */ #define MODR 0x40500140 /* Modem FIFO Data Register */ @@ -441,23 +441,23 @@ typedef void (*ExcpHndlr) (void) ; #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define UDCCR 0x40600000 /* UDC Control Register */ -#define UDCCR_UDE (1 << 0) /* UDC enable */ -#define UDCCR_UDA (1 << 1) /* UDC active */ -#define UDCCR_RSM (1 << 2) /* Device resume */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */ -#define UDCCR_RESIR (1 << 29) /* Resume interrupt request */ -#define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */ -#define UDCCR_SM (1 << 28) /* Suspend interrupt mask */ -#define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */ -#define UDCCR_REM (1 << 27) /* Reset interrupt mask */ -#define UDCCR_RM (1 << 29) /* resume interrupt mask */ +#define UDCCR_UDE BIT(0) /* UDC enable */ +#define UDCCR_UDA BIT(1) /* UDC active */ +#define UDCCR_RSM BIT(2) /* Device resume */ +#define UDCCR_EMCE BIT(3) /* Endpoint Memory Configuration Error */ +#define UDCCR_SMAC BIT(4) /* Switch Endpoint Memory to Active Configuration */ +#define UDCCR_RESIR BIT(29) /* Resume interrupt request */ +#define UDCCR_SUSIR BIT(28) /* Suspend interrupt request */ +#define UDCCR_SM BIT(28) /* Suspend interrupt mask */ +#define UDCCR_RSTIR BIT(27) /* Reset interrupt request */ +#define UDCCR_REM BIT(27) /* Reset interrupt mask */ +#define UDCCR_RM BIT(29) /* resume interrupt mask */ #define UDCCR_SRM (UDCCR_SM|UDCCR_RM) -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ +#define UDCCR_OEN BIT(31) /* On-the-Go Enable */ +#define UDCCR_AALTHNP BIT(30) /* A-device Alternate Host Negotiation Protocol Port Support */ +#define UDCCR_AHNP BIT(29) /* A-device Host Negotiation Protocol Support */ +#define UDCCR_BHNP BIT(28) /* B-device Host Negotiation Protocol Enable */ +#define UDCCR_DWRE BIT(16) /* Device Remote Wake-up Enable */ #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ #define UDCCR_ACN_S 11 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ @@ -466,76 +466,76 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCR_AAISN_S 5 #define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */ -#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ -#define UDCCS0_IPR (1 << 1) /* IN packet ready */ -#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */ -#define UDCCS0_SST (1 << 4) /* Sent stall */ -#define UDCCS0_FST (1 << 5) /* Force stall */ -#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ -#define UDCCS0_SA (1 << 7) /* Setup active */ +#define UDCCS0_OPR BIT(0) /* OUT packet ready */ +#define UDCCS0_IPR BIT(1) /* IN packet ready */ +#define UDCCS0_FTF BIT(2) /* Flush Tx FIFO */ +#define UDCCS0_DRWF BIT(16) /* Device remote wakeup feature */ +#define UDCCS0_SST BIT(4) /* Sent stall */ +#define UDCCS0_FST BIT(5) /* Force stall */ +#define UDCCS0_RNE BIT(6) /* Receive FIFO no empty */ +#define UDCCS0_SA BIT(7) /* Setup active */ /* Bulk IN - Endpoint 1,6,11 */ #define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */ #define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */ #define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */ -#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */ -#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_BI_SST (1 << 4) /* Sent stall */ -#define UDCCS_BI_FST (1 << 5) /* Force stall */ -#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ +#define UDCCS_BI_TFS BIT(0) /* Transmit FIFO service */ +#define UDCCS_BI_TPC BIT(1) /* Transmit packet complete */ +#define UDCCS_BI_FTF BIT(8) /* Flush Tx FIFO */ +#define UDCCS_BI_TUR BIT(3) /* Transmit FIFO underrun */ +#define UDCCS_BI_SST BIT(4) /* Sent stall */ +#define UDCCS_BI_FST BIT(5) /* Force stall */ +#define UDCCS_BI_TSP BIT(7) /* Transmit short packet */ /* Bulk OUT - Endpoint 2,7,12 */ #define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */ #define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */ #define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */ -#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_BO_DME (1 << 3) /* DMA enable */ -#define UDCCS_BO_SST (1 << 4) /* Sent stall */ -#define UDCCS_BO_FST (1 << 5) /* Force stall */ -#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ +#define UDCCS_BO_RFS BIT(0) /* Receive FIFO service */ +#define UDCCS_BO_RPC BIT(1) /* Receive packet complete */ +#define UDCCS_BO_DME BIT(3) /* DMA enable */ +#define UDCCS_BO_SST BIT(4) /* Sent stall */ +#define UDCCS_BO_FST BIT(5) /* Force stall */ +#define UDCCS_BO_RNE BIT(6) /* Receive FIFO not empty */ +#define UDCCS_BO_RSP BIT(7) /* Receive short packet */ /* Isochronous IN - Endpoint 3,8,13 */ #define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */ #define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */ #define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */ -#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ +#define UDCCS_II_TFS BIT(0) /* Transmit FIFO service */ +#define UDCCS_II_TPC BIT(1) /* Transmit packet complete */ +#define UDCCS_II_FTF BIT(2) /* Flush Tx FIFO */ +#define UDCCS_II_TUR BIT(3) /* Transmit FIFO underrun */ +#define UDCCS_II_TSP BIT(7) /* Transmit short packet */ /* Isochronous OUT - Endpoint 4,9,14 */ #define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */ #define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */ #define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */ -#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ -#define UDCCS_IO_DME (1 << 3) /* DMA enable */ -#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ +#define UDCCS_IO_RFS BIT(0) /* Receive FIFO service */ +#define UDCCS_IO_RPC BIT(1) /* Receive packet complete */ +#define UDCCS_IO_ROF BIT(3) /* Receive overflow */ +#define UDCCS_IO_DME BIT(3) /* DMA enable */ +#define UDCCS_IO_RNE BIT(6) /* Receive FIFO not empty */ +#define UDCCS_IO_RSP BIT(7) /* Receive short packet */ /* Interrupt IN - Endpoint 5,10,15 */ #define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ #define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ #define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ -#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_INT_SST (1 << 4) /* Sent stall */ -#define UDCCS_INT_FST (1 << 5) /* Force stall */ -#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ +#define UDCCS_INT_TFS BIT(0) /* Transmit FIFO service */ +#define UDCCS_INT_TPC BIT(1) /* Transmit packet complete */ +#define UDCCS_INT_FTF BIT(2) /* Flush Tx FIFO */ +#define UDCCS_INT_TUR BIT(3) /* Transmit FIFO underrun */ +#define UDCCS_INT_SST BIT(4) /* Sent stall */ +#define UDCCS_INT_FST BIT(5) /* Force stall */ +#define UDCCS_INT_TSP BIT(7) /* Transmit short packet */ #define UFNRH 0x40600060 /* UDC Frame Number Register High */ #define UFNRL 0x40600014 /* UDC Frame Number Register Low */ @@ -564,98 +564,98 @@ typedef void (*ExcpHndlr) (void) ; #define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */ -#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ -#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ -#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ -#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ -#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ -#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ -#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ -#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ +#define UICR0_IM0 BIT(0) /* Interrupt mask ep 0 */ +#define UICR0_IM1 BIT(1) /* Interrupt mask ep 1 */ +#define UICR0_IM2 BIT(2) /* Interrupt mask ep 2 */ +#define UICR0_IM3 BIT(3) /* Interrupt mask ep 3 */ +#define UICR0_IM4 BIT(4) /* Interrupt mask ep 4 */ +#define UICR0_IM5 BIT(5) /* Interrupt mask ep 5 */ +#define UICR0_IM6 BIT(6) /* Interrupt mask ep 6 */ +#define UICR0_IM7 BIT(7) /* Interrupt mask ep 7 */ #define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */ -#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ -#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ -#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ -#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ -#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ -#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ -#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ -#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ +#define UICR1_IM8 BIT(0) /* Interrupt mask ep 8 */ +#define UICR1_IM9 BIT(1) /* Interrupt mask ep 9 */ +#define UICR1_IM10 BIT(2) /* Interrupt mask ep 10 */ +#define UICR1_IM11 BIT(3) /* Interrupt mask ep 11 */ +#define UICR1_IM12 BIT(4) /* Interrupt mask ep 12 */ +#define UICR1_IM13 BIT(5) /* Interrupt mask ep 13 */ +#define UICR1_IM14 BIT(6) /* Interrupt mask ep 14 */ +#define UICR1_IM15 BIT(7) /* Interrupt mask ep 15 */ #define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */ -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ +#define USIR0_IR0 BIT(0) /* Interrup request ep 0 */ +#define USIR0_IR1 BIT(2) /* Interrup request ep 1 */ +#define USIR0_IR2 BIT(4) /* Interrup request ep 2 */ +#define USIR0_IR3 BIT(3) /* Interrup request ep 3 */ +#define USIR0_IR4 BIT(4) /* Interrup request ep 4 */ +#define USIR0_IR5 BIT(5) /* Interrup request ep 5 */ +#define USIR0_IR6 BIT(6) /* Interrup request ep 6 */ +#define USIR0_IR7 BIT(7) /* Interrup request ep 7 */ #define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ +#define USIR1_IR8 BIT(0) /* Interrup request ep 8 */ +#define USIR1_IR9 BIT(1) /* Interrup request ep 9 */ +#define USIR1_IR10 BIT(2) /* Interrup request ep 10 */ +#define USIR1_IR11 BIT(3) /* Interrup request ep 11 */ +#define USIR1_IR12 BIT(4) /* Interrup request ep 12 */ +#define USIR1_IR13 BIT(5) /* Interrup request ep 13 */ +#define USIR1_IR14 BIT(6) /* Interrup request ep 14 */ +#define USIR1_IR15 BIT(7) /* Interrup request ep 15 */ #define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */ #define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ +#define UDCICR_FIFOERR BIT(1) /* FIFO Error interrupt for EP */ +#define UDCICR_PKTCOMPL BIT(0) /* Packet Complete interrupt for EP */ #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ +#define UDCICR1_IECC BIT(31) /* IntEn - Configuration Change */ +#define UDCICR1_IESOF BIT(30) /* IntEn - Start of Frame */ +#define UDCICR1_IERU BIT(29) /* IntEn - Resume */ +#define UDCICR1_IESU BIT(28) /* IntEn - Suspend */ +#define UDCICR1_IERS BIT(27) /* IntEn - Reset */ #define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */ #define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */ #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ +#define UDCISR1_IRCC BIT(31) /* IntEn - Configuration Change */ +#define UDCISR1_IRSOF BIT(30) /* IntEn - Start of Frame */ +#define UDCISR1_IRRU BIT(29) /* IntEn - Resume */ +#define UDCISR1_IRSU BIT(28) /* IntEn - Suspend */ +#define UDCISR1_IRRS BIT(27) /* IntEn - Reset */ #define UDCFNR 0x40600014 /* UDC Frame Number Register */ #define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ +#define UDCOTGICR_IESF BIT(24) /* OTG SET_FEATURE command recvd */ +#define UDCOTGICR_IEXR BIT(17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEXF BIT(16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40R BIT(9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40F BIT(8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV44R BIT(7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEVV44F BIT(6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */ +#define UDCOTGICR_IESVR BIT(5) /* OTG Session Valid Rising Edge Interrupt Enable */ +#define UDCOTGICR_IESVF BIT(4) /* OTG Session Valid Falling Edge Interrupt Enable */ +#define UDCOTGICR_IESDR BIT(3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */ +#define UDCOTGICR_IESDF BIT(2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEIDR BIT(1) /* OTG ID Change Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEIDF BIT(0) /* OTG ID Change Falling Edge Interrupt Enable */ #define UDCCSN(x) (0x40600100 + ((x) << 2)) #define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ +#define UDCCSR0_SA BIT(7) /* Setup Active */ +#define UDCCSR0_RNE BIT(6) /* Receive FIFO Not Empty */ +#define UDCCSR0_FST BIT(5) /* Force Stall */ +#define UDCCSR0_SST BIT(4) /* Sent Stall */ +#define UDCCSR0_DME BIT(3) /* DMA Enable */ +#define UDCCSR0_FTF BIT(2) /* Flush Transmit FIFO */ +#define UDCCSR0_IPR BIT(1) /* IN Packet Ready */ +#define UDCCSR0_OPC BIT(0) /* OUT Packet Complete */ #define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */ #define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */ @@ -681,17 +681,17 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ #define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */ -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ +#define UDCCSR_DPE BIT(9) /* Data Packet Error */ +#define UDCCSR_FEF BIT(8) /* Flush Endpoint FIFO */ +#define UDCCSR_SP BIT(7) /* Short Packet Control/Status */ +#define UDCCSR_BNE BIT(6) /* Buffer Not Empty (IN endpoints) */ +#define UDCCSR_BNF BIT(6) /* Buffer Not Full (OUT endpoints) */ +#define UDCCSR_FST BIT(5) /* Force STALL */ +#define UDCCSR_SST BIT(4) /* Sent STALL */ +#define UDCCSR_DME BIT(3) /* DMA Enable */ +#define UDCCSR_TRN BIT(2) /* Tx/Rx NAK */ +#define UDCCSR_PC BIT(1) /* Packet Complete */ +#define UDCCSR_FS BIT(0) /* FIFO needs service */ #define UDCBCN(x) (0x40600200 + ((x) << 2)) #define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ @@ -784,11 +784,11 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ +#define UDCCONR_ED BIT(12) /* Endpoint Direction */ #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ #define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ +#define UDCCONR_DE BIT(1) /* Double Buffering Enable */ +#define UDCCONR_EE BIT(0) /* Endpoint Enable */ #define UDC_INT_FIFOERROR (0x2) @@ -904,13 +904,13 @@ typedef void (*ExcpHndlr) (void) ; #define SWCR 0x40900028 /* Stopwatch Count Register */ #define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */ -#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ -#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ +#define RTSR_PICE BIT(15) /* Peridoc interrupt count enable */ +#define RTSR_PIALE BIT(14) /* Peridoc interrupt Alarm enable */ +#define RTSR_PIAL BIT(13) /* Peridoc interrupt Alarm status */ +#define RTSR_HZE BIT(3) /* HZ interrupt enable */ +#define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */ +#define RTSR_HZ BIT(1) /* HZ rising-edge detected */ +#define RTSR_AL BIT(0) /* RTC alarm detected */ /******************************************************************************/ /* @@ -955,19 +955,19 @@ typedef void (*ExcpHndlr) (void) ; #endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ -#define OSSR_M4 (1 << 4) /* Match status channel 4 */ -#define OSSR_M3 (1 << 3) /* Match status channel 3 */ -#define OSSR_M2 (1 << 2) /* Match status channel 2 */ -#define OSSR_M1 (1 << 1) /* Match status channel 1 */ -#define OSSR_M0 (1 << 0) /* Match status channel 0 */ +#define OSSR_M4 BIT(4) /* Match status channel 4 */ +#define OSSR_M3 BIT(3) /* Match status channel 3 */ +#define OSSR_M2 BIT(2) /* Match status channel 2 */ +#define OSSR_M1 BIT(1) /* Match status channel 1 */ +#define OSSR_M0 BIT(0) /* Match status channel 0 */ -#define OWER_WME (1 << 0) /* Watchdog Match Enable */ +#define OWER_WME BIT(0) /* Watchdog Match Enable */ -#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ -#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ -#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ -#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ -#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ +#define OIER_E4 BIT(4) /* Interrupt enable channel 4 */ +#define OIER_E3 BIT(3) /* Interrupt enable channel 3 */ +#define OIER_E2 BIT(2) /* Interrupt enable channel 2 */ +#define OIER_E1 BIT(1) /* Interrupt enable channel 1 */ +#define OIER_E0 BIT(0) /* Interrupt enable channel 0 */ #define OSCR_CLK_FREQ 3250 @@ -991,49 +991,49 @@ typedef void (*ExcpHndlr) (void) ; #define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ #define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ #define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ +#define ACCR_XPDIS BIT(31) +#define ACCR_SPDIS BIT(30) +#define ACCR_13MEND1 BIT(27) +#define ACCR_D0CS BIT(26) +#define ACCR_13MEND2 BIT(21) +#define ACCR_PCCE BIT(11) + +#define CKENA_30_MSL0 BIT(30) /* MSL0 Interface Unit Clock Enable */ +#define CKENA_29_SSP4 BIT(29) /* SSP3 Unit Clock Enable */ +#define CKENA_28_SSP3 BIT(28) /* SSP2 Unit Clock Enable */ +#define CKENA_27_SSP2 BIT(27) /* SSP1 Unit Clock Enable */ +#define CKENA_26_SSP1 BIT(26) /* SSP0 Unit Clock Enable */ +#define CKENA_25_TSI BIT(25) /* TSI Clock Enable */ +#define CKENA_24_AC97 BIT(24) /* AC97 Unit Clock Enable */ +#define CKENA_23_STUART BIT(23) /* STUART Unit Clock Enable */ +#define CKENA_22_FFUART BIT(22) /* FFUART Unit Clock Enable */ +#define CKENA_21_BTUART BIT(21) /* BTUART Unit Clock Enable */ +#define CKENA_20_UDC BIT(20) /* UDC Clock Enable */ +#define CKENA_19_TPM BIT(19) /* TPM Unit Clock Enable */ +#define CKENA_18_USIM1 BIT(18) /* USIM1 Unit Clock Enable */ +#define CKENA_17_USIM0 BIT(17) /* USIM0 Unit Clock Enable */ +#define CKENA_15_CIR BIT(15) /* Consumer IR Clock Enable */ +#define CKENA_14_KEY BIT(14) /* Keypad Controller Clock Enable */ +#define CKENA_13_MMC1 BIT(13) /* MMC1 Clock Enable */ +#define CKENA_12_MMC0 BIT(12) /* MMC0 Clock Enable */ +#define CKENA_11_FLASH BIT(11) /* Boot ROM Clock Enable */ +#define CKENA_10_SRAM BIT(10) /* SRAM Controller Clock Enable */ +#define CKENA_9_SMC BIT(9) /* Static Memory Controller */ +#define CKENA_8_DMC BIT(8) /* Dynamic Memory Controller */ +#define CKENA_7_GRAPHICS BIT(7) /* 2D Graphics Clock Enable */ +#define CKENA_6_USBCLI BIT(6) /* USB Client Unit Clock Enable */ +#define CKENA_4_NAND BIT(4) /* NAND Flash Controller Clock Enable */ +#define CKENA_3_CAMERA BIT(3) /* Camera Interface Clock Enable */ +#define CKENA_2_USBHOST BIT(2) /* USB Host Unit Clock Enable */ +#define CKENA_1_LCD BIT(1) /* LCD Unit Clock Enable */ + +#define CKENB_9_SYSBUS2 BIT(9) /* System bus 2 */ +#define CKENB_8_1WIRE BIT(8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO BIT(7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ BIT(6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C BIT(4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 BIT(1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 BIT(0) /* PWM0 & PWM1 Clock Enable */ #else /* if defined CONFIG_CPU_MONAHANS */ @@ -1042,16 +1042,16 @@ typedef void (*ExcpHndlr) (void) ; #define OSCC 0x41300008 /* Oscillator Configuration Register */ #define CCSR 0x4130000C /* Core Clock Status Register */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ +#define CKEN23_SSP1 BIT(23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC BIT(22) /* Memory Controler */ +#define CKEN21_MSHC BIT(21) /* Memery Stick Host Controller */ +#define CKEN20_IM BIT(20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD BIT(19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM BIT(18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL BIT(17) /* MSL Interface Unit Clock Enable */ +#define CKEN15_PWR_I2C BIT(15) /* PWR_I2C Unit Clock Enable */ +#define CKEN9_OST BIT(9) /* OS Timer Unit Clock Enable */ +#define CKEN4_SSP3 BIT(4) /* SSP3 Unit Clock Enable */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ #if !defined(CONFIG_CPU_PXA27X) @@ -1059,35 +1059,35 @@ typedef void (*ExcpHndlr) (void) ; #endif #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ +#define CKEN24_CAMERA BIT(24) /* Camera Interface Clock Enable */ +#define CKEN23_SSP1 BIT(23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC BIT(22) /* Memory Controller Clock Enable */ +#define CKEN21_MEMSTK BIT(21) /* Memory Stick Host Controller */ +#define CKEN20_IM BIT(20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD BIT(19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM BIT(18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL BIT(17) /* MSL Unit Clock Enable */ +#define CKEN16_LCD BIT(16) /* LCD Unit Clock Enable */ +#define CKEN15_PWRI2C BIT(15) /* PWR I2C Unit Clock Enable */ +#define CKEN14_I2C BIT(14) /* I2C Unit Clock Enable */ +#define CKEN13_FICP BIT(13) /* FICP Unit Clock Enable */ +#define CKEN12_MMC BIT(12) /* MMC Unit Clock Enable */ +#define CKEN11_USB BIT(11) /* USB Unit Clock Enable */ #if defined(CONFIG_CPU_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ +#define CKEN10_USBHOST BIT(10) /* USB Host Unit Clock Enable */ +#define CKEN24_CAMERA BIT(24) /* Camera Unit Clock Enable */ #endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ +#define CKEN8_I2S BIT(8) /* I2S Unit Clock Enable */ +#define CKEN7_BTUART BIT(7) /* BTUART Unit Clock Enable */ +#define CKEN6_FFUART BIT(6) /* FFUART Unit Clock Enable */ +#define CKEN5_STUART BIT(5) /* STUART Unit Clock Enable */ +#define CKEN3_SSP BIT(3) /* SSP Unit Clock Enable */ +#define CKEN2_AC97 BIT(2) /* AC97 Unit Clock Enable */ +#define CKEN1_PWM1 BIT(1) /* PWM1 Clock Enable */ +#define CKEN0_PWM0 BIT(0) /* PWM0 Clock Enable */ + +#define OSCC_OON BIT(1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK BIT(0) /* 32.768kHz OOK (read-only bit) */ #if !defined(CONFIG_CPU_PXA27X) #define CCCR_L09 (0x1F) @@ -2034,22 +2034,22 @@ typedef void (*ExcpHndlr) (void) ; #define PCFR_FVC (0x1 << 10) #define PCFR_PI2C_EN (0x1 << 6) -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ +#define PSSR_OTGPH BIT(6) /* OTG Peripheral control Hold */ +#define PSSR_RDH BIT(5) /* Read Disable Hold */ +#define PSSR_PH BIT(4) /* Peripheral Control Hold */ +#define PSSR_VFS BIT(2) /* VDD Fault Status */ +#define PSSR_BFS BIT(1) /* Battery Fault Status */ +#define PSSR_SSS BIT(0) /* Software Sleep Status */ -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ +#define PCFR_DS BIT(3) /* Deep Sleep Mode */ +#define PCFR_FS BIT(2) /* Float Static Chip Selects */ +#define PCFR_FP BIT(1) /* Float PCMCIA controls */ +#define PCFR_OPDE BIT(0) /* 3.6864 MHz oscillator power-down enable */ -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ +#define RCSR_GPR BIT(3) /* GPIO Reset */ +#define RCSR_SMR BIT(2) /* Sleep Mode */ +#define RCSR_WDR BIT(1) /* Watchdog Reset */ +#define RCSR_HWR BIT(0) /* Hardware Reset */ #endif /* CONFIG_CPU_MONAHANS */ @@ -2109,26 +2109,26 @@ typedef void (*ExcpHndlr) (void) ; #define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ #define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ +#define LCCR0_ENB BIT(0) /* LCD Controller enable */ +#define LCCR0_CMS BIT(1) /* Color = 0, Monochrome = 1 */ +#define LCCR0_SDS BIT(2) /* Single Panel = 0, Dual Panel = 1 */ +#define LCCR0_LDM BIT(3) /* LCD Disable Done Mask */ +#define LCCR0_SFM BIT(4) /* Start of frame mask */ +#define LCCR0_IUM BIT(5) /* Input FIFO underrun mask */ +#define LCCR0_EFM BIT(6) /* End of Frame mask */ +#define LCCR0_PAS BIT(7) /* Passive = 0, Active = 1 */ +#define LCCR0_BLE BIT(8) /* Little Endian = 0, Big Endian = 1 */ +#define LCCR0_DPD BIT(9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ +#define LCCR0_DIS BIT(10) /* LCD Disable */ +#define LCCR0_QDM BIT(11) /* LCD Quick Disable mask */ #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ #define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ +#define LCCR0_BM BIT(20) /* Branch mask */ +#define LCCR0_OUM BIT(21) /* Output FIFO underrun mask */ #if defined(CONFIG_CPU_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ +#define LCCR0_LCDT BIT(22) /* LCD Panel Type */ +#define LCCR0_RDSTM BIT(23) /* Read Status Interrupt Mask */ +#define LCCR0_CMDIM BIT(24) /* Command Interrupt Mask */ #endif #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ @@ -2177,14 +2177,14 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ #define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ +#define LCCR3_VSP BIT(20) /* vertical sync polarity */ +#define LCCR3_HSP BIT(21) /* horizontal sync polarity */ +#define LCCR3_PCP BIT(22) /* pixel clock polarity */ +#define LCCR3_OEP BIT(23) /* output enable polarity */ +#define LCCR3_DPC BIT(27) /* double pixel clock mode */ #define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) +#define LCCR3_PDFOR_1 BIT(30) #define LCCR3_PDFOR_2 (2 << 30) #define LCCR3_PDFOR_3 (3 << 30) @@ -2211,49 +2211,49 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ /* active Low */ -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +#define LCSR0_LDD BIT(0) /* LCD Disable Done */ +#define LCSR0_SOF BIT(1) /* Start of frame */ +#define LCSR0_BER BIT(2) /* Bus error */ +#define LCSR0_ABC BIT(3) /* AC Bias count */ +#define LCSR0_IUL BIT(4) /* input FIFO underrun Lower panel */ +#define LCSR0_IUU BIT(5) /* input FIFO underrun Upper panel */ +#define LCSR0_OU BIT(6) /* output FIFO underrun */ +#define LCSR0_QD BIT(7) /* quick disable */ +#define LCSR0_EOF0 BIT(8) /* end of frame */ +#define LCSR0_BS BIT(9) /* branch status */ +#define LCSR0_SINT BIT(10) /* subsequent interrupt */ + +#define LCSR1_SOF1 BIT(0) +#define LCSR1_SOF2 BIT(1) +#define LCSR1_SOF3 BIT(2) +#define LCSR1_SOF4 BIT(3) +#define LCSR1_SOF5 BIT(4) +#define LCSR1_SOF6 BIT(5) + +#define LCSR1_EOF1 BIT(8) +#define LCSR1_EOF2 BIT(9) +#define LCSR1_EOF3 BIT(10) +#define LCSR1_EOF4 BIT(11) +#define LCSR1_EOF5 BIT(12) +#define LCSR1_EOF6 BIT(13) + +#define LCSR1_BS1 BIT(16) +#define LCSR1_BS2 BIT(17) +#define LCSR1_BS3 BIT(18) +#define LCSR1_BS4 BIT(19) +#define LCSR1_BS5 BIT(20) +#define LCSR1_BS6 BIT(21) + +#define LCSR1_IU2 BIT(25) +#define LCSR1_IU3 BIT(26) +#define LCSR1_IU4 BIT(27) +#define LCSR1_IU5 BIT(28) +#define LCSR1_IU6 BIT(29) + +#define LDCMD_PAL BIT(26) /* instructs DMA to load palette buffer */ #if defined(CONFIG_CPU_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) +#define LDCMD_SOFINT BIT(22) +#define LDCMD_EOFINT BIT(21) #endif /* @@ -2400,7 +2400,7 @@ typedef void (*ExcpHndlr) (void) ; #define MCMEM(s) MCMEM0 #define MCATT(s) MCATT0 #define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ +#define MECR_CIT BIT(1)/* Card Is There: 0 -> no card, 1 -> card inserted */ /* Maximum values for NAND Interface Timing Registers in DFC clock * periods */ @@ -2465,22 +2465,22 @@ typedef void (*ExcpHndlr) (void) ; #define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ #define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ -#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ -#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ +#define MDREFR_ALTREFA BIT(31) /* Exiting Alternate Bus Master Mode Refresh Control */ +#define MDREFR_ALTREFB BIT(30) /* Entering Alternate Bus Master Mode Refresh Control */ +#define MDREFR_K0DB4 BIT(29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE BIT(25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE BIT(24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE BIT(23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH BIT(22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD BIT(20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 BIT(19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN BIT(18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 BIT(17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN BIT(16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN BIT(15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 BIT(14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN BIT(13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN BIT(12) /* SDCKE0 Level Control/Status */ #if defined(CONFIG_CPU_PXA27X) @@ -2619,7 +2619,7 @@ typedef void (*ExcpHndlr) (void) ; #define KPAS_SO (0x1 << 31) #define KPASMKPx_SO (0x1 << 31) -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ +#define GPIO113_BIT BIT(17)/* GPIO113 in GPSR, GPCR, bit 17 */ #define PSLR 0x40F00034 #define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ #define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h index 1b18eea..36a24fb 100644 --- a/arch/arm/include/asm/arch-pxa/regs-mmc.h +++ b/arch/arm/include/asm/arch-pxa/regs-mmc.h @@ -34,22 +34,22 @@ struct pxa_mmc_regs { }; /* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (1 << 0) -#define MMC_STRPCL_START_CLK (1 << 1) +#define MMC_STRPCL_STOP_CLK BIT(0) +#define MMC_STRPCL_START_CLK BIT(1) /* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (1 << 13) -#define MMC_STAT_PRG_DONE (1 << 12) -#define MMC_STAT_DATA_TRAN_DONE (1 << 11) -#define MMC_STAT_CLK_EN (1 << 8) -#define MMC_STAT_RECV_FIFO_FULL (1 << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) -#define MMC_STAT_RES_CRC_ERROR (1 << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) -#define MMC_STAT_CRC_READ_ERROR (1 << 3) -#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) -#define MMC_STAT_READ_TIME_OUT (1 << 0) +#define MMC_STAT_END_CMD_RES BIT(13) +#define MMC_STAT_PRG_DONE BIT(12) +#define MMC_STAT_DATA_TRAN_DONE BIT(11) +#define MMC_STAT_CLK_EN BIT(8) +#define MMC_STAT_RECV_FIFO_FULL BIT(7) +#define MMC_STAT_XMIT_FIFO_EMPTY BIT(6) +#define MMC_STAT_RES_CRC_ERROR BIT(5) +#define MMC_STAT_SPI_READ_ERROR_TOKEN BIT(4) +#define MMC_STAT_CRC_READ_ERROR BIT(3) +#define MMC_STAT_CRC_WRITE_ERROR BIT(2) +#define MMC_STAT_TIME_OUT_RESPONSE BIT(1) +#define MMC_STAT_READ_TIME_OUT BIT(0) /* MMC_CLKRT */ #define MMC_CLKRT_20MHZ 0 @@ -61,20 +61,20 @@ struct pxa_mmc_regs { #define MMC_CLKRT_0_3125MHZ 6 /* MMC_SPI */ -#define MMC_SPI_EN (1 << 0) -#define MMC_SPI_CS_EN (1 << 2) -#define MMC_SPI_CS_ADDRESS (1 << 3) -#define MMC_SPI_CRC_ON (1 << 1) +#define MMC_SPI_EN BIT(0) +#define MMC_SPI_CS_EN BIT(2) +#define MMC_SPI_CS_ADDRESS BIT(3) +#define MMC_SPI_CRC_ON BIT(1) /* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (1 << 8) -#define MMC_CMDAT_MMC_DMA_EN (1 << 7) -#define MMC_CMDAT_INIT (1 << 6) -#define MMC_CMDAT_BUSY (1 << 5) +#define MMC_CMDAT_SD_4DAT BIT(8) +#define MMC_CMDAT_MMC_DMA_EN BIT(7) +#define MMC_CMDAT_INIT BIT(6) +#define MMC_CMDAT_BUSY BIT(5) #define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) -#define MMC_CMDAT_STREAM (1 << 4) -#define MMC_CMDAT_WRITE (1 << 3) -#define MMC_CMDAT_DATA_EN (1 << 2) +#define MMC_CMDAT_STREAM BIT(4) +#define MMC_CMDAT_WRITE BIT(3) +#define MMC_CMDAT_DATA_EN BIT(2) #define MMC_CMDAT_R0 0 #define MMC_CMDAT_R1 1 #define MMC_CMDAT_R2 2 @@ -90,27 +90,27 @@ struct pxa_mmc_regs { #define MMC_BLK_LEN_MAX_MASK 0x3ff /* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) +#define MMC_PRTBUF_BUF_PART_FULL BIT(0) /* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_MASK_CLK_IS_OFF (1 << 4) -#define MMC_I_MASK_STOP_CMD (1 << 3) -#define MMC_I_MASK_END_CMD_RES (1 << 2) -#define MMC_I_MASK_PRG_DONE (1 << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) +#define MMC_I_MASK_TXFIFO_WR_REQ BIT(6) +#define MMC_I_MASK_RXFIFO_RD_REQ BIT(5) +#define MMC_I_MASK_CLK_IS_OFF BIT(4) +#define MMC_I_MASK_STOP_CMD BIT(3) +#define MMC_I_MASK_END_CMD_RES BIT(2) +#define MMC_I_MASK_PRG_DONE BIT(1) +#define MMC_I_MASK_DATA_TRAN_DONE BIT(0) #define MMC_I_MASK_ALL 0x7f /* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_REG_CLK_IS_OFF (1 << 4) -#define MMC_I_REG_STOP_CMD (1 << 3) -#define MMC_I_REG_END_CMD_RES (1 << 2) -#define MMC_I_REG_PRG_DONE (1 << 1) -#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) +#define MMC_I_REG_TXFIFO_WR_REQ BIT(6) +#define MMC_I_REG_RXFIFO_RD_REQ BIT(5) +#define MMC_I_REG_CLK_IS_OFF BIT(4) +#define MMC_I_REG_STOP_CMD BIT(3) +#define MMC_I_REG_END_CMD_RES BIT(2) +#define MMC_I_REG_PRG_DONE BIT(1) +#define MMC_I_REG_DATA_TRAN_DONE BIT(0) /* MMC_CMD */ #define MMC_CMD_INDEX_MAX 0x6f diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h index 313a691..1f08605 100644 --- a/arch/arm/include/asm/arch-pxa/regs-uart.h +++ b/arch/arm/include/asm/arch-pxa/regs-uart.h @@ -34,63 +34,63 @@ struct pxa_uart_regs { uint32_t isr; }; -#define IER_DMAE (1 << 7) -#define IER_UUE (1 << 6) -#define IER_NRZE (1 << 5) -#define IER_RTIOE (1 << 4) -#define IER_MIE (1 << 3) -#define IER_RLSE (1 << 2) -#define IER_TIE (1 << 1) -#define IER_RAVIE (1 << 0) +#define IER_DMAE BIT(7) +#define IER_UUE BIT(6) +#define IER_NRZE BIT(5) +#define IER_RTIOE BIT(4) +#define IER_MIE BIT(3) +#define IER_RLSE BIT(2) +#define IER_TIE BIT(1) +#define IER_RAVIE BIT(0) -#define IIR_FIFOES1 (1 << 7) -#define IIR_FIFOES0 (1 << 6) -#define IIR_TOD (1 << 3) -#define IIR_IID2 (1 << 2) -#define IIR_IID1 (1 << 1) -#define IIR_IP (1 << 0) +#define IIR_FIFOES1 BIT(7) +#define IIR_FIFOES0 BIT(6) +#define IIR_TOD BIT(3) +#define IIR_IID2 BIT(2) +#define IIR_IID1 BIT(1) +#define IIR_IP BIT(0) -#define FCR_ITL2 (1 << 7) -#define FCR_ITL1 (1 << 6) -#define FCR_RESETTF (1 << 2) -#define FCR_RESETRF (1 << 1) -#define FCR_TRFIFOE (1 << 0) +#define FCR_ITL2 BIT(7) +#define FCR_ITL1 BIT(6) +#define FCR_RESETTF BIT(2) +#define FCR_RESETRF BIT(1) +#define FCR_TRFIFOE BIT(0) #define FCR_ITL_1 0 #define FCR_ITL_8 (FCR_ITL1) #define FCR_ITL_16 (FCR_ITL2) #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) -#define LCR_DLAB (1 << 7) -#define LCR_SB (1 << 6) -#define LCR_STKYP (1 << 5) -#define LCR_EPS (1 << 4) -#define LCR_PEN (1 << 3) -#define LCR_STB (1 << 2) -#define LCR_WLS1 (1 << 1) -#define LCR_WLS0 (1 << 0) +#define LCR_DLAB BIT(7) +#define LCR_SB BIT(6) +#define LCR_STKYP BIT(5) +#define LCR_EPS BIT(4) +#define LCR_PEN BIT(3) +#define LCR_STB BIT(2) +#define LCR_WLS1 BIT(1) +#define LCR_WLS0 BIT(0) -#define LSR_FIFOE (1 << 7) -#define LSR_TEMT (1 << 6) -#define LSR_TDRQ (1 << 5) -#define LSR_BI (1 << 4) -#define LSR_FE (1 << 3) -#define LSR_PE (1 << 2) -#define LSR_OE (1 << 1) -#define LSR_DR (1 << 0) +#define LSR_FIFOE BIT(7) +#define LSR_TEMT BIT(6) +#define LSR_TDRQ BIT(5) +#define LSR_BI BIT(4) +#define LSR_FE BIT(3) +#define LSR_PE BIT(2) +#define LSR_OE BIT(1) +#define LSR_DR BIT(0) -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) -#define MCR_OUT1 (1 << 2) -#define MCR_RTS (1 << 1) -#define MCR_DTR (1 << 0) +#define MCR_LOOP BIT(4) +#define MCR_OUT2 BIT(3) +#define MCR_OUT1 BIT(2) +#define MCR_RTS BIT(1) +#define MCR_DTR BIT(0) -#define MSR_DCD (1 << 7) -#define MSR_RI (1 << 6) -#define MSR_DSR (1 << 5) -#define MSR_CTS (1 << 4) -#define MSR_DDCD (1 << 3) -#define MSR_TERI (1 << 2) -#define MSR_DDSR (1 << 1) -#define MSR_DCTS (1 << 0) +#define MSR_DCD BIT(7) +#define MSR_RI BIT(6) +#define MSR_DSR BIT(5) +#define MSR_CTS BIT(4) +#define MSR_DDCD BIT(3) +#define MSR_TERI BIT(2) +#define MSR_DDSR BIT(1) +#define MSR_DCTS BIT(0) #endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h b/arch/arm/include/asm/arch-pxa/regs-usb.h index 90ffbf4..3335ee3 100644 --- a/arch/arm/include/asm/arch-pxa/regs-usb.h +++ b/arch/arm/include/asm/arch-pxa/regs-usb.h @@ -74,74 +74,74 @@ struct pxa25x_udc_regs { #define PXA25X_UDC_BASE 0x40600000 -#define UDCCR_UDE (1 << 0) -#define UDCCR_UDA (1 << 1) -#define UDCCR_RSM (1 << 2) -#define UDCCR_RESIR (1 << 3) -#define UDCCR_SUSIR (1 << 4) -#define UDCCR_SRM (1 << 5) -#define UDCCR_RSTIR (1 << 6) -#define UDCCR_REM (1 << 7) +#define UDCCR_UDE BIT(0) +#define UDCCR_UDA BIT(1) +#define UDCCR_RSM BIT(2) +#define UDCCR_RESIR BIT(3) +#define UDCCR_SUSIR BIT(4) +#define UDCCR_SRM BIT(5) +#define UDCCR_RSTIR BIT(6) +#define UDCCR_REM BIT(7) /* Bulk IN endpoint 1/6/11 */ -#define UDCCS_BI_TSP (1 << 7) -#define UDCCS_BI_FST (1 << 5) -#define UDCCS_BI_SST (1 << 4) -#define UDCCS_BI_TUR (1 << 3) -#define UDCCS_BI_FTF (1 << 2) -#define UDCCS_BI_TPC (1 << 1) -#define UDCCS_BI_TFS (1 << 0) +#define UDCCS_BI_TSP BIT(7) +#define UDCCS_BI_FST BIT(5) +#define UDCCS_BI_SST BIT(4) +#define UDCCS_BI_TUR BIT(3) +#define UDCCS_BI_FTF BIT(2) +#define UDCCS_BI_TPC BIT(1) +#define UDCCS_BI_TFS BIT(0) /* Bulk OUT endpoint 2/7/12 */ -#define UDCCS_BO_RSP (1 << 7) -#define UDCCS_BO_RNE (1 << 6) -#define UDCCS_BO_FST (1 << 5) -#define UDCCS_BO_SST (1 << 4) -#define UDCCS_BO_DME (1 << 3) -#define UDCCS_BO_RPC (1 << 1) -#define UDCCS_BO_RFS (1 << 0) +#define UDCCS_BO_RSP BIT(7) +#define UDCCS_BO_RNE BIT(6) +#define UDCCS_BO_FST BIT(5) +#define UDCCS_BO_SST BIT(4) +#define UDCCS_BO_DME BIT(3) +#define UDCCS_BO_RPC BIT(1) +#define UDCCS_BO_RFS BIT(0) /* Isochronous OUT endpoint 4/9/14 */ -#define UDCCS_IO_RSP (1 << 7) -#define UDCCS_IO_RNE (1 << 6) -#define UDCCS_IO_DME (1 << 3) -#define UDCCS_IO_ROF (1 << 2) -#define UDCCS_IO_RPC (1 << 1) -#define UDCCS_IO_RFS (1 << 0) +#define UDCCS_IO_RSP BIT(7) +#define UDCCS_IO_RNE BIT(6) +#define UDCCS_IO_DME BIT(3) +#define UDCCS_IO_ROF BIT(2) +#define UDCCS_IO_RPC BIT(1) +#define UDCCS_IO_RFS BIT(0) /* Control endpoint 0 */ -#define UDCCS0_OPR (1 << 0) -#define UDCCS0_IPR (1 << 1) -#define UDCCS0_FTF (1 << 2) -#define UDCCS0_DRWF (1 << 3) -#define UDCCS0_SST (1 << 4) -#define UDCCS0_FST (1 << 5) -#define UDCCS0_RNE (1 << 6) -#define UDCCS0_SA (1 << 7) - -#define UICR0_IM0 (1 << 0) - -#define USIR0_IR0 (1 << 0) -#define USIR0_IR1 (1 << 1) -#define USIR0_IR2 (1 << 2) -#define USIR0_IR3 (1 << 3) -#define USIR0_IR4 (1 << 4) -#define USIR0_IR5 (1 << 5) -#define USIR0_IR6 (1 << 6) -#define USIR0_IR7 (1 << 7) - -#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ -#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ +#define UDCCS0_OPR BIT(0) +#define UDCCS0_IPR BIT(1) +#define UDCCS0_FTF BIT(2) +#define UDCCS0_DRWF BIT(3) +#define UDCCS0_SST BIT(4) +#define UDCCS0_FST BIT(5) +#define UDCCS0_RNE BIT(6) +#define UDCCS0_SA BIT(7) + +#define UICR0_IM0 BIT(0) + +#define USIR0_IR0 BIT(0) +#define USIR0_IR1 BIT(1) +#define USIR0_IR2 BIT(2) +#define USIR0_IR3 BIT(3) +#define USIR0_IR4 BIT(4) +#define USIR0_IR5 BIT(5) +#define USIR0_IR6 BIT(6) +#define USIR0_IR7 BIT(7) + +#define UDCCFR_AREN BIT(7) /* ACK response enable (now) */ +#define UDCCFR_ACM BIT(2) /* ACK control mode (wait for AREN) */ /* * Intel(R) PXA255 Processor Specification, September 2003 (page 31) * define new "must be one" bits in UDCCFR (see Table 12-13.) */ #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) -#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ -#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ -#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ -#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ -#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ +#define UFNRH_SIR BIT(7) /* SOF interrupt request */ +#define UFNRH_SIM BIT(6) /* SOF interrupt mask */ +#define UFNRH_IPE14 BIT(5) /* ISO packet error, ep14 */ +#define UFNRH_IPE9 BIT(4) /* ISO packet error, ep9 */ +#define UFNRH_IPE4 BIT(3) /* ISO packet error, ep4 */ #endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h index 463654e..dcbb800 100644 --- a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h @@ -17,59 +17,59 @@ #define EHCI_USBCMD (EHCI_OFFSET + 0x0020) /* USBCTR */ -#define DIRPD (1 << 8) -#define PLL_RST (1 << 2) -#define PCICLK_MASK (1 << 1) -#define USBH_RST (1 << 0) +#define DIRPD BIT(8) +#define PLL_RST BIT(2) +#define PCICLK_MASK BIT(1) +#define USBH_RST BIT(0) /* CMND_STS */ -#define SERREN (1 << 8) -#define PERREN (1 << 6) -#define MASTEREN (1 << 2) -#define MEMEN (1 << 1) +#define SERREN BIT(8) +#define PERREN BIT(6) +#define MASTEREN BIT(2) +#define MEMEN BIT(1) /* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ -#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) +#define PCIAHB_WIN_PREFETCH (BIT(1)|BIT(0)) /* AHBPCI_WIN1_CTR */ -#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define PCIWIN1_PCICMD (BIT(3)|BIT(1)) #define AHB_CFG_AHBPCI 0x40000000 #define AHB_CFG_HOST 0x80000000 /* AHBPCI_WIN2_CTR */ -#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) +#define PCIWIN2_PCICMD (BIT(2)|BIT(1)) /* PCI_INT_ENABLE */ -#define USBH_PMEEN (1 << 19) -#define USBH_INTBEN (1 << 17) -#define USBH_INTAEN (1 << 16) +#define USBH_PMEEN BIT(19) +#define USBH_INTBEN BIT(17) +#define USBH_INTAEN BIT(16) /* AHB_BUS_CTR */ -#define SMODE_READY_CTR (1 << 17) -#define SMODE_READ_BURST (1 << 16) -#define MMODE_HBUSREQ (1 << 7) -#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) -#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) -#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) -#define MMODE_WR_INCR (1 << 2) -#define MMODE_BYTE_BURST (1 << 1) -#define MMODE_HTRANS (1 << 0) +#define SMODE_READY_CTR BIT(17) +#define SMODE_READ_BURST BIT(16) +#define MMODE_HBUSREQ BIT(7) +#define MMODE_BOUNDARY (BIT(6)|BIT(5)) +#define MMODE_BURST_WIDTH (BIT(4)|BIT(3)) +#define MMODE_SINGLE_MODE (BIT(4)|BIT(3)) +#define MMODE_WR_INCR BIT(2) +#define MMODE_BYTE_BURST BIT(1) +#define MMODE_HTRANS BIT(0) /* PCI_ARBITER_CTR */ #define PCIBUS_PARK_TIMER 0x00FF0000 #define PCIBUS_PARK_TIMER_SET 0x00070000 -#define PCIBP_MODE (1 << 12) -#define PCIREQ7 (1 << 7) -#define PCIREQ6 (1 << 6) -#define PCIREQ5 (1 << 5) -#define PCIREQ4 (1 << 4) -#define PCIREQ3 (1 << 3) -#define PCIREQ2 (1 << 2) -#define PCIREQ1 (1 << 1) -#define PCIREQ0 (1 << 0) +#define PCIBP_MODE BIT(12) +#define PCIREQ7 BIT(7) +#define PCIREQ6 BIT(6) +#define PCIREQ5 BIT(5) +#define PCIREQ4 BIT(4) +#define PCIREQ3 BIT(3) +#define PCIREQ2 BIT(2) +#define PCIREQ1 BIT(1) +#define PCIREQ0 BIT(0) #define SMSTPCR7 0xE615014C -#define SMSTPCR703 (1 << 3) +#define SMSTPCR703 BIT(3) /* Init AHB master and slave functions of the host logic */ #define AHB_BUS_CTR_INIT \ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h index 9d447ab..97dfc18 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h @@ -22,9 +22,9 @@ /* * MD_CKx pin */ -#define MD_CK2 (1 << 2) -#define MD_CK1 (1 << 1) -#define MD_CK0 (1 << 0) +#define MD_CK2 BIT(2) +#define MD_CK1 BIT(1) +#define MD_CK0 BIT(0) /* * Pin Function Controller: diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h index 057bf3f..e6cbde4 100644 --- a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h +++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h @@ -54,48 +54,48 @@ #define SDHI_SD_SWITCH 0x1C06 /* SDHI_PORTSEL */ -#define USE_1PORT (1 << 8) /* 1 port */ +#define USE_1PORT BIT(8) /* 1 port */ /* SDHI_ARG */ #define ARG0_MASK 0x0000ffff #define ARG1_MASK 0x0000ffff /* SDHI_STOP */ -#define STOP_SEC_ENABLE (1 << 8) +#define STOP_SEC_ENABLE BIT(8) /* SDHI_INFO1 */ -#define INFO1_RESP_END (1 << 0) -#define INFO1_ACCESS_END (1 << 2) -#define INFO1_CARD_RE (1 << 3) -#define INFO1_CARD_IN (1 << 4) -#define INFO1_ISD0CD (1 << 5) -#define INFO1_WRITE_PRO (1 << 7) -#define INFO1_DATA3_CARD_RE (1 << 8) -#define INFO1_DATA3_CARD_IN (1 << 9) -#define INFO1_DATA3 (1 << 10) +#define INFO1_RESP_END BIT(0) +#define INFO1_ACCESS_END BIT(2) +#define INFO1_CARD_RE BIT(3) +#define INFO1_CARD_IN BIT(4) +#define INFO1_ISD0CD BIT(5) +#define INFO1_WRITE_PRO BIT(7) +#define INFO1_DATA3_CARD_RE BIT(8) +#define INFO1_DATA3_CARD_IN BIT(9) +#define INFO1_DATA3 BIT(10) /* SDHI_INFO2 */ -#define INFO2_CMD_ERROR (1 << 0) -#define INFO2_CRC_ERROR (1 << 1) -#define INFO2_END_ERROR (1 << 2) -#define INFO2_TIMEOUT (1 << 3) -#define INFO2_BUF_ILL_WRITE (1 << 4) -#define INFO2_BUF_ILL_READ (1 << 5) -#define INFO2_RESP_TIMEOUT (1 << 6) -#define INFO2_SDDAT0 (1 << 7) -#define INFO2_BRE_ENABLE (1 << 8) -#define INFO2_BWE_ENABLE (1 << 9) -#define INFO2_CBUSY (1 << 14) -#define INFO2_ILA (1 << 15) +#define INFO2_CMD_ERROR BIT(0) +#define INFO2_CRC_ERROR BIT(1) +#define INFO2_END_ERROR BIT(2) +#define INFO2_TIMEOUT BIT(3) +#define INFO2_BUF_ILL_WRITE BIT(4) +#define INFO2_BUF_ILL_READ BIT(5) +#define INFO2_RESP_TIMEOUT BIT(6) +#define INFO2_SDDAT0 BIT(7) +#define INFO2_BRE_ENABLE BIT(8) +#define INFO2_BWE_ENABLE BIT(9) +#define INFO2_CBUSY BIT(14) +#define INFO2_ILA BIT(15) #define INFO2_ALL_ERR (0x807f) /* SDHI_INFO1_MASK */ -#define INFO1M_RESP_END (1 << 0) -#define INFO1M_ACCESS_END (1 << 2) -#define INFO1M_CARD_RE (1 << 3) -#define INFO1M_CARD_IN (1 << 4) -#define INFO1M_DATA3_CARD_RE (1 << 8) -#define INFO1M_DATA3_CARD_IN (1 << 9) +#define INFO1M_RESP_END BIT(0) +#define INFO1M_ACCESS_END BIT(2) +#define INFO1M_CARD_RE BIT(3) +#define INFO1M_CARD_IN BIT(4) +#define INFO1M_DATA3_CARD_RE BIT(8) +#define INFO1M_DATA3_CARD_IN BIT(9) #define INFO1M_ALL (0xffff) #define INFO1M_SET (INFO1M_RESP_END | \ INFO1M_ACCESS_END | \ @@ -103,58 +103,58 @@ INFO1M_DATA3_CARD_IN) /* SDHI_INFO2_MASK */ -#define INFO2M_CMD_ERROR (1 << 0) -#define INFO2M_CRC_ERROR (1 << 1) -#define INFO2M_END_ERROR (1 << 2) -#define INFO2M_TIMEOUT (1 << 3) -#define INFO2M_BUF_ILL_WRITE (1 << 4) -#define INFO2M_BUF_ILL_READ (1 << 5) -#define INFO2M_RESP_TIMEOUT (1 << 6) -#define INFO2M_BRE_ENABLE (1 << 8) -#define INFO2M_BWE_ENABLE (1 << 9) -#define INFO2M_ILA (1 << 15) +#define INFO2M_CMD_ERROR BIT(0) +#define INFO2M_CRC_ERROR BIT(1) +#define INFO2M_END_ERROR BIT(2) +#define INFO2M_TIMEOUT BIT(3) +#define INFO2M_BUF_ILL_WRITE BIT(4) +#define INFO2M_BUF_ILL_READ BIT(5) +#define INFO2M_RESP_TIMEOUT BIT(6) +#define INFO2M_BRE_ENABLE BIT(8) +#define INFO2M_BWE_ENABLE BIT(9) +#define INFO2M_ILA BIT(15) #define INFO2M_ALL (0xffff) #define INFO2M_ALL_ERR (0x807f) /* SDHI_CLK_CTRL */ -#define CLK_ENABLE (1 << 8) +#define CLK_ENABLE BIT(8) /* SDHI_OPTION */ -#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */ +#define OPT_BUS_WIDTH_1 BIT(15) /* bus width = 1 bit */ /* SDHI_ERR_STS1 */ -#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ - (1 << 8) | (1 << 5)) -#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \ - (1 << 1) | (1 << 0)) +#define ERR_STS1_CRC_ERROR (BIT(11) | BIT(10) | BIT(9) | \ + BIT(8) | BIT(5)) +#define ERR_STS1_CMD_ERROR (BIT(4) | BIT(3) | BIT(2) | \ + BIT(1) | BIT(0)) /* SDHI_ERR_STS2 */ -#define ERR_STS2_RES_TIMEOUT (1 << 0) -#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1)) -#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \ - (1 << 3) | (1 << 2) | (1 << 1) | \ - (1 << 0)) +#define ERR_STS2_RES_TIMEOUT BIT(0) +#define ERR_STS2_RES_STOP_TIMEOUT (BIT(0) | BIT(1)) +#define ERR_STS2_SYS_ERROR (BIT(6) | BIT(5) | BIT(4) | \ + BIT(3) | BIT(2) | BIT(1) | \ + BIT(0)) /* SDHI_SDIO_MODE */ -#define SDIO_MODE_ON (1 << 0) +#define SDIO_MODE_ON BIT(0) #define SDIO_MODE_OFF (0 << 0) /* SDHI_SDIO_INFO1 */ -#define SDIO_INFO1_IOIRQ (1 << 0) -#define SDIO_INFO1_EXPUB52 (1 << 14) -#define SDIO_INFO1_EXWT (1 << 15) +#define SDIO_INFO1_IOIRQ BIT(0) +#define SDIO_INFO1_EXPUB52 BIT(14) +#define SDIO_INFO1_EXWT BIT(15) /* SDHI_SDIO_INFO1_MASK */ -#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2)) -#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \ - (1 << 1) | (1 << 0)) +#define SDIO_INFO1M_CLEAR (BIT(1) | BIT(2)) +#define SDIO_INFO1M_ON (BIT(15) | BIT(14) | BIT(2) | \ + BIT(1) | BIT(0)) /* SDHI_EXT_SWAP */ -#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */ +#define SET_SWAP (BIT(6) | BIT(7)) /* SWAP */ /* SDHI_SOFT_RST */ #define SOFT_RST_ON (0 << 0) -#define SOFT_RST_OFF (1 << 0) +#define SOFT_RST_OFF BIT(0) #define CLKDEV_SD_DATA 25000000 /* 25 MHz */ #define CLKDEV_HS_DATA 50000000 /* 50 MHz */ diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h index 9811644..ad1a71b 100644 --- a/arch/arm/include/asm/arch-s3c24x0/iomux.h +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h @@ -12,28 +12,28 @@ enum s3c2440_iomux_func { /* PORT A */ IOMUXA_ADDR0 = 1, - IOMUXA_ADDR16 = (1 << 1), - IOMUXA_ADDR17 = (1 << 2), - IOMUXA_ADDR18 = (1 << 3), - IOMUXA_ADDR19 = (1 << 4), - IOMUXA_ADDR20 = (1 << 5), - IOMUXA_ADDR21 = (1 << 6), - IOMUXA_ADDR22 = (1 << 7), - IOMUXA_ADDR23 = (1 << 8), - IOMUXA_ADDR24 = (1 << 9), - IOMUXA_ADDR25 = (1 << 10), - IOMUXA_ADDR26 = (1 << 11), - IOMUXA_nGCS1 = (1 << 12), - IOMUXA_nGCS2 = (1 << 13), - IOMUXA_nGCS3 = (1 << 14), - IOMUXA_nGCS4 = (1 << 15), - IOMUXA_nGCS5 = (1 << 16), - IOMUXA_CLE = (1 << 17), - IOMUXA_ALE = (1 << 18), - IOMUXA_nFWE = (1 << 19), - IOMUXA_nFRE = (1 << 20), - IOMUXA_nRSTOUT = (1 << 21), - IOMUXA_nFCE = (1 << 22), + IOMUXA_ADDR16 = BIT(1), + IOMUXA_ADDR17 = BIT(2), + IOMUXA_ADDR18 = BIT(3), + IOMUXA_ADDR19 = BIT(4), + IOMUXA_ADDR20 = BIT(5), + IOMUXA_ADDR21 = BIT(6), + IOMUXA_ADDR22 = BIT(7), + IOMUXA_ADDR23 = BIT(8), + IOMUXA_ADDR24 = BIT(9), + IOMUXA_ADDR25 = BIT(10), + IOMUXA_ADDR26 = BIT(11), + IOMUXA_nGCS1 = BIT(12), + IOMUXA_nGCS2 = BIT(13), + IOMUXA_nGCS3 = BIT(14), + IOMUXA_nGCS4 = BIT(15), + IOMUXA_nGCS5 = BIT(16), + IOMUXA_CLE = BIT(17), + IOMUXA_ALE = BIT(18), + IOMUXA_nFWE = BIT(19), + IOMUXA_nFRE = BIT(20), + IOMUXA_nRSTOUT = BIT(21), + IOMUXA_nFCE = BIT(22), /* PORT B */ IOMUXB_nXDREQ0 = (2 << 20), diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index dd473c8..63482c0 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -14,10 +14,10 @@ #define SDHCI_CONTROL3 0x84 #define SDHCI_CONTROL4 0x8C -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define SDHCI_CTRL2_SLCARDOUT (1 << 28) +#define SDHCI_CTRL2_ENSTAASYNCCLR BIT(31) +#define SDHCI_CTRL2_ENCMDCNFMSK BIT(30) +#define SDHCI_CTRL2_CDINVRXD3 BIT(29) +#define SDHCI_CTRL2_SLCARDOUT BIT(28) #define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) #define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) @@ -27,28 +27,28 @@ #define SDHCI_CTRL2_LVLDAT_SHIFT (16) #define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define SDHCI_CTRL2_SDCDSEL (1 << 13) -#define SDHCI_CTRL2_SDSIGPC (1 << 12) -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) +#define SDHCI_CTRL2_ENFBCLKTX BIT(15) +#define SDHCI_CTRL2_ENFBCLKRX BIT(14) +#define SDHCI_CTRL2_SDCDSEL BIT(13) +#define SDHCI_CTRL2_SDSIGPC BIT(12) +#define SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11) #define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) #define SDHCI_CTRL2_DFCNT_SHIFT (9) -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define SDHCI_CTRL2_RWAITMODE (1 << 7) -#define SDHCI_CTRL2_DISBUFRD (1 << 6) +#define SDHCI_CTRL2_ENCLKOUTHOLD BIT(8) +#define SDHCI_CTRL2_RWAITMODE BIT(7) +#define SDHCI_CTRL2_DISBUFRD BIT(6) #define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) #define SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define SDHCI_CTRL2_PWRSYNC (1 << 3) -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define SDHCI_CTRL2_HWINITFIN (1 << 0) +#define SDHCI_CTRL2_PWRSYNC BIT(3) +#define SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1) +#define SDHCI_CTRL2_HWINITFIN BIT(0) -#define SDHCI_CTRL3_FCSEL3 (1 << 31) -#define SDHCI_CTRL3_FCSEL2 (1 << 23) -#define SDHCI_CTRL3_FCSEL1 (1 << 15) -#define SDHCI_CTRL3_FCSEL0 (1 << 7) +#define SDHCI_CTRL3_FCSEL3 BIT(31) +#define SDHCI_CTRL3_FCSEL2 BIT(23) +#define SDHCI_CTRL3_FCSEL1 BIT(15) +#define SDHCI_CTRL3_FCSEL0 BIT(7) #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/include/asm/arch-s5pc1xx/power.h index 8400cda..c6b5c2e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/power.h +++ b/arch/arm/include/asm/arch-s5pc1xx/power.h @@ -14,12 +14,12 @@ */ #define S5PC100_OTHERS 0xE0108200 #define S5PC100_RST_STAT 0xE0108300 -#define S5PC100_SLEEP_WAKEUP (1 << 3) +#define S5PC100_SLEEP_WAKEUP BIT(3) #define S5PC100_WAKEUP_STAT 0xE0108304 #define S5PC100_INFORM0 0xE0108400 #define S5PC110_RST_STAT 0xE010A000 -#define S5PC110_SLEEP_WAKEUP (1 << 3) +#define S5PC110_SLEEP_WAKEUP BIT(3) #define S5PC110_WAKEUP_STAT 0xE010C200 #define S5PC110_OTHERS 0xE010E000 #define S5PC110_USB_PHY_CON 0xE010E80C diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h index 7a33ed8..7dff506 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h @@ -27,7 +27,7 @@ #define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) #define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) #define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) -#define TCON4_AUTO_RELOAD (1 << 22) +#define TCON4_AUTO_RELOAD BIT(22) #ifndef __ASSEMBLY__ struct s5p_timer { diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index 5449726..8d13a68 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -119,18 +119,18 @@ struct socfpga_clock_manager { u32 _pad_0xe8_0x200[70]; }; -#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_CTRL_SAFEMODE BIT(0) #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 -#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) +#define CLKMGR_BYPASS_PERPLLSRC BIT(4) #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 -#define CLKMGR_BYPASS_PERPLL (1 << 3) +#define CLKMGR_BYPASS_PERPLL BIT(3) #define CLKMGR_BYPASS_PERPLL_OFFSET 3 -#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) +#define CLKMGR_BYPASS_SDRPLLSRC BIT(2) #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 -#define CLKMGR_BYPASS_SDRPLL (1 << 1) +#define CLKMGR_BYPASS_SDRPLL BIT(1) #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 -#define CLKMGR_BYPASS_MAINPLL (1 << 0) +#define CLKMGR_BYPASS_MAINPLL BIT(0) #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 @@ -140,19 +140,19 @@ struct socfpga_clock_manager { #define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 -#define CLKMGR_STAT_BUSY (1 << 0) +#define CLKMGR_STAT_BUSY BIT(0) /* Main PLL */ -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) +#define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d @@ -199,9 +199,9 @@ struct socfpga_clock_manager { #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 @@ -276,7 +276,7 @@ struct socfpga_clock_manager { #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 071ec4f..1cf02c4 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -117,18 +117,18 @@ struct socfpga_system_manager { u32 spim0usefpga; /* 0x738 */ }; -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) -#define SYSMGR_ECC_OCRAM_EN (1 << 0) -#define SYSMGR_ECC_OCRAM_SERR (1 << 3) -#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) #define SYSMGR_FPGAINTF_USEFPGA 0x1 -#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) -#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) -#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) -#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) -#define SYSMGR_FPGAINTF_NAND (1 << 4) -#define SYSMGR_FPGAINTF_SDMMC (1 << 5) +#define SYSMGR_FPGAINTF_SPIM0 BIT(0) +#define SYSMGR_FPGAINTF_SPIM1 BIT(1) +#define SYSMGR_FPGAINTF_EMAC0 BIT(2) +#define SYSMGR_FPGAINTF_EMAC1 BIT(3) +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(5) /* FIXME: This is questionable macro. */ #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index c6da405..387f862 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -22,8 +22,8 @@ #define CONFIG_SSP3_BASE 0xD8180000 #define CONFIG_GPIO_BASE 0xD8100000 -#define CONFIG_SYS_NAND_CLE (1 << 16) -#define CONFIG_SYS_NAND_ALE (1 << 17) +#define CONFIG_SYS_NAND_CLE BIT(16) +#define CONFIG_SYS_NAND_ALE BIT(17) #if defined(CONFIG_SPEAR600) #define CONFIG_SYS_FSMC_BASE 0xD1800000 @@ -48,8 +48,8 @@ #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE -#define CONFIG_SYS_NAND_CLE (1 << 17) -#define CONFIG_SYS_NAND_ALE (1 << 16) +#define CONFIG_SYS_NAND_CLE BIT(17) +#define CONFIG_SYS_NAND_ALE BIT(16) #define CONFIG_SPEAR_EMIBASE 0x4F000000 #define CONFIG_SPEAR_RASBASE 0xB4000000 diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h index 3a6acb5..51e88b1 100644 --- a/arch/arm/include/asm/arch-spear/spr_emi.h +++ b/arch/arm/include/asm/arch-spear/spr_emi.h @@ -29,8 +29,8 @@ struct emi_regs { #define EMI_ACKMSK 0x40 /* control register definitions */ -#define EMI_CNTL_ENBBYTEW (1 << 2) -#define EMI_CNTL_ENBBYTER (1 << 3) +#define EMI_CNTL_ENBBYTEW BIT(2) +#define EMI_CNTL_ENBBYTER BIT(3) #define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) #endif diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h index 4ab3031..9a2640e 100644 --- a/arch/arm/include/asm/arch-stm32f4/fmc.h +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -58,12 +58,12 @@ struct stm32_fmc_regs { #define FMC_SDCMR_MODE_SELFREFRESH 5 #define FMC_SDCMR_MODE_POWERDOWN 6 -#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3) #define FMC_SDCMR_MODE_REGISTER_SHIFT 9 -#define FMC_SDSR_BUSY (1 << 5) +#define FMC_SDSR_BUSY BIT(5) #define FMC_BUSY_WAIT() do { \ __asm__ __volatile__ ("dsb" : : : "memory"); \ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index a9f88db..0b43f30 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -87,12 +87,12 @@ struct stm32_flash_regs { #define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) #define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) -#define STM32_FLASH_SR_BSY (1 << 16) +#define STM32_FLASH_SR_BSY BIT(16) -#define STM32_FLASH_CR_PG (1 << 0) -#define STM32_FLASH_CR_SER (1 << 1) -#define STM32_FLASH_CR_STRT (1 << 16) -#define STM32_FLASH_CR_LOCK (1 << 31) +#define STM32_FLASH_CR_PG BIT(0) +#define STM32_FLASH_CR_SER BIT(1) +#define STM32_FLASH_CR_STRT BIT(16) +#define STM32_FLASH_CR_LOCK BIT(31) #define STM32_FLASH_CR_SNB_OFFSET 3 enum clock { diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h index ddcbb57..a772361 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -64,7 +64,7 @@ struct stv0991_cgu_regs { /* Clock Enable/Disable */ -#define TIMER1_CLK_EN (1 << 15) +#define TIMER1_CLK_EN BIT(15) /* CGU Uart config */ #define CLK_UART_MCLK 0 diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index abd7257..7b08b90 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -28,7 +28,7 @@ struct gpt_regs *const gpt1_regs_ptr = /* Timer control1 register */ #define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) +#define GPT_MODE_AUTO_RELOAD BIT(7) /* Timer prescalar reg */ #define GPT_PRESCALER_128 0x128 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index c28ee05..ed9919c 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -282,7 +282,7 @@ struct sunxi_ccm_reg { #define CCM_DRAM_GATE_OFFSET_DE_BE1 27 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 BIT(24) #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) #define CCM_LCD_CH0_CTRL_RST (0x1 << 30) @@ -291,18 +291,18 @@ struct sunxi_ccm_reg { #define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) /* We leave bit 11 set to 0, so sclk1 == sclk2 */ #define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 BIT(24) #define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) /* Enable / disable both ch1 sclk1 and sclk2 at the same time */ #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) -#define CCM_LVDS_CTRL_RST (1 << 0) +#define CCM_LVDS_CTRL_RST BIT(0) #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_HDMI_CTRL_PLL_MASK (3 << 24) #define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL7 BIT(24) #define CCM_HDMI_CTRL_PLL3_2X (2 << 24) #define CCM_HDMI_CTRL_PLL7_2X (3 << 24) /* No separate ddc gate on sun4i, sun5i and sun7i */ @@ -330,10 +330,10 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_DE_CTRL_PLL_MASK (3 << 24) #define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL7 BIT(24) #define CCM_DE_CTRL_PLL5P (2 << 24) -#define CCM_DE_CTRL_RST (1 << 30) -#define CCM_DE_CTRL_GATE (1 << 31) +#define CCM_DE_CTRL_RST BIT(30) +#define CCM_DE_CTRL_GATE BIT(31) #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 8a80385..4910203 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -256,7 +256,7 @@ struct sunxi_ccm_reg { #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH0_CTRL_PLL7 BIT(24) #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) #define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) @@ -266,7 +266,7 @@ struct sunxi_ccm_reg { #define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) +#define CCM_LCD_CH1_CTRL_PLL7 BIT(24) #define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) @@ -274,7 +274,7 @@ struct sunxi_ccm_reg { #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_HDMI_CTRL_PLL_MASK (3 << 24) #define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) +#define CCM_HDMI_CTRL_PLL7 BIT(24) #define CCM_HDMI_CTRL_PLL3_2X (2 << 24) #define CCM_HDMI_CTRL_PLL7_2X (3 << 24) #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) @@ -315,12 +315,12 @@ struct sunxi_ccm_reg { #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_DE_CTRL_PLL_MASK (0xf << 24) #define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) +#define CCM_DE_CTRL_PLL7 BIT(24) #define CCM_DE_CTRL_PLL6_2X (2 << 24) #define CCM_DE_CTRL_PLL8 (3 << 24) #define CCM_DE_CTRL_PLL9 (4 << 24) #define CCM_DE_CTRL_PLL10 (5 << 24) -#define CCM_DE_CTRL_GATE (1 << 31) +#define CCM_DE_CTRL_GATE BIT(31) #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index c506b0a..9a119cf 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -108,8 +108,8 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_N(x) ((x) << 16) #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) #define CCM_MMC_CTRL_OSCM24 (0 << 24) -#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) -#define CCM_MMC_CTRL_ENABLE (1 << 31) +#define CCM_MMC_CTRL_PLL_PERIPH0 BIT(24) +#define CCM_MMC_CTRL_ENABLE BIT(31) /* ahb_gate0 fields */ /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 5e94253..b3c9852 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -316,11 +316,11 @@ struct sunxi_tve_reg { #define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) #define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) #define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) -#define SUNXI_DE_FE_ENABLE_EN (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) -#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) -#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) +#define SUNXI_DE_FE_ENABLE_EN BIT(0) +#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY BIT(0) +#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY BIT(1) +#define SUNXI_DE_FE_FRAME_CTRL_FRM_START BIT(16) +#define SUNXI_DE_FE_BYPASS_CSC_BYPASS BIT(1) #define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 #define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 @@ -329,11 +329,11 @@ struct sunxi_tve_reg { */ #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) #define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) -#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) -#define SUNXI_DE_BE_MODE_START (1 << 1) -#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) +#define SUNXI_DE_BE_MODE_ENABLE BIT(0) +#define SUNXI_DE_BE_MODE_START BIT(1) +#define SUNXI_DE_BE_MODE_LAYER0_ENABLE BIT(8) #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) -#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) +#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS BIT(0) #define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) @@ -342,21 +342,21 @@ struct sunxi_tve_reg { */ #define SUNXI_LCDC_X(x) (((x) - 1) << 16) #define SUNXI_LCDC_Y(y) (((y) - 1) << 0) -#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) -#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) -#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) +#define SUNXI_LCDC_TCON_VSYNC_MASK BIT(24) +#define SUNXI_LCDC_TCON_HSYNC_MASK BIT(25) +#define SUNXI_LCDC_CTRL_IO_MAP_MASK BIT(0) #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) -#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) -#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) +#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 BIT(0) +#define SUNXI_LCDC_CTRL_TCON_ENABLE BIT(31) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 (BIT(31) | (0 << 4)) +#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 (BIT(31) | (5 << 4)) #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_CTRL_ENABLE BIT(31) #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) @@ -364,16 +364,16 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) -#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE BIT(31) #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON1_CTRL_ENABLE BIT(31) #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 -#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#define SUNXI_LCDC_LVDS_ANA0_UPDATE BIT(22) #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) @@ -382,15 +382,15 @@ struct sunxi_tve_reg { */ #define SUNXI_HDMI_X(x) (((x) - 1) << 0) #define SUNXI_HDMI_Y(y) (((y) - 1) << 16) -#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) +#define SUNXI_HDMI_CTRL_ENABLE BIT(31) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF BIT(0) +#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF BIT(1) #define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 -#define SUNXI_HDMI_HPD_DETECT (1 << 0) -#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) -#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) -#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) +#define SUNXI_HDMI_HPD_DETECT BIT(0) +#define SUNXI_HDMI_VIDEO_CTRL_ENABLE BIT(31) +#define SUNXI_HDMI_VIDEO_CTRL_HDMI BIT(30) +#define SUNXI_HDMI_VIDEO_POL_HOR BIT(0) +#define SUNXI_HDMI_VIDEO_POL_VER BIT(1) #define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) #define SUNXI_HDMI_QCP_PACKET0 3 #define SUNXI_HDMI_QCP_PACKET1 0 @@ -410,7 +410,7 @@ struct sunxi_tve_reg { #else #define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 #endif -#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) +#define SUNXI_HDMI_PAD_CTRL1_HALVE BIT(6) #ifdef CONFIG_MACH_SUN6I #define SUNXI_HDMI_PLL_CTRL 0xba48a308 @@ -422,25 +422,25 @@ struct sunxi_tve_reg { #define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) #define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) -#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) +#define SUNXI_HDMI_PLL_DBG0_PLL7 BIT(21) #define SUNXI_HDMI_PKT_CTRL0 0x00000f21 #define SUNXI_HDMI_PKT_CTRL1 0x0000000f #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 #ifdef CONFIG_MACH_SUN6I -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) -#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) -#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) -#define SUNXI_HMDI_DDC_CTRL_START (1 << 27) -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) +#define SUNXI_HMDI_DDC_CTRL_ENABLE BIT(0) +#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE BIT(4) +#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE BIT(6) +#define SUNXI_HMDI_DDC_CTRL_START BIT(27) +#define SUNXI_HMDI_DDC_CTRL_RESET BIT(31) #else -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) +#define SUNXI_HMDI_DDC_CTRL_RESET BIT(0) /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 -#define SUNXI_HMDI_DDC_CTRL_START (1 << 30) -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) +#define SUNXI_HMDI_DDC_CTRL_START BIT(30) +#define SUNXI_HMDI_DDC_CTRL_ENABLE BIT(31) #endif #ifdef CONFIG_MACH_SUN6I @@ -453,9 +453,9 @@ struct sunxi_tve_reg { #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) #ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15) #else -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) +#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) #endif #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 @@ -468,13 +468,13 @@ struct sunxi_tve_reg { #define SUNXI_HDMI_DDC_CLOCK 0x0d #endif -#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) -#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) +#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) +#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) /* * TVE register constants. */ -#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) +#define SUNXI_TVE_GCTRL_ENABLE BIT(0) /* * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed * dac from tve1. When using tve1 the mux value must be written to both tve0's @@ -495,7 +495,7 @@ struct sunxi_tve_reg { #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) -#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) +#define SUNXI_TVE_CSC_REG0_ENABLE BIT(31) #define SUNXI_TVE_CSC_REG0 0x08440832 #define SUNXI_TVE_CSC_REG1 0x3b6dace1 #define SUNXI_TVE_CSC_REG2 0x0e1d13dc diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h index 40c385a..d54b4ee 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h @@ -159,10 +159,10 @@ struct dram_para { #define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) #define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) -#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ -#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ +#define DRAM_ZQCR0_ZCAL BIT(31) /* Starts ZQ calibration when set to 1 */ +#define DRAM_ZQCR0_ZDEN BIT(28) /* Uses ZDATA instead of doing calibration */ -#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ +#define DRAM_ZQSR_ZDONE BIT(31) /* ZQ calibration completion flag */ #define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) #define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h index 9b0b310..809bcb0 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h @@ -253,16 +253,16 @@ struct sunxi_mctl_phy_reg { #define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) #define MCTL_CR_BUSW_MASK (3 << 12) -#define MCTL_CR_BUSW16 (1 << 12) +#define MCTL_CR_BUSW16 BIT(12) #define MCTL_CR_BUSW32 (3 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) +#define MCTL_CR_SEQUENCE BIT(15) #define MCTL_CR_DDR3 (3 << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) +#define MCTL_CR_CHANNEL_MASK BIT(19) #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) -#define MCTL_CCR_CH0_CLK_EN (1 << 0) -#define MCTL_CCR_CH1_CLK_EN (1 << 1) -#define MCTL_CCR_MASTER_CLK_EN (1 << 2) +#define MCTL_CR_UNKNOWN (BIT(22) | BIT(20)) +#define MCTL_CCR_CH0_CLK_EN BIT(0) +#define MCTL_CCR_CH1_CLK_EN BIT(1) +#define MCTL_CCR_MASTER_CLK_EN BIT(2) /* * DRAM control (sunxi_mctl_ctl_reg) register constants. @@ -306,21 +306,21 @@ struct sunxi_mctl_phy_reg { #define MCTL_TCKESR 5 #define MCTL_TDPD 0 #define MCTL_DFITPHYRDL 15 -#define MCTL_DFIUPDCFG_UPD (1 << 1) +#define MCTL_DFIUPDCFG_UPD BIT(1) #define MCTL_DFISTCFG0 5 /* * DRAM phy (sunxi_mctl_phy_reg) register values / constants. */ -#define MCTL_PIR_CLEAR_STATUS (1 << 28) +#define MCTL_PIR_CLEAR_STATUS BIT(28) #define MCTL_PIR_STEP1 0xe9 #define MCTL_PIR_STEP2 0x81 -#define MCTL_PGCR_RANK (1 << 19) +#define MCTL_PGCR_RANK BIT(19) #define MCTL_PGCR 0x018c0202 #define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) /* constants for both acdllcr as well as dx#dllcr */ -#define MCTL_DLLCR_NRESET (1 << 30) -#define MCTL_DLLCR_DISABLE (1 << 31) +#define MCTL_DLLCR_NRESET BIT(30) +#define MCTL_DLLCR_DISABLE BIT(31) /* ptr constants these are or-ed together to get the final ptr# values */ #define MCTL_TITMSRST 10 #define MCTL_TDLLLOCK 2250 @@ -330,10 +330,10 @@ struct sunxi_mctl_phy_reg { #define MCTL_TDINIT2 87000 #define MCTL_TDINIT3 433 /* end ptr constants */ -#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) -#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) +#define MCTL_ACIOCR_DISABLE ((3 << 18) | BIT(8) | BIT(3)) +#define MCTL_DXCCR_DISABLE (BIT(3) | BIT(2)) #define MCTL_DXCCR 0x800 -#define MCTL_DSGCR_ENABLE (1 << 28) +#define MCTL_DSGCR_ENABLE BIT(28) #define MCTL_DSGCR 0xf200001b #define MCTL_DCR_DDR3 0x0b /* dtpr constants these are or-ed together to get the final dtpr# values */ @@ -349,11 +349,11 @@ struct sunxi_mctl_phy_reg { #define MCTL_MR1 0x4 #define MCTL_MR2 ((MCTL_TCWL - 5) << 3) #define MCTL_MR3 0x0 -#define MCTL_DX_GCR_EN (1 << 0) +#define MCTL_DX_GCR_EN BIT(0) #define MCTL_DX_GCR 0x880 -#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) -#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) -#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) -#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) +#define MCTL_DX_GSR0_RANK0_TRAIN_DONE BIT(0) +#define MCTL_DX_GSR0_RANK1_TRAIN_DONE BIT(1) +#define MCTL_DX_GSR0_RANK0_TRAIN_ERR BIT(4) +#define MCTL_DX_GSR0_RANK1_TRAIN_ERR BIT(5) #endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 74833b5..609c07b 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -124,8 +124,8 @@ struct sunxi_mmc { #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) -#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) -#define SUNXI_MMC_COMMON_RESET (1 << 18) +#define SUNXI_MMC_COMMON_CLK_GATE BIT(16) +#define SUNXI_MMC_COMMON_RESET BIT(18) struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h index a893466..e77f93e 100644 --- a/arch/arm/include/asm/arch-sunxi/rsb.h +++ b/arch/arm/include/asm/arch-sunxi/rsb.h @@ -30,15 +30,15 @@ struct sunxi_rsb_reg { u32 devaddr; /* 0x30 */ }; -#define RSB_CTRL_SOFT_RST (1 << 0) -#define RSB_CTRL_START_TRANS (1 << 7) +#define RSB_CTRL_SOFT_RST BIT(0) +#define RSB_CTRL_START_TRANS BIT(7) -#define RSB_STAT_TOVER_INT (1 << 0) -#define RSB_STAT_TERR_INT (1 << 1) -#define RSB_STAT_LBSY_INT (1 << 2) +#define RSB_STAT_TOVER_INT BIT(0) +#define RSB_STAT_TERR_INT BIT(1) +#define RSB_STAT_LBSY_INT BIT(2) #define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00 -#define RSB_DMCR_DEVICE_MODE_START (1 << 31) +#define RSB_DMCR_DEVICE_MODE_START BIT(31) #define RSB_CMD_BYTE_WRITE 0x4e #define RSB_CMD_BYTE_READ 0x8b diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index ca40e4e..5c104c1 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -10,7 +10,7 @@ #define PLL_STABILIZATION_DELAY (300) #define IO_STABILIZATION_DELAY (1000) -#define PLLX_ENABLED (1 << 30) +#define PLLX_ENABLED BIT(30) #define CCLK_BURST_POLICY 0x20008888 #define SUPER_CCLK_DIVIDER 0x80000000 @@ -35,9 +35,9 @@ #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) #define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) +#define HALT_COP_EVENT_JTAG BIT(28) +#define HALT_COP_EVENT_IRQ_1 BIT(11) +#define HALT_COP_EVENT_FIQ_1 BIT(9) /* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 7d28e16..a9d0b3e 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -237,9 +237,9 @@ struct clk_rst_ctlr { #define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ -#define PLL_OUT_RSTN (1 << 0) -#define PLL_OUT_CLKEN (1 << 1) -#define PLL_OUT_OVRRIDE (1 << 2) +#define PLL_OUT_RSTN BIT(0) +#define PLL_OUT_CLKEN BIT(1) +#define PLL_OUT_OVRRIDE BIT(2) #define PLL_OUT_RATIO_SHIFT 8 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) @@ -260,10 +260,10 @@ struct clk_rst_ctlr { #define PLLU_VCO_FREQ_SHIFT 20 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) -#define PLLP_OUT1_OVR (1 << 2) -#define PLLP_OUT2_OVR (1 << 18) -#define PLLP_OUT3_OVR (1 << 2) -#define PLLP_OUT4_OVR (1 << 18) +#define PLLP_OUT1_OVR BIT(2) +#define PLLP_OUT2_OVR BIT(18) +#define PLLP_OUT3_OVR BIT(2) +#define PLLP_OUT4_OVR BIT(18) #define PLLP_OUT1_RATIO 8 #define PLLP_OUT2_RATIO 24 #define PLLP_OUT3_RATIO 8 @@ -276,29 +276,29 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; -#define PLLP_OUT1_RSTN_DIS (1 << 0) +#define PLLP_OUT1_RSTN_DIS BIT(0) #define PLLP_OUT1_RSTN_EN (0 << 0) -#define PLLP_OUT1_CLKEN (1 << 1) -#define PLLP_OUT2_RSTN_DIS (1 << 16) +#define PLLP_OUT1_CLKEN BIT(1) +#define PLLP_OUT2_RSTN_DIS BIT(16) #define PLLP_OUT2_RSTN_EN (0 << 16) -#define PLLP_OUT2_CLKEN (1 << 17) +#define PLLP_OUT2_CLKEN BIT(17) -#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_DIS BIT(0) #define PLLP_OUT3_RSTN_EN (0 << 0) -#define PLLP_OUT3_CLKEN (1 << 1) -#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT3_CLKEN BIT(1) +#define PLLP_OUT4_RSTN_DIS BIT(16) #define PLLP_OUT4_RSTN_EN (0 << 16) -#define PLLP_OUT4_CLKEN (1 << 17) +#define PLLP_OUT4_CLKEN BIT(17) /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) +#define PLLU_POWERDOWN BIT(16) +#define PLL_ENABLE_POWERDOWN BIT(14) +#define PLL_ACTIVE_POWERDOWN BIT(12) /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN BIT(4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN BIT(2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN BIT(0) /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ #define OSC_XOE_SHIFT 0 @@ -340,10 +340,10 @@ enum { SCLK_SYS_STATE_IRQ = 4U, SCLK_SYS_STATE_FIQ = 8U, }; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) +#define SCLK_COP_FIQ_MASK BIT(27) +#define SCLK_CPU_FIQ_MASK BIT(26) +#define SCLK_COP_IRQ_MASK BIT(25) +#define SCLK_CPU_IRQ_MASK BIT(24) #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 #define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ @@ -392,49 +392,49 @@ enum { #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_L2RESET (1 << 24) -#define CLR_NONCPURESET (1 << 29) -#define CLR_PRESETDBG (1 << 30) +#define CLR_CPURESET0 BIT(0) +#define CLR_CPURESET1 BIT(1) +#define CLR_CPURESET2 BIT(2) +#define CLR_CPURESET3 BIT(3) +#define CLR_DBGRESET0 BIT(12) +#define CLR_DBGRESET1 BIT(13) +#define CLR_DBGRESET2 BIT(14) +#define CLR_DBGRESET3 BIT(15) +#define CLR_CORERESET0 BIT(16) +#define CLR_CORERESET1 BIT(17) +#define CLR_CORERESET2 BIT(18) +#define CLR_CORERESET3 BIT(19) +#define CLR_CXRESET0 BIT(20) +#define CLR_CXRESET1 BIT(21) +#define CLR_CXRESET2 BIT(22) +#define CLR_CXRESET3 BIT(23) +#define CLR_L2RESET BIT(24) +#define CLR_NONCPURESET BIT(29) +#define CLR_PRESETDBG BIT(30) /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ -#define CLR_CPU0_CLK_STP (1 << 8) -#define CLR_CPU1_CLK_STP (1 << 9) -#define CLR_CPU2_CLK_STP (1 << 10) -#define CLR_CPU3_CLK_STP (1 << 11) +#define CLR_CPU0_CLK_STP BIT(8) +#define CLR_CPU1_CLK_STP BIT(9) +#define CLR_CPU2_CLK_STP BIT(10) +#define CLR_CPU3_CLK_STP BIT(11) /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) /* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) +#define SET_CLK_ENB_CPUG_ENABLE BIT(0) +#define SET_CLK_ENB_CPULP_ENABLE BIT(1) +#define SET_CLK_ENB_MSELECT_ENABLE BIT(3) /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ -#define PLL_ACTIVE_POWERDOWN (1 << 12) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLLU_POWERDOWN (1 << 16) +#define PLL_ACTIVE_POWERDOWN BIT(12) +#define PLL_ENABLE_POWERDOWN BIT(14) +#define PLLU_POWERDOWN BIT(16) /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN BIT(0) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN BIT(2) +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN BIT(4) /* CLK_RST_CONTROLLER_PLLX_MISC_3 */ #define PLLX_IDDQ_SHIFT 3 diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 1dd3154..171da11 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -286,10 +286,10 @@ struct pmc_ctlr { #define CPU_CLMP 1 #define PARTID_CP 0xFFFFFFF8 -#define START_CP (1 << 8) +#define START_CP BIT(8) -#define CPUPWRREQ_OE (1 << 16) -#define CPUPWRREQ_POL (1 << 15) +#define CPUPWRREQ_OE BIT(16) +#define CPUPWRREQ_POL BIT(15) #define CRAIL 0 #define CE0 14 @@ -322,15 +322,15 @@ struct pmc_ctlr { #define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) /* SEC_DISABLE_0, 0x04 */ -#define SEC_DISABLE_WRITE0_ON (1 << 4) -#define SEC_DISABLE_READ0_ON (1 << 5) -#define SEC_DISABLE_WRITE1_ON (1 << 6) -#define SEC_DISABLE_READ1_ON (1 << 7) -#define SEC_DISABLE_WRITE2_ON (1 << 8) -#define SEC_DISABLE_READ2_ON (1 << 9) -#define SEC_DISABLE_WRITE3_ON (1 << 10) -#define SEC_DISABLE_READ3_ON (1 << 11) -#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) +#define SEC_DISABLE_WRITE0_ON BIT(4) +#define SEC_DISABLE_READ0_ON BIT(5) +#define SEC_DISABLE_WRITE1_ON BIT(6) +#define SEC_DISABLE_READ1_ON BIT(7) +#define SEC_DISABLE_WRITE2_ON BIT(8) +#define SEC_DISABLE_READ2_ON BIT(9) +#define SEC_DISABLE_WRITE3_ON BIT(10) +#define SEC_DISABLE_READ3_ON BIT(11) +#define SEC_DISABLE_AMAP_WRITE_ON BIT(20) /* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ #define PWRGATE_TOGGLE_PARTID_CRAIL 0 @@ -357,35 +357,35 @@ struct pmc_ctlr { #define PWRGATE_TOGGLE_PARTID_XUSBC 22 #define PWRGATE_TOGGLE_PARTID_VIC 23 #define PWRGATE_TOGGLE_PARTID_IRAM 24 -#define PWRGATE_TOGGLE_START (1 << 8) +#define PWRGATE_TOGGLE_START BIT(8) /* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ -#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) -#define PWRGATE_STATUS_TD_ENABLE (1 << 1) -#define PWRGATE_STATUS_VE_ENABLE (1 << 2) -#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) -#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) -#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) -#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) -#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) -#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) -#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) -#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) -#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) -#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) -#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) -#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) -#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) -#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) -#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) -#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) -#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) -#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) -#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) -#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) -#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) +#define PWRGATE_STATUS_CRAIL_ENABLE BIT(0) +#define PWRGATE_STATUS_TD_ENABLE BIT(1) +#define PWRGATE_STATUS_VE_ENABLE BIT(2) +#define PWRGATE_STATUS_PCX_ENABLE BIT(3) +#define PWRGATE_STATUS_VDE_ENABLE BIT(4) +#define PWRGATE_STATUS_L2C_ENABLE BIT(5) +#define PWRGATE_STATUS_MPE_ENABLE BIT(6) +#define PWRGATE_STATUS_HEG_ENABLE BIT(7) +#define PWRGATE_STATUS_SAX_ENABLE BIT(8) +#define PWRGATE_STATUS_CE1_ENABLE BIT(9) +#define PWRGATE_STATUS_CE2_ENABLE BIT(10) +#define PWRGATE_STATUS_CE3_ENABLE BIT(11) +#define PWRGATE_STATUS_CELP_ENABLE BIT(12) +#define PWRGATE_STATUS_CE0_ENABLE BIT(14) +#define PWRGATE_STATUS_C0NC_ENABLE BIT(15) +#define PWRGATE_STATUS_C1NC_ENABLE BIT(16) +#define PWRGATE_STATUS_SOR_ENABLE BIT(17) +#define PWRGATE_STATUS_DIS_ENABLE BIT(18) +#define PWRGATE_STATUS_DISB_ENABLE BIT(19) +#define PWRGATE_STATUS_XUSBA_ENABLE BIT(20) +#define PWRGATE_STATUS_XUSBB_ENABLE BIT(21) +#define PWRGATE_STATUS_XUSBC_ENABLE BIT(22) +#define PWRGATE_STATUS_VIC_ENABLE BIT(23) +#define PWRGATE_STATUS_IRAM_ENABLE BIT(24) /* APBDEV_PMC_CNTRL2_0 0x440 */ -#define HOLD_CKE_LOW_EN (1 << 12) +#define HOLD_CKE_LOW_EN BIT(12) #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/scu.h b/arch/arm/include/asm/arch-tegra/scu.h index 987c16f..70ee14f 100644 --- a/arch/arm/include/asm/arch-tegra/scu.h +++ b/arch/arm/include/asm/arch-tegra/scu.h @@ -22,6 +22,6 @@ struct scu_ctlr { uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ }; -#define SCU_CTRL_ENABLE (1 << 0) +#define SCU_CTRL_ENABLE BIT(0) #endif /* SCU_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a20bdaa..14c3942 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -69,7 +69,7 @@ struct tegra_mmc { unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ }; -#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) +#define TEGRA_MMC_PWRCTL_SD_BUS_POWER BIT(0) #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) @@ -79,53 +79,53 @@ struct tegra_mmc { #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) -#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) -#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) +#define TEGRA_MMC_TRNMOD_DMA_ENABLE BIT(0) +#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE BIT(1) #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) -#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ BIT(4) +#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT BIT(5) #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 BIT(0) #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) -#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) -#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) -#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) +#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK BIT(3) +#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK BIT(4) +#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER BIT(5) -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD BIT(0) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT BIT(1) -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) -#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE BIT(0) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE BIT(1) +#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE BIT(2) #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL BIT(0) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE BIT(1) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE BIT(2) -#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) -#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) +#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE BIT(0) +#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE BIT(1) +#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT BIT(3) +#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT BIT(15) +#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT BIT(16) -#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) +#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE BIT(0) +#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE BIT(1) +#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT BIT(3) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY BIT(4) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY BIT(5) -#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE BIT(1) /* SDMMC1/3 settings from section 24.6 of T30 TRM */ #define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLED (1 << 29) +#define AUTO_CAL_ENABLED BIT(29) #define AUTO_CAL_PD_OFFSET (0x70 << 8) #define AUTO_CAL_PU_OFFSET (0x62 << 0) diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index c817088..8fd83d0 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -202,33 +202,33 @@ struct usb_ctlr { #define VBUS_SENSE_CTL_A_SESS_VLD 3 /* USBx_IF_USB_SUSP_CTRL_0 */ -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) -#define USB_SUSP_CLR (1 << 5) +#define UTMIP_PHY_ENB BIT(12) +#define UTMIP_RESET BIT(11) +#define USB_PHY_CLK_VALID BIT(7) +#define USB_SUSP_CLR BIT(5) #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) /* USB2_IF_USB_SUSP_CTRL_0 */ -#define ULPI_PHY_ENB (1 << 13) +#define ULPI_PHY_ENB BIT(13) /* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) +#define ULPI_OUTPUT_PINMUX_BYP BIT(10) +#define ULPI_CLKOUT_PINMUX_BYP BIT(11) /* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_LOAD BIT(0) #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16) #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_LOAD BIT(24) #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) #endif /* USBx_UTMIP_MISC_CFG0 */ -#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) +#define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22) /* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) +#define UTMIP_PHY_XTAL_CLOCKEN BIT(30) /* * Tegra 3 and later: Moved to Clock and Reset register space, see @@ -254,9 +254,9 @@ struct usb_ctlr { #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff /* USBx_UTMIP_BIAS_CFG0_0 */ -#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) -#define UTMIP_OTGPD (1 << 11) -#define UTMIP_BIASPD (1 << 10) +#define UTMIP_HSDISCON_LEVEL_MSB BIT(24) +#define UTMIP_OTGPD BIT(11) +#define UTMIP_BIASPD BIT(10) #define UTMIP_HSDISCON_LEVEL_SHIFT 2 #define UTMIP_HSDISCON_LEVEL_MASK \ (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) @@ -275,13 +275,13 @@ struct usb_ctlr { #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff /* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) +#define UTMIP_FS_PREAMBLE_J BIT(19) /* USBx_UTMIP_BAT_CHRG_CFG0_0 */ #define UTMIP_PD_CHRG 1 /* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) +#define FUSE_SETUP_SEL BIT(3) /* USBx_UTMIP_HSRX_CFG0_0 */ #define UTMIP_IDLE_WAIT_SHIFT 15 @@ -296,23 +296,23 @@ struct usb_ctlr { (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) +#define IC_ENB1 BIT(3) #ifdef CONFIG_TEGRA20 /* PORTSC1, USB1 */ #define PTS1_SHIFT 31 #define PTS1_MASK (1 << PTS1_SHIFT) -#define STS1 (1 << 30) +#define STS1 BIT(30) /* PORTSC, USB2, USB3 */ #define PTS_SHIFT 30 #define PTS_MASK (3U << PTS_SHIFT) -#define STS (1 << 29) +#define STS BIT(29) #else /* USB2D_HOSTPC1_DEVLC_0 */ #define PTS_SHIFT 29 #define PTS_MASK (0x7U << PTS_SHIFT) -#define STS (1 << 28) +#define STS BIT(28) #endif #define PTS_UTMI 0 @@ -322,15 +322,15 @@ struct usb_ctlr { #define PTS_HSIC 4 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define WKOC (1 << 22) -#define WKDS (1 << 21) -#define WKCN (1 << 20) +#define WKOC BIT(22) +#define WKDS BIT(21) +#define WKCN BIT(20) /* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) +#define UTMIP_FORCE_PD_POWERDOWN BIT(14) +#define UTMIP_FORCE_PD2_POWERDOWN BIT(16) +#define UTMIP_FORCE_PDZI_POWERDOWN BIT(18) +#define UTMIP_XCVR_LSBIAS_SE BIT(21) #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 #define UTMIP_XCVR_HSSLEW_MSB_MASK \ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) @@ -343,14 +343,14 @@ struct usb_ctlr { #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2) +#define UTMIP_FORCE_PDDR_POWERDOWN BIT(4) /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) -#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) -#define VBUS_B_SESS_VLD_SW_EN (1 << 11) +#define VBUS_VLD_STS BIT(26) +#define VBUS_B_SESS_VLD_SW_VALUE BIT(12) +#define VBUS_B_SESS_VLD_SW_EN BIT(11) /* Setup USB on the board */ int usb_process_devicetree(const void *blob); diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h index c05e2c3..0d90438 100644 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -29,7 +29,7 @@ struct sysctr_ctlr { u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ }; -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ +#define TSC_CNTCR_ENABLE BIT(0) /* Enable */ +#define TSC_CNTCR_HDBG BIT(1) /* Halt on debug */ #endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h index 4e48c43..c83df0a 100644 --- a/arch/arm/include/asm/arch-tegra124/ahb.h +++ b/arch/arm/include/asm/arch-tegra124/ahb.h @@ -77,15 +77,15 @@ struct ahb_ctlr { u32 axicif_fastsync2_mcclk_to_cpuclk; }; -#define PPSB_STOPCLK_ENABLE (1 << 2) +#define PPSB_STOPCLK_ENABLE BIT(2) -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) +#define GIZ_ENABLE_SPLIT BIT(0) +#define GIZ_ENB_FAST_REARB BIT(2) +#define GIZ_DONT_SPLIT_AHB_WR BIT(7) -#define GIZ_USB_IMMEDIATE (1 << 18) +#define GIZ_USB_IMMEDIATE BIT(18) /* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE BIT(2) #endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 0db1881..96227d5 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -29,12 +29,12 @@ struct flow_ctlr { }; /* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) +#define EVENT_MSEC BIT(24) +#define EVENT_USEC BIT(25) +#define EVENT_JTAG BIT(28) #define EVENT_MODE_STOP (2 << 29) /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) +#define ACTIVE_LP BIT(0) #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index d526dfe..1c27576 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -44,6 +44,6 @@ struct mc_ctlr { }; #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED BIT(0) #endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h index 3f0309b..ea21dbb 100644 --- a/arch/arm/include/asm/arch-tegra124/sysctr.h +++ b/arch/arm/include/asm/arch-tegra124/sysctr.h @@ -20,7 +20,7 @@ struct sysctr_ctlr { u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ }; -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ +#define TSC_CNTCR_ENABLE BIT(0) /* Enable */ +#define TSC_CNTCR_HDBG BIT(1) /* Halt on debug */ #endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a..da7886a 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -112,7 +112,7 @@ struct anadig_reg { }; #endif -#define CCM_CCR_FIRC_EN (1 << 16) +#define CCM_CCR_FIRC_EN BIT(16) #define CCM_CCR_OSCNT_MASK 0xff #define CCM_CCR_OSCNT(v) ((v) & 0xff) @@ -124,14 +124,14 @@ struct anadig_reg { #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) -#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) -#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) +#define CCM_CCSR_PLL2_PFD4_EN BIT(15) +#define CCM_CCSR_PLL2_PFD3_EN BIT(14) +#define CCM_CCSR_PLL2_PFD2_EN BIT(13) +#define CCM_CCSR_PLL2_PFD1_EN BIT(12) +#define CCM_CCSR_PLL1_PFD4_EN BIT(11) +#define CCM_CCSR_PLL1_PFD3_EN BIT(10) +#define CCM_CCSR_PLL1_PFD2_EN BIT(9) +#define CCM_CCSR_PLL1_PFD1_EN BIT(8) #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) @@ -160,16 +160,16 @@ struct anadig_reg { #define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) #define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) -#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) +#define CCM_CSCDR1_RMII_CLK_EN BIT(24) -#define CCM_CSCDR2_NFC_EN (1 << 9) -#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) -#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) +#define CCM_CSCDR2_NFC_EN BIT(9) +#define CCM_CSCDR2_NFC_FRAC_DIV_EN BIT(13) +#define CCM_CSCDR2_NFC_CLK_INV BIT(14) #define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 #define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) #define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) -#define CCM_CSCDR2_ESDHC1_EN (1 << 29) +#define CCM_CSCDR2_ESDHC1_EN BIT(29) #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) @@ -177,7 +177,7 @@ struct anadig_reg { #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 #define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) #define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) -#define CCM_CSCDR3_QSPI0_EN (1 << 4) +#define CCM_CSCDR3_QSPI0_EN BIT(4) #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) #define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) @@ -213,23 +213,23 @@ struct anadig_reg { #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) #define CCM_CCGR10_NFC_CTRL_MASK 0x3 -#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL7_CTRL_BYPASS BIT(16) +#define ANADIG_PLL7_CTRL_ENABLE BIT(13) +#define ANADIG_PLL7_CTRL_POWERDOWN BIT(12) +#define ANADIG_PLL7_CTRL_DIV_SELECT BIT(1) +#define ANADIG_PLL5_CTRL_BYPASS BIT(16) +#define ANADIG_PLL5_CTRL_ENABLE BIT(13) +#define ANADIG_PLL5_CTRL_POWERDOWN BIT(12) #define ANADIG_PLL5_CTRL_DIV_SELECT 1 -#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL3_CTRL_BYPASS BIT(16) +#define ANADIG_PLL3_CTRL_ENABLE BIT(13) +#define ANADIG_PLL3_CTRL_POWERDOWN BIT(12) +#define ANADIG_PLL3_CTRL_DIV_SELECT BIT(1) +#define ANADIG_PLL2_CTRL_ENABLE BIT(13) +#define ANADIG_PLL2_CTRL_POWERDOWN BIT(12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL1_CTRL_ENABLE BIT(13) +#define ANADIG_PLL1_CTRL_POWERDOWN BIT(12) #define ANADIG_PLL1_CTRL_DIV_SELECT 1 #define FASE_CLK_FREQ 24000000 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index a7d765a..f86791a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -113,8 +113,8 @@ #define DDRMC_PHY_OFF 0x00000000 #define DDRMC_PHY_PROC_PAD_ODT 0x00010101 -#define DDRMC_PHY50_DDR3_MODE (1 << 12) -#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) +#define DDRMC_PHY50_DDR3_MODE BIT(12) +#define DDRMC_PHY50_EN_SW_HALF_CYCLE BIT(8) #define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) #define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) @@ -138,15 +138,15 @@ #define DDRMC_CR17_TMOD(v) ((v) & 0xff) #define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) #define DDRMC_CR18_TCKE(v) ((v) & 0x7) -#define DDRMC_CR20_AP_EN (1 << 24) +#define DDRMC_CR20_AP_EN BIT(24) #define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) -#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8) +#define DDRMC_CR21_TRAS_LOCKOUT BIT(8) #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) #define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) -#define DDRMC_CR25_TREF_EN (1 << 16) +#define DDRMC_CR25_TREF_EN BIT(16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) #define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) #define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) @@ -154,7 +154,7 @@ #define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) #define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) #define DDRMC_CR31_TXSR(v) ((v) & 0xffff) -#define DDRMC_CR33_EN_QK_SREF (1 << 16) +#define DDRMC_CR33_EN_QK_SREF BIT(16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) #define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) @@ -173,37 +173,37 @@ #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) -#define DDRMC_CR74_BANKSPLT_EN (1 << 24) -#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) +#define DDRMC_CR74_BANKSPLT_EN BIT(24) +#define DDRMC_CR74_ADDR_CMP_EN BIT(16) #define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) #define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) -#define DDRMC_CR75_RW_PG_EN (1 << 24) -#define DDRMC_CR75_RW_EN (1 << 16) -#define DDRMC_CR75_PRI_EN (1 << 8) +#define DDRMC_CR75_RW_PG_EN BIT(24) +#define DDRMC_CR75_RW_EN BIT(16) +#define DDRMC_CR75_PRI_EN BIT(8) #define DDRMC_CR75_PLEN 1 #define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) #define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) -#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) +#define DDRMC_CR76_W2R_SPLT_EN BIT(8) #define DDRMC_CR76_CS_EN 1 -#define DDRMC_CR77_CS_MAP (1 << 24) -#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) +#define DDRMC_CR77_CS_MAP BIT(24) +#define DDRMC_CR77_DI_RD_INTLEAVE BIT(8) #define DDRMC_CR77_SWAP_EN 1 #define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) #define DDRMC_CR82_INT_MASK 0x10000000 -#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) -#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) +#define DDRMC_CR87_ODT_WR_MAPCS0 BIT(24) +#define DDRMC_CR87_ODT_RD_MAPCS0 BIT(16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) -#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR97_WRLVL_EN BIT(24) #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) -#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) -#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) +#define DDRMC_CR102_RDLVL_GT_REGEN BIT(16) +#define DDRMC_CR102_RDLVL_REG_EN BIT(8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) #define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) @@ -223,7 +223,7 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) +#define DDRMC_CR123_AXI1_P_ODR_EN BIT(16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) @@ -252,7 +252,7 @@ #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) #define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) -#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) +#define DDRMC_CR155_AXI0_AWCACHE BIT(10) #define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) #define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 58d8b16..db042f6 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -81,7 +81,7 @@ static inline void v7_enable_l2_hazard_detect(void) /* L2ACTLR[7]: Enable hazard detect timeout */ asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); - val |= (1 << 7); + val |= BIT(7); asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); } @@ -99,7 +99,7 @@ static inline void v7_enable_smp(uint32_t address) asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); /* Enable SMP */ - val |= (1 << 6); + val |= BIT(6); /* Dummy read to assure L2 access */ temp = readl(address); diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index d2aa1c4..6366fc9 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -32,10 +32,10 @@ struct v7m_scb { #define V7M_AIRCR_VECTKEY 0x5fa #define V7M_AIRCR_VECTKEY_SHIFT 16 -#define V7M_AIRCR_ENDIAN (1 << 15) +#define V7M_AIRCR_ENDIAN BIT(15) #define V7M_AIRCR_PRIGROUP_SHIFT 8 #define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) -#define V7M_AIRCR_SYSRESET (1 << 2) +#define V7M_AIRCR_SYSRESET BIT(2) #define V7M_ICSR_VECTACT_MSK 0xFF @@ -48,10 +48,10 @@ struct v7m_mpu { }; #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) +#define V7M_MPU_CTRL_ENABLE BIT(0) +#define V7M_MPU_CTRL_HFNMIENA BIT(1) -#define V7M_MPU_RASR_EN (1 << 0) +#define V7M_MPU_RASR_EN BIT(0) #define V7M_MPU_RASR_SIZE_BITS 1 #define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) #define V7M_MPU_RASR_AP_RW_RW (3 << 24) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b9cb52..be6a6ea 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -60,15 +60,15 @@ #define PMD_TYPE_MASK (3 << 0) #define PMD_TYPE_FAULT (0 << 0) #define PMD_TYPE_TABLE (3 << 0) -#define PMD_TYPE_SECT (1 << 0) +#define PMD_TYPE_SECT BIT(0) /* * Section */ #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) -#define PMD_SECT_AF (1 << 10) -#define PMD_SECT_NG (1 << 11) +#define PMD_SECT_AF BIT(10) +#define PMD_SECT_NG BIT(11) #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54) @@ -83,20 +83,20 @@ */ #define TCR_T0SZ(x) ((64 - (x)) << 0) #define TCR_IRGN_NC (0 << 8) -#define TCR_IRGN_WBWA (1 << 8) +#define TCR_IRGN_WBWA BIT(8) #define TCR_IRGN_WT (2 << 8) #define TCR_IRGN_WBNWA (3 << 8) #define TCR_IRGN_MASK (3 << 8) #define TCR_ORGN_NC (0 << 10) -#define TCR_ORGN_WBWA (1 << 10) +#define TCR_ORGN_WBWA BIT(10) #define TCR_ORGN_WT (2 << 10) #define TCR_ORGN_WBNWA (3 << 10) #define TCR_ORGN_MASK (3 << 10) #define TCR_SHARED_NON (0 << 12) -#define TCR_SHARED_OUTER (1 << 12) +#define TCR_SHARED_OUTER BIT(12) #define TCR_SHARED_INNER (2 << 12) #define TCR_TG0_4K (0 << 14) -#define TCR_TG0_64K (1 << 14) +#define TCR_TG0_64K BIT(14) #define TCR_TG0_16K (2 << 14) #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index c7bca05..a9928ed 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -45,27 +45,27 @@ enum usbhs_omap_port_mode { #define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */ /* UHH Register Set */ -#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) -#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) -#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) -#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN BIT(2) +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN BIT(3) +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN BIT(4) +#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN BIT(5) #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS 1 -#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) -#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) -#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) +#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS BIT(11) +#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS BIT(12) +#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK BIT(31) #define OMAP_P1_MODE_CLEAR (3 << 16) -#define OMAP_P1_MODE_TLL (1 << 16) +#define OMAP_P1_MODE_TLL BIT(16) #define OMAP_P1_MODE_HSIC (3 << 16) #define OMAP_P2_MODE_CLEAR (3 << 18) -#define OMAP_P2_MODE_TLL (1 << 18) +#define OMAP_P2_MODE_TLL BIT(18) #define OMAP_P2_MODE_HSIC (3 << 18) #define OMAP_P3_MODE_CLEAR (3 << 20) #define OMAP_P3_MODE_HSIC (3 << 20) /* EHCI Register Set */ -#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) +#define EHCI_INSNREG04_DISABLE_UNSUSPEND BIT(5) #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 @@ -76,9 +76,9 @@ enum usbhs_omap_port_mode { /* TLL Register Set */ #define OMAP_TLL_CHANNEL_CONF(num) (0x004 * num) -#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16) -#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15) -#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) +#define OMAP_TLL_CHANNEL_CONF_DRVVBUS BIT(16) +#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS BIT(15) +#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF BIT(11) #define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI (2 << 1) #define OMAP_TLL_CHANNEL_CONF_CHANEN 1 diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7a545ea..66c8b7e 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -39,13 +39,13 @@ /* STATUS */ #define EMIF_REG_BE_SHIFT 31 -#define EMIF_REG_BE_MASK (1 << 31) +#define EMIF_REG_BE_MASK BIT(31) #define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 -#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define EMIF_REG_DUAL_CLK_MODE_MASK BIT(30) #define EMIF_REG_FAST_INIT_SHIFT 29 -#define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_FAST_INIT_MASK BIT(29) #define EMIF_REG_PHY_DLL_READY_SHIFT 2 -#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) +#define EMIF_REG_PHY_DLL_READY_MASK BIT(2) /* SDRAM_CONFIG */ #define EMIF_REG_SDRAM_TYPE_SHIFT 29 @@ -61,11 +61,11 @@ #define EMIF_REG_DDR_TERM_SHIFT 24 #define EMIF_REG_DDR_TERM_MASK (0x7 << 24) #define EMIF_REG_DDR2_DDQS_SHIFT 23 -#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) +#define EMIF_REG_DDR2_DDQS_MASK BIT(23) #define EMIF_REG_DYN_ODT_SHIFT 21 #define EMIF_REG_DYN_ODT_MASK (0x3 << 21) #define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 -#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define EMIF_REG_DDR_DISABLE_DLL_MASK BIT(20) #define EMIF_REG_SDRAM_DRIVE_SHIFT 18 #define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) #define EMIF_REG_CWL_SHIFT 16 @@ -79,15 +79,15 @@ #define EMIF_REG_IBANK_SHIFT 4 #define EMIF_REG_IBANK_MASK (0x7 << 4) #define EMIF_REG_EBANK_SHIFT 3 -#define EMIF_REG_EBANK_MASK (1 << 3) +#define EMIF_REG_EBANK_MASK BIT(3) #define EMIF_REG_PAGESIZE_SHIFT 0 #define EMIF_REG_PAGESIZE_MASK (0x7 << 0) /* SDRAM_CONFIG_2 */ #define EMIF_REG_CS1NVMEN_SHIFT 30 -#define EMIF_REG_CS1NVMEN_MASK (1 << 30) +#define EMIF_REG_CS1NVMEN_MASK BIT(30) #define EMIF_REG_EBANK_POS_SHIFT 27 -#define EMIF_REG_EBANK_POS_MASK (1 << 27) +#define EMIF_REG_EBANK_POS_MASK BIT(27) #define EMIF_REG_RDBNUM_SHIFT 4 #define EMIF_REG_RDBNUM_MASK (0x3 << 4) #define EMIF_REG_RDBSIZE_SHIFT 0 @@ -95,11 +95,11 @@ /* SDRAM_REF_CTRL */ #define EMIF_REG_INITREF_DIS_SHIFT 31 -#define EMIF_REG_INITREF_DIS_MASK (1 << 31) +#define EMIF_REG_INITREF_DIS_MASK BIT(31) #define EMIF_REG_SRT_SHIFT 29 -#define EMIF_REG_SRT_MASK (1 << 29) +#define EMIF_REG_SRT_MASK BIT(29) #define EMIF_REG_ASR_SHIFT 28 -#define EMIF_REG_ASR_MASK (1 << 28) +#define EMIF_REG_ASR_MASK BIT(28) #define EMIF_REG_PASR_SHIFT 24 #define EMIF_REG_PASR_MASK (0x7 << 24) #define EMIF_REG_REFRESH_RATE_SHIFT 0 @@ -227,7 +227,7 @@ #define EMIF_REG_PD_TIM_SHIFT 12 #define EMIF_REG_PD_TIM_MASK (0xf << 12) #define EMIF_REG_DPD_EN_SHIFT 11 -#define EMIF_REG_DPD_EN_MASK (1 << 11) +#define EMIF_REG_DPD_EN_MASK BIT(11) #define EMIF_REG_LP_MODE_SHIFT 8 #define EMIF_REG_LP_MODE_MASK (0x7 << 8) #define EMIF_REG_SR_TIM_SHIFT 4 @@ -249,9 +249,9 @@ /* LPDDR2_MODE_REG_CFG */ #define EMIF_REG_CS_SHIFT 31 -#define EMIF_REG_CS_MASK (1 << 31) +#define EMIF_REG_CS_MASK BIT(31) #define EMIF_REG_REFRESH_EN_SHIFT 30 -#define EMIF_REG_REFRESH_EN_MASK (1 << 30) +#define EMIF_REG_REFRESH_EN_MASK BIT(30) #define EMIF_REG_ADDRESS_SHIFT 0 #define EMIF_REG_ADDRESS_MASK (0xff << 0) @@ -287,21 +287,21 @@ #define EMIF_REG_TLEC_SHIFT 16 #define EMIF_REG_TLEC_MASK (0xffff << 16) #define EMIF_REG_MT_SHIFT 14 -#define EMIF_REG_MT_MASK (1 << 14) +#define EMIF_REG_MT_MASK BIT(14) #define EMIF_REG_ACT_CAP_EN_SHIFT 13 -#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) +#define EMIF_REG_ACT_CAP_EN_MASK BIT(13) #define EMIF_REG_OPG_LD_SHIFT 12 -#define EMIF_REG_OPG_LD_MASK (1 << 12) +#define EMIF_REG_OPG_LD_MASK BIT(12) #define EMIF_REG_RESET_PHY_SHIFT 10 -#define EMIF_REG_RESET_PHY_MASK (1 << 10) +#define EMIF_REG_RESET_PHY_MASK BIT(10) #define EMIF_REG_MMS_SHIFT 8 -#define EMIF_REG_MMS_MASK (1 << 8) +#define EMIF_REG_MMS_MASK BIT(8) #define EMIF_REG_MC_SHIFT 4 #define EMIF_REG_MC_MASK (0x3 << 4) #define EMIF_REG_PC_SHIFT 1 #define EMIF_REG_PC_MASK (0x7 << 1) #define EMIF_REG_TM_SHIFT 0 -#define EMIF_REG_TM_MASK (1 << 0) +#define EMIF_REG_TM_MASK BIT(0) /* IODFT_CTRL_MISR_RSLT */ #define EMIF_REG_DQM_TLMR_SHIFT 16 @@ -335,15 +335,15 @@ /* PERF_CNT_CFG */ #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 -#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define EMIF_REG_CNTR2_MCONNID_EN_MASK BIT(31) #define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 -#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define EMIF_REG_CNTR2_REGION_EN_MASK BIT(30) #define EMIF_REG_CNTR2_CFG_SHIFT 16 #define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 -#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define EMIF_REG_CNTR1_MCONNID_EN_MASK BIT(15) #define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 -#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define EMIF_REG_CNTR1_REGION_EN_MASK BIT(14) #define EMIF_REG_CNTR1_CFG_SHIFT 0 #define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) @@ -375,23 +375,23 @@ /* IRQ_EOI */ #define EMIF_REG_EOI_SHIFT 0 -#define EMIF_REG_EOI_MASK (1 << 0) +#define EMIF_REG_EOI_MASK BIT(0) /* IRQSTATUS_RAW_SYS */ #define EMIF_REG_DNV_SYS_SHIFT 2 -#define EMIF_REG_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_DNV_SYS_MASK BIT(2) #define EMIF_REG_TA_SYS_SHIFT 1 -#define EMIF_REG_TA_SYS_MASK (1 << 1) +#define EMIF_REG_TA_SYS_MASK BIT(1) #define EMIF_REG_ERR_SYS_SHIFT 0 -#define EMIF_REG_ERR_SYS_MASK (1 << 0) +#define EMIF_REG_ERR_SYS_MASK BIT(0) /* IRQSTATUS_RAW_LL */ #define EMIF_REG_DNV_LL_SHIFT 2 -#define EMIF_REG_DNV_LL_MASK (1 << 2) +#define EMIF_REG_DNV_LL_MASK BIT(2) #define EMIF_REG_TA_LL_SHIFT 1 -#define EMIF_REG_TA_LL_MASK (1 << 1) +#define EMIF_REG_TA_LL_MASK BIT(1) #define EMIF_REG_ERR_LL_SHIFT 0 -#define EMIF_REG_ERR_LL_MASK (1 << 0) +#define EMIF_REG_ERR_LL_MASK BIT(0) /* IRQSTATUS_SYS */ @@ -399,19 +399,19 @@ /* IRQENABLE_SET_SYS */ #define EMIF_REG_EN_DNV_SYS_SHIFT 2 -#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_EN_DNV_SYS_MASK BIT(2) #define EMIF_REG_EN_TA_SYS_SHIFT 1 -#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) +#define EMIF_REG_EN_TA_SYS_MASK BIT(1) #define EMIF_REG_EN_ERR_SYS_SHIFT 0 -#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) +#define EMIF_REG_EN_ERR_SYS_MASK BIT(0) /* IRQENABLE_SET_LL */ #define EMIF_REG_EN_DNV_LL_SHIFT 2 -#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) +#define EMIF_REG_EN_DNV_LL_MASK BIT(2) #define EMIF_REG_EN_TA_LL_SHIFT 1 -#define EMIF_REG_EN_TA_LL_MASK (1 << 1) +#define EMIF_REG_EN_TA_LL_MASK BIT(1) #define EMIF_REG_EN_ERR_LL_SHIFT 0 -#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) +#define EMIF_REG_EN_ERR_LL_MASK BIT(0) /* IRQENABLE_CLR_SYS */ @@ -419,13 +419,13 @@ /* ZQ_CONFIG */ #define EMIF_REG_ZQ_CS1EN_SHIFT 31 -#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) +#define EMIF_REG_ZQ_CS1EN_MASK BIT(31) #define EMIF_REG_ZQ_CS0EN_SHIFT 30 -#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) +#define EMIF_REG_ZQ_CS0EN_MASK BIT(30) #define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 -#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define EMIF_REG_ZQ_DUALCALEN_MASK BIT(29) #define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 -#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_ZQ_SFEXITEN_MASK BIT(28) #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 #define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 @@ -435,11 +435,11 @@ /* TEMP_ALERT_CONFIG */ #define EMIF_REG_TA_CS1EN_SHIFT 31 -#define EMIF_REG_TA_CS1EN_MASK (1 << 31) +#define EMIF_REG_TA_CS1EN_MASK BIT(31) #define EMIF_REG_TA_CS0EN_SHIFT 30 -#define EMIF_REG_TA_CS0EN_MASK (1 << 30) +#define EMIF_REG_TA_CS0EN_MASK BIT(30) #define EMIF_REG_TA_SFEXITEN_SHIFT 28 -#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_TA_SFEXITEN_MASK BIT(28) #define EMIF_REG_TA_DEVWDT_SHIFT 26 #define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) #define EMIF_REG_TA_DEVCNT_SHIFT 24 @@ -483,7 +483,7 @@ /*EMIF_READ_WRITE_LEVELING_CONTROL*/ #define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 -#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLFULL_START_MASK BIT(31) #define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 #define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) #define EMIF_REG_RDLVLINC_INT_SHIFT 16 @@ -495,7 +495,7 @@ /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ #define EMIF_REG_RDWRLVL_EN_SHIFT 31 -#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVL_EN_MASK BIT(31) #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 @@ -1016,15 +1016,15 @@ struct dmm_lisa_map_regs { #define LPDDR2_MR0_DAI_SHIFT 0 #define LPDDR2_MR0_DAI_MASK 1 #define LPDDR2_MR0_DI_SHIFT 1 -#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DI_MASK BIT(1) #define LPDDR2_MR0_DNVI_SHIFT 2 -#define LPDDR2_MR0_DNVI_MASK (1 << 2) +#define LPDDR2_MR0_DNVI_MASK BIT(2) /* MR4 */ #define MR4_SDRAM_REF_RATE_SHIFT 0 #define MR4_SDRAM_REF_RATE_MASK 7 #define MR4_TUF_SHIFT 7 -#define MR4_TUF_MASK (1 << 7) +#define MR4_TUF_MASK BIT(7) /* MR4 SDRAM Refresh Rate field values */ #define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h index d5c1f7f..608eedf 100644 --- a/arch/arm/include/asm/imx-common/dma.h +++ b/arch/arm/include/asm/imx-common/dma.h @@ -87,14 +87,14 @@ enum { #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 -#define MXS_DMA_DESC_CHAIN (1 << 2) -#define MXS_DMA_DESC_IRQ (1 << 3) -#define MXS_DMA_DESC_NAND_LOCK (1 << 4) -#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) -#define MXS_DMA_DESC_DEC_SEM (1 << 6) -#define MXS_DMA_DESC_WAIT4END (1 << 7) -#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) -#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) +#define MXS_DMA_DESC_CHAIN BIT(2) +#define MXS_DMA_DESC_IRQ BIT(3) +#define MXS_DMA_DESC_NAND_LOCK BIT(4) +#define MXS_DMA_DESC_NAND_WAIT_4_READY BIT(5) +#define MXS_DMA_DESC_DEC_SEM BIT(6) +#define MXS_DMA_DESC_WAIT4END BIT(7) +#define MXS_DMA_DESC_HALT_ON_TERMINATE BIT(8) +#define MXS_DMA_DESC_TERMINATE_FLUSH BIT(9) #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) @@ -116,9 +116,9 @@ struct mxs_dma_cmd { * This structure incorporates an MXS DMA hardware command structure, along * with metadata. */ -#define MXS_DMA_DESC_FIRST (1 << 0) -#define MXS_DMA_DESC_LAST (1 << 1) -#define MXS_DMA_DESC_READY (1 << 31) +#define MXS_DMA_DESC_FIRST BIT(0) +#define MXS_DMA_DESC_LAST BIT(1) +#define MXS_DMA_DESC_READY BIT(31) struct mxs_dma_desc { struct mxs_dma_cmd cmd; @@ -136,10 +136,10 @@ struct mxs_dma_desc { * system (see mxs_dma_channels). */ #define MXS_DMA_FLAGS_IDLE 0 -#define MXS_DMA_FLAGS_BUSY (1 << 0) +#define MXS_DMA_FLAGS_BUSY BIT(0) #define MXS_DMA_FLAGS_FREE 0 -#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) -#define MXS_DMA_FLAGS_VALID (1 << 31) +#define MXS_DMA_FLAGS_ALLOCATED BIT(16) +#define MXS_DMA_FLAGS_VALID BIT(31) struct mxs_dma_chan { const char *name; diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index e0a49be..c6b65bb 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -83,27 +83,27 @@ typedef u64 iomux_v3_cfg_t; #define NO_MUX_I 0 #define NO_PAD_I 0 -#define NO_PAD_CTRL (1 << 17) +#define NO_PAD_CTRL BIT(17) #ifdef CONFIG_MX6 -#define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_HYS BIT(16) #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) -#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_PKE BIT(12) -#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_ODE BIT(11) -#define PAD_CTL_SPEED_LOW (1 << 6) +#define PAD_CTL_SPEED_LOW BIT(6) #define PAD_CTL_SPEED_MED (2 << 6) #define PAD_CTL_SPEED_HIGH (3 << 6) #define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_240ohm BIT(3) #define PAD_CTL_DSE_120ohm (2 << 3) #define PAD_CTL_DSE_80ohm (3 << 3) #define PAD_CTL_DSE_60ohm (4 << 3) @@ -112,22 +112,22 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_34ohm (7 << 3) #if defined CONFIG_MX6SL -#define PAD_CTL_LVE (1 << 1) -#define PAD_CTL_LVE_BIT (1 << 22) +#define PAD_CTL_LVE BIT(1) +#define PAD_CTL_LVE_BIT BIT(22) #endif #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20 -#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) +#define PAD_CTL_INPUT_DIFFERENTIAL BIT(16) -#define PAD_CTL_SPEED_MED (1 << 12) +#define PAD_CTL_SPEED_MED BIT(12) #define PAD_CTL_SPEED_HIGH (3 << 12) -#define PAD_CTL_SRE (1 << 11) +#define PAD_CTL_SRE BIT(11) -#define PAD_CTL_DSE_150ohm (1 << 6) +#define PAD_CTL_DSE_150ohm BIT(6) #define PAD_CTL_DSE_50ohm (3 << 6) #define PAD_CTL_DSE_25ohm (6 << 6) #define PAD_CTL_DSE_20ohm (7 << 6) @@ -135,37 +135,37 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PKE (1 << 3) +#define PAD_CTL_PKE BIT(3) #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) #define PAD_CTL_OBE_IBE_ENABLE (3 << 0) -#define PAD_CTL_OBE_ENABLE (1 << 1) -#define PAD_CTL_IBE_ENABLE (1 << 0) +#define PAD_CTL_OBE_ENABLE BIT(1) +#define PAD_CTL_IBE_ENABLE BIT(0) #else -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_INPUT_DDR (1 << 9) -#define PAD_CTL_HYS (1 << 8) +#define PAD_CTL_DVS BIT(13) +#define PAD_CTL_INPUT_DDR BIT(9) +#define PAD_CTL_HYS BIT(8) -#define PAD_CTL_PKE (1 << 7) +#define PAD_CTL_PKE BIT(7) #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) -#define PAD_CTL_ODE (1 << 3) +#define PAD_CTL_ODE BIT(3) #define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_MED BIT(1) #define PAD_CTL_DSE_HIGH (2 << 1) #define PAD_CTL_DSE_MAX (3 << 1) #endif #define PAD_CTL_SRE_SLOW (0 << 0) -#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_FAST BIT(0) #define IOMUX_CONFIG_SION 0x10 diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h index ca77436..d4801d9 100644 --- a/arch/arm/include/asm/imx-common/regs-apbh.h +++ b/arch/arm/include/asm/imx-common/regs-apbh.h @@ -239,10 +239,10 @@ struct mxs_apbh_regs { #endif -#define APBH_CTRL0_SFTRST (1 << 31) -#define APBH_CTRL0_CLKGATE (1 << 30) -#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) -#define APBH_CTRL0_APB_BURST_EN (1 << 28) +#define APBH_CTRL0_SFTRST BIT(31) +#define APBH_CTRL0_CLKGATE BIT(30) +#define APBH_CTRL0_AHB_BURST8_EN BIT(29) +#define APBH_CTRL0_APB_BURST_EN BIT(28) #if defined(CONFIG_MX23) #define APBH_CTRL0_RSVD0_MASK (0xf << 24) #define APBH_CTRL0_RSVD0_OFFSET 24 @@ -288,73 +288,73 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 #endif -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN BIT(31) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN BIT(30) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN BIT(29) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN BIT(28) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN BIT(27) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN BIT(26) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN BIT(25) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN BIT(24) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN BIT(23) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN BIT(22) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN BIT(21) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN BIT(20) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN BIT(19) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN BIT(18) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN BIT(17) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN BIT(16) #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ BIT(15) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ BIT(14) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ BIT(13) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ BIT(12) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ BIT(11) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ BIT(10) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ BIT(9) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ BIT(8) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ BIT(7) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ BIT(6) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ BIT(5) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ BIT(4) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ BIT(3) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ BIT(2) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ BIT(1) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ BIT(0) -#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) -#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) -#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) -#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) -#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) -#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) -#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) -#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) -#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) -#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) -#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) -#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) -#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) -#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) -#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) -#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) -#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) -#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) -#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) -#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) -#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) -#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) -#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) -#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) -#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) -#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) -#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) -#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) -#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) -#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) -#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) -#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) +#define APBH_CTRL2_CH15_ERROR_STATUS BIT(31) +#define APBH_CTRL2_CH14_ERROR_STATUS BIT(30) +#define APBH_CTRL2_CH13_ERROR_STATUS BIT(29) +#define APBH_CTRL2_CH12_ERROR_STATUS BIT(28) +#define APBH_CTRL2_CH11_ERROR_STATUS BIT(27) +#define APBH_CTRL2_CH10_ERROR_STATUS BIT(26) +#define APBH_CTRL2_CH9_ERROR_STATUS BIT(25) +#define APBH_CTRL2_CH8_ERROR_STATUS BIT(24) +#define APBH_CTRL2_CH7_ERROR_STATUS BIT(23) +#define APBH_CTRL2_CH6_ERROR_STATUS BIT(22) +#define APBH_CTRL2_CH5_ERROR_STATUS BIT(21) +#define APBH_CTRL2_CH4_ERROR_STATUS BIT(20) +#define APBH_CTRL2_CH3_ERROR_STATUS BIT(19) +#define APBH_CTRL2_CH2_ERROR_STATUS BIT(18) +#define APBH_CTRL2_CH1_ERROR_STATUS BIT(17) +#define APBH_CTRL2_CH0_ERROR_STATUS BIT(16) +#define APBH_CTRL2_CH15_ERROR_IRQ BIT(15) +#define APBH_CTRL2_CH14_ERROR_IRQ BIT(14) +#define APBH_CTRL2_CH13_ERROR_IRQ BIT(13) +#define APBH_CTRL2_CH12_ERROR_IRQ BIT(12) +#define APBH_CTRL2_CH11_ERROR_IRQ BIT(11) +#define APBH_CTRL2_CH10_ERROR_IRQ BIT(10) +#define APBH_CTRL2_CH9_ERROR_IRQ BIT(9) +#define APBH_CTRL2_CH8_ERROR_IRQ BIT(8) +#define APBH_CTRL2_CH7_ERROR_IRQ BIT(7) +#define APBH_CTRL2_CH6_ERROR_IRQ BIT(6) +#define APBH_CTRL2_CH5_ERROR_IRQ BIT(5) +#define APBH_CTRL2_CH4_ERROR_IRQ BIT(4) +#define APBH_CTRL2_CH3_ERROR_IRQ BIT(3) +#define APBH_CTRL2_CH2_ERROR_IRQ BIT(2) +#define APBH_CTRL2_CH1_ERROR_IRQ BIT(1) +#define APBH_CTRL2_CH0_ERROR_IRQ BIT(0) #if defined(CONFIG_MX28) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) @@ -498,7 +498,7 @@ struct mxs_apbh_regs { #define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 #define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 -#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) +#define APBH_DEBUG_GPMI_ONE_FIFO BIT(0) #endif #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff @@ -511,13 +511,13 @@ struct mxs_apbh_regs { #define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 #define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) #define APBH_CHn_CMD_CMDWORDS_OFFSET 12 -#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) -#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) -#define APBH_CHn_CMD_SEMAPHORE (1 << 6) -#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) -#define APBH_CHn_CMD_NANDLOCK (1 << 4) -#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) -#define APBH_CHn_CMD_CHAIN (1 << 2) +#define APBH_CHn_CMD_HALTONTERMINATE BIT(8) +#define APBH_CHn_CMD_WAIT4ENDCMD BIT(7) +#define APBH_CHn_CMD_SEMAPHORE BIT(6) +#define APBH_CHn_CMD_NANDWAIT4READY BIT(5) +#define APBH_CHn_CMD_NANDLOCK BIT(4) +#define APBH_CHn_CMD_IRQONCMPLT BIT(3) +#define APBH_CHn_CMD_CHAIN BIT(2) #define APBH_CHn_CMD_COMMAND_MASK 0x3 #define APBH_CHn_CMD_COMMAND_OFFSET 0 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 @@ -537,18 +537,18 @@ struct mxs_apbh_regs { #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 -#define APBH_CHn_DEBUG1_REQ (1 << 31) -#define APBH_CHn_DEBUG1_BURST (1 << 30) -#define APBH_CHn_DEBUG1_KICK (1 << 29) -#define APBH_CHn_DEBUG1_END (1 << 28) -#define APBH_CHn_DEBUG1_SENSE (1 << 27) -#define APBH_CHn_DEBUG1_READY (1 << 26) -#define APBH_CHn_DEBUG1_LOCK (1 << 25) -#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) -#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) -#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) -#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) -#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) +#define APBH_CHn_DEBUG1_REQ BIT(31) +#define APBH_CHn_DEBUG1_BURST BIT(30) +#define APBH_CHn_DEBUG1_KICK BIT(29) +#define APBH_CHn_DEBUG1_END BIT(28) +#define APBH_CHn_DEBUG1_SENSE BIT(27) +#define APBH_CHn_DEBUG1_READY BIT(26) +#define APBH_CHn_DEBUG1_LOCK BIT(25) +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID BIT(24) +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY BIT(23) +#define APBH_CHn_DEBUG1_RD_FIFO_FULL BIT(22) +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY BIT(21) +#define APBH_CHn_DEBUG1_WR_FIFO_FULL BIT(20) #define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) #define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index a33d341..5f5a536 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -44,18 +44,18 @@ struct mxs_bch_regs { }; #endif -#define BCH_CTRL_SFTRST (1 << 31) -#define BCH_CTRL_CLKGATE (1 << 30) -#define BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BCH_CTRL_SFTRST BIT(31) +#define BCH_CTRL_CLKGATE BIT(30) +#define BCH_CTRL_DEBUGSYNDROME BIT(22) #define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) #define BCH_CTRL_M2M_LAYOUT_OFFSET 18 -#define BCH_CTRL_M2M_ENCODE (1 << 17) -#define BCH_CTRL_M2M_ENABLE (1 << 16) -#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) -#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) -#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) -#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) -#define BCH_CTRL_COMPLETE_IRQ (1 << 0) +#define BCH_CTRL_M2M_ENCODE BIT(17) +#define BCH_CTRL_M2M_ENABLE BIT(16) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN BIT(10) +#define BCH_CTRL_COMPLETE_IRQ_EN BIT(8) +#define BCH_CTRL_BM_ERROR_IRQ BIT(3) +#define BCH_CTRL_DEBUG_STALL_IRQ BIT(2) +#define BCH_CTRL_COMPLETE_IRQ BIT(0) #define BCH_STATUS0_HANDLE_MASK (0xfff << 20) #define BCH_STATUS0_HANDLE_OFFSET 20 @@ -70,9 +70,9 @@ struct mxs_bch_regs { #define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) #define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) #define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) -#define BCH_STATUS0_ALLONES (1 << 4) -#define BCH_STATUS0_CORRECTED (1 << 3) -#define BCH_STATUS0_UNCORRECTABLE (1 << 2) +#define BCH_STATUS0_ALLONES BIT(4) +#define BCH_STATUS0_CORRECTED BIT(3) +#define BCH_STATUS0_UNCORRECTABLE BIT(2) #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 @@ -147,7 +147,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 BIT(10) #define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 @@ -177,26 +177,26 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 BIT(10) #define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 #define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) #define BCH_DEBUG0_RSVD1_OFFSET 27 -#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) -#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BCH_DEBUG0_ROM_BIST_ENABLE BIT(26) +#define BCH_DEBUG0_ROM_BIST_COMPLETE BIT(25) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) -#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) -#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) -#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) -#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) -#define BCH_DEBUG0_KES_STANDALONE (1 << 11) -#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) -#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) -#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND BIT(15) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG BIT(14) +#define BCH_DEBUG0_KES_DEBUG_MODE4K BIT(13) +#define BCH_DEBUG0_KES_DEBUG_KICK BIT(12) +#define BCH_DEBUG0_KES_STANDALONE BIT(11) +#define BCH_DEBUG0_KES_DEBUG_STEP BIT(10) +#define BCH_DEBUG0_KES_DEBUG_STALL BIT(9) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS BIT(8) #define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) #define BCH_DEBUG0_RSVD0_OFFSET 6 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f diff --git a/arch/arm/include/asm/imx-common/regs-gpmi.h b/arch/arm/include/asm/imx-common/regs-gpmi.h index b93bfe5..47b7d77 100644 --- a/arch/arm/include/asm/imx-common/regs-gpmi.h +++ b/arch/arm/include/asm/imx-common/regs-gpmi.h @@ -36,19 +36,19 @@ struct mxs_gpmi_regs { }; #endif -#define GPMI_CTRL0_SFTRST (1 << 31) -#define GPMI_CTRL0_CLKGATE (1 << 30) -#define GPMI_CTRL0_RUN (1 << 29) -#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) -#define GPMI_CTRL0_LOCK_CS (1 << 27) -#define GPMI_CTRL0_UDMA (1 << 26) +#define GPMI_CTRL0_SFTRST BIT(31) +#define GPMI_CTRL0_CLKGATE BIT(30) +#define GPMI_CTRL0_RUN BIT(29) +#define GPMI_CTRL0_DEV_IRQ_EN BIT(28) +#define GPMI_CTRL0_LOCK_CS BIT(27) +#define GPMI_CTRL0_UDMA BIT(26) #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) #define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 #define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) #define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) #define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) #define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) -#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_WORD_LENGTH BIT(23) #define GPMI_CTRL0_CS_MASK (0x7 << 20) #define GPMI_CTRL0_CS_OFFSET 20 #define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) @@ -56,7 +56,7 @@ struct mxs_gpmi_regs { #define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) #define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) #define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) -#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define GPMI_CTRL0_ADDRESS_INCREMENT BIT(16) #define GPMI_CTRL0_XFER_COUNT_MASK 0xffff #define GPMI_CTRL0_XFER_COUNT_OFFSET 0 @@ -71,7 +71,7 @@ struct mxs_gpmi_regs { #define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 #define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) #define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) -#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define GPMI_ECCCTRL_ENABLE_ECC BIT(12) #define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff #define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 @@ -86,27 +86,27 @@ struct mxs_gpmi_regs { #define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) #define GPMI_AUXILIARY_ADDRESS_OFFSET 2 -#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define GPMI_CTRL1_DECOUPLE_CS BIT(24) #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 -#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) -#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) -#define GPMI_CTRL1_BCH_MODE (1 << 18) -#define GPMI_CTRL1_DLL_ENABLE (1 << 17) -#define GPMI_CTRL1_HALF_PERIOD (1 << 16) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN BIT(20) +#define GPMI_CTRL1_GANGED_RDYBUSY BIT(19) +#define GPMI_CTRL1_BCH_MODE BIT(18) +#define GPMI_CTRL1_DLL_ENABLE BIT(17) +#define GPMI_CTRL1_HALF_PERIOD BIT(16) #define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) #define GPMI_CTRL1_RDN_DELAY_OFFSET 12 -#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) -#define GPMI_CTRL1_DEV_IRQ (1 << 10) -#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) -#define GPMI_CTRL1_BURST_EN (1 << 8) -#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define GPMI_CTRL1_DMA2ECC_MODE BIT(11) +#define GPMI_CTRL1_DEV_IRQ BIT(10) +#define GPMI_CTRL1_TIMEOUT_IRQ BIT(9) +#define GPMI_CTRL1_BURST_EN BIT(8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST BIT(7) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 -#define GPMI_CTRL1_DEV_RESET (1 << 3) -#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) -#define GPMI_CTRL1_CAMERA_MODE (1 << 1) -#define GPMI_CTRL1_GPMI_MODE (1 << 0) +#define GPMI_CTRL1_DEV_RESET BIT(3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY BIT(2) +#define GPMI_CTRL1_CAMERA_MODE BIT(1) +#define GPMI_CTRL1_GPMI_MODE BIT(0) #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 @@ -134,19 +134,19 @@ struct mxs_gpmi_regs { #define GPMI_STAT_READY_BUSY_OFFSET 24 #define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) #define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 -#define GPMI_STAT_DEV7_ERROR (1 << 15) -#define GPMI_STAT_DEV6_ERROR (1 << 14) -#define GPMI_STAT_DEV5_ERROR (1 << 13) -#define GPMI_STAT_DEV4_ERROR (1 << 12) -#define GPMI_STAT_DEV3_ERROR (1 << 11) -#define GPMI_STAT_DEV2_ERROR (1 << 10) -#define GPMI_STAT_DEV1_ERROR (1 << 9) -#define GPMI_STAT_DEV0_ERROR (1 << 8) -#define GPMI_STAT_ATA_IRQ (1 << 4) -#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) -#define GPMI_STAT_FIFO_EMPTY (1 << 2) -#define GPMI_STAT_FIFO_FULL (1 << 1) -#define GPMI_STAT_PRESENT (1 << 0) +#define GPMI_STAT_DEV7_ERROR BIT(15) +#define GPMI_STAT_DEV6_ERROR BIT(14) +#define GPMI_STAT_DEV5_ERROR BIT(13) +#define GPMI_STAT_DEV4_ERROR BIT(12) +#define GPMI_STAT_DEV3_ERROR BIT(11) +#define GPMI_STAT_DEV2_ERROR BIT(10) +#define GPMI_STAT_DEV1_ERROR BIT(9) +#define GPMI_STAT_DEV0_ERROR BIT(8) +#define GPMI_STAT_ATA_IRQ BIT(4) +#define GPMI_STAT_INVALID_BUFFER_MASK BIT(3) +#define GPMI_STAT_FIFO_EMPTY BIT(2) +#define GPMI_STAT_FIFO_FULL BIT(1) +#define GPMI_STAT_PRESENT BIT(0) #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) #define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 @@ -166,7 +166,7 @@ struct mxs_gpmi_regs { #define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) #define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 -#define GPMI_DEBUG2_BUSY (1 << 23) +#define GPMI_DEBUG2_BUSY BIT(23) #define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) #define GPMI_DEBUG2_PIN_STATE_OFFSET 20 #define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) @@ -192,12 +192,12 @@ struct mxs_gpmi_regs { #define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) #define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 -#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) -#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) -#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) -#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) -#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) -#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define GPMI_DEBUG2_GPMI2SYND_VALID BIT(11) +#define GPMI_DEBUG2_GPMI2SYND_READY BIT(10) +#define GPMI_DEBUG2_SYND2GPMI_VALID BIT(9) +#define GPMI_DEBUG2_SYND2GPMI_READY BIT(8) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN BIT(7) +#define GPMI_DEBUG2_UPDATE_WINDOW BIT(6) #define GPMI_DEBUG2_RDN_TAP_MASK 0x3f #define GPMI_DEBUG2_RDN_TAP_OFFSET 0 diff --git a/arch/arm/include/asm/imx-common/regs-usbphy.h b/arch/arm/include/asm/imx-common/regs-usbphy.h index 220e45f..591becc 100644 --- a/arch/arm/include/asm/imx-common/regs-usbphy.h +++ b/arch/arm/include/asm/imx-common/regs-usbphy.h @@ -17,10 +17,10 @@ #define USBPHY_RX 0x00000020 #define USBPHY_DEBUG 0x00000050 -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_OTG_ID (1 << 27) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_ENUTMILEVEL2 BIT(14) +#define USBPHY_CTRL_ENUTMILEVEL3 BIT(15) +#define USBPHY_CTRL_OTG_ID BIT(27) +#define USBPHY_CTRL_CLKGATE BIT(30) +#define USBPHY_CTRL_SFTRST BIT(31) #endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 3cf3307..b09a3d4 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -185,8 +185,8 @@ lr .req x30 msr cpacr_el1, \xreg1 /* Enable FP/SIMD at EL1 */ /* Initialize HCR_EL2 */ - mov \xreg1, #(1 << 31) /* 64bit EL1 */ - orr \xreg1, \xreg1, #(1 << 29) /* Disable HVC */ + mov \xreg1, #BIT(31) /* 64bit EL1 */ + orr \xreg1, \xreg1, #BIT(29) /* Disable HVC */ msr hcr_el2, \xreg1 /* SCTLR_EL1 initialization diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 617e22f..44b64cc 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -139,8 +139,8 @@ struct hsmmc { #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) +#define VS30_3V0SUP BIT(25) +#define VS18_1V8SUP BIT(26) /* Driver definitions */ #define MMCSD_SECTOR_SIZE 512 diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index ddc245b..88f27f3 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -11,9 +11,9 @@ #include /* Register bit fields */ -#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) -#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) -#define L2X0_STNDBY_MODE_EN (1 << 0) +#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK BIT(16) +#define L2X0_DYNAMIC_CLK_GATING_EN BIT(1) +#define L2X0_STNDBY_MODE_EN BIT(0) #define L2X0_CTRL_EN 1 struct pl310_regs { diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 71df5a9..9db6f65 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -46,10 +46,10 @@ struct pt_regs { #define F_BIT 0x40 #define I_BIT 0x80 #define A_BIT 0x100 -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) +#define CC_V_BIT BIT(28) +#define CC_C_BIT BIT(29) +#define CC_Z_BIT BIT(30) +#define CC_N_BIT BIT(31) #define PCMASK 0 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2..d7d9aee 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -6,13 +6,13 @@ /* * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_WXN (1 << 19) /* Write Permision Imply XN */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_M BIT(0) /* MMU enable */ +#define CR_A BIT(1) /* Alignment abort enable */ +#define CR_C BIT(2) /* Dcache enable */ +#define CR_SA BIT(3) /* Stack Alignment Check Enable */ +#define CR_I BIT(12) /* Icache enable */ +#define CR_WXN BIT(19) /* Write Permision Imply XN */ +#define CR_EE BIT(25) /* Exception (Big) Endian */ #define PGTABLE_SIZE (0x10000) @@ -101,33 +101,33 @@ void flush_l3_cache(void); /* * CR1 bits (CP#15 CR1) */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CR_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CR_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ -#define CR_L4 (1 << 15) /* LDR pc can set T bit */ -#define CR_DT (1 << 16) -#define CR_IT (1 << 18) -#define CR_ST (1 << 19) -#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ -#define CR_U (1 << 22) /* Unaligned access operation */ -#define CR_XP (1 << 23) /* Extended page tables */ -#define CR_VE (1 << 24) /* Vectored interrupts */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ -#define CR_TRE (1 << 28) /* TEX remap enable */ -#define CR_AFE (1 << 29) /* Access flag enable */ -#define CR_TE (1 << 30) /* Thumb exception enable */ +#define CR_M BIT(0) /* MMU enable */ +#define CR_A BIT(1) /* Alignment abort enable */ +#define CR_C BIT(2) /* Dcache enable */ +#define CR_W BIT(3) /* Write buffer enable */ +#define CR_P BIT(4) /* 32-bit exception handler */ +#define CR_D BIT(5) /* 32-bit data address range */ +#define CR_L BIT(6) /* Implementation defined */ +#define CR_B BIT(7) /* Big endian */ +#define CR_S BIT(8) /* System MMU protection */ +#define CR_R BIT(9) /* ROM MMU protection */ +#define CR_F BIT(10) /* Implementation defined */ +#define CR_Z BIT(11) /* Implementation defined */ +#define CR_I BIT(12) /* Icache enable */ +#define CR_V BIT(13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR BIT(14) /* Round Robin cache replacement */ +#define CR_L4 BIT(15) /* LDR pc can set T bit */ +#define CR_DT BIT(16) +#define CR_IT BIT(18) +#define CR_ST BIT(19) +#define CR_FI BIT(21) /* Fast interrupt (lower latency mode) */ +#define CR_U BIT(22) /* Unaligned access operation */ +#define CR_XP BIT(23) /* Extended page tables */ +#define CR_VE BIT(24) /* Vectored interrupts */ +#define CR_EE BIT(25) /* Exception (Big) Endian */ +#define CR_TRE BIT(28) /* TEX remap enable */ +#define CR_AFE BIT(29) /* Access flag enable */ +#define CR_TE BIT(30) /* Thumb exception enable */ #define PGTABLE_SIZE (4096 * 4) diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 11407be..46b9484 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -76,13 +76,13 @@ struct davinci_emif_regs { #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) +#define DAVINCI_NANDFCR_4BIT_ECC_START BIT(12) +#define DAVINCI_NANDFCR_4BIT_CALC_START BIT(13) +#define DAVINCI_NANDFCR_CS2NAND BIT(0) /* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_STROBE_SELECT BIT(31) +#define DAVINCI_ABCR_EXT_WAIT BIT(30) #define DAVINCI_ABCR_WSETUP(n) (n << 26) #define DAVINCI_ABCR_WSTROBE(n) (n << 20) #define DAVINCI_ABCR_WHOLD(n) (n << 17) diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h index 696d8c6..d7558ce 100644 --- a/arch/arm/include/asm/ti-common/keystone_nav.h +++ b/arch/arm/include/asm/ti-common/keystone_nav.h @@ -122,7 +122,7 @@ void queue_close(u32 qnum); ((fd1qnum & 0xfff) << 0)) #define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) -#define CPDMA_CHAN_A_TDOWN (1 << 30) +#define CPDMA_CHAN_A_TDOWN BIT(30) #define TDOWN_TIMEOUT_COUNT 100 struct global_ctl_regs { diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h index 5adc1da..1062405 100644 --- a/arch/arm/include/asm/ti-common/ti-edma3.h +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -26,7 +26,7 @@ #define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20) #define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12) #define EDMA3_SLOPT_FIFO_WIDTH_8 0 -#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_16 BIT(8) #define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8) #define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8) #define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8) diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index 6015493..06ba485 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -72,20 +72,20 @@ #else - cmp \divisor, #(1 << 16) + cmp \divisor, #BIT(16) movhs \divisor, \divisor, lsr #16 movhs \order, #16 movlo \order, #0 - cmp \divisor, #(1 << 8) + cmp \divisor, #BIT(8) movhs \divisor, \divisor, lsr #8 addhs \order, \order, #8 - cmp \divisor, #(1 << 4) + cmp \divisor, #BIT(4) movhs \divisor, \divisor, lsr #4 addhs \order, \order, #4 - cmp \divisor, #(1 << 2) + cmp \divisor, #BIT(2) addhi \order, \order, #3 addls \order, \order, \divisor, lsr #1 diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index a3e18f7..b547a28 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -93,7 +93,7 @@ ENTRY(gic_init_secure_percpu) 3: ldr w10, [x9, GICR_WAKER] tbnz w10, #2, 3b /* Wait Children be Alive */ - add x10, x9, #(1 << 16) /* SGI_Base */ + add x10, x9, #BIT(16) /* SGI_Base */ mov w11, #~0 str w11, [x10, GICR_IGROUPRn] str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */ diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 7208f20..7311edd 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -84,7 +84,7 @@ ENTRY(memset) movs r8, r8, lsl #(32 - 4) stmiacs ip!, {r4, r5, r6, r7} stmiami ip!, {r4, r5} - tst r8, #(1 << 30) + tst r8, #BIT(30) mov r8, r1 strne r1, [ip], #4 diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 475d503..a65dd32 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -51,7 +51,7 @@ ENTRY(relocate_vectors) */ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */ - ands r2, r2, #(1 << 13) + ands r2, r2, #BIT(13) ldreq r1, =0x00000000 /* If V=0 */ ldrne r1, =0xFFFF0000 /* If V=1 */ ldmia r0!, {r2-r8,r10} diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index efb53d6..4aac250 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -78,28 +78,28 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTC, 11, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_b_periph(AT91_PIO_PORTC, 16, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_b_periph(AT91_PIO_PORTC, 17, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTC, 11, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTC, 16, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTC, 17, 1); } } @@ -115,28 +115,28 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTC, 5, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_b_periph(AT91_PIO_PORTC, 4, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_b_periph(AT91_PIO_PORTC, 3, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTC, 5, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTC, 4, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTC, 3, 1); } } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index a445c75..94d9db5 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -75,28 +75,28 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_a_periph(AT91_PIO_PORTA, 4, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_a_periph(AT91_PIO_PORTA, 5, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_a_periph(AT91_PIO_PORTA, 6, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTA, 4, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTA, 5, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTA, 6, 1); } } @@ -112,28 +112,28 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTA, 24, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_b_periph(AT91_PIO_PORTA, 25, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_a_periph(AT91_PIO_PORTA, 26, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTB, 28, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTA, 24, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTA, 25, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTA, 26, 1); } } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 6b51d5f..654edd6 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -79,28 +79,28 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_b_periph(AT91_PIO_PORTA, 4, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_b_periph(AT91_PIO_PORTB, 11, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTA, 5, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTA, 3, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTA, 4, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTB, 11, 1); } } @@ -116,28 +116,28 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_a_periph(AT91_PIO_PORTB, 16, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_a_periph(AT91_PIO_PORTB, 18, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTB, 15, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTB, 16, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 0e6c0da..dabc5b3 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -75,28 +75,28 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTB, 18, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_b_periph(AT91_PIO_PORTB, 19, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_b_periph(AT91_PIO_PORTD, 27, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTB, 19, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTD, 27, 1); } } @@ -112,28 +112,28 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTD, 28, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_a_periph(AT91_PIO_PORTD, 18, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_a_periph(AT91_PIO_PORTD, 19, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTD, 28, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTD, 18, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTD, 19, 1); } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 39f17a1..fcf2a91 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -73,13 +73,13 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) + if (cs_mask & BIT(0)) at91_set_pio_output(AT91_PIO_PORTA, 14, 1); - if (cs_mask & (1 << 1)) + if (cs_mask & BIT(1)) at91_set_pio_output(AT91_PIO_PORTA, 7, 1); - if (cs_mask & (1 << 2)) + if (cs_mask & BIT(2)) at91_set_pio_output(AT91_PIO_PORTA, 1, 1); - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } @@ -94,13 +94,13 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) + if (cs_mask & BIT(0)) at91_set_pio_output(AT91_PIO_PORTA, 8, 1); - if (cs_mask & (1 << 1)) + if (cs_mask & BIT(1)) at91_set_pio_output(AT91_PIO_PORTA, 0, 1); - if (cs_mask & (1 << 2)) + if (cs_mask & BIT(2)) at91_set_pio_output(AT91_PIO_PORTA, 31, 1); - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) at91_set_pio_output(AT91_PIO_PORTA, 30, 1); } #endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index 857c864..1f34423 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -75,28 +75,28 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI, &pmc->pcer); - if (cs_mask & (1 << 0)) { + if (cs_mask & BIT(0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); } - if (cs_mask & (1 << 1)) { + if (cs_mask & BIT(1)) { at91_set_b_periph(AT91_PIO_PORTB, 7, 1); } - if (cs_mask & (1 << 2)) { + if (cs_mask & BIT(2)) { at91_set_a_periph(AT91_PIO_PORTD, 8, 1); } - if (cs_mask & (1 << 3)) { + if (cs_mask & BIT(3)) { at91_set_b_periph(AT91_PIO_PORTD, 9, 1); } - if (cs_mask & (1 << 4)) { + if (cs_mask & BIT(4)) { at91_set_pio_output(AT91_PIO_PORTA, 28, 1); } - if (cs_mask & (1 << 5)) { + if (cs_mask & BIT(5)) { at91_set_pio_output(AT91_PIO_PORTB, 7, 1); } - if (cs_mask & (1 << 6)) { + if (cs_mask & BIT(6)) { at91_set_pio_output(AT91_PIO_PORTD, 8, 1); } - if (cs_mask & (1 << 7)) { + if (cs_mask & BIT(7)) { at91_set_pio_output(AT91_PIO_PORTD, 9, 1); } } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 6d94572..d4a3383 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -129,21 +129,21 @@ void at91_spi0_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - if (cs_mask & (1 << 0)) + if (cs_mask & BIT(0)) at91_set_a_periph(AT91_PIO_PORTA, 14, 0); - if (cs_mask & (1 << 1)) + if (cs_mask & BIT(1)) at91_set_b_periph(AT91_PIO_PORTA, 7, 0); - if (cs_mask & (1 << 2)) + if (cs_mask & BIT(2)) at91_set_b_periph(AT91_PIO_PORTA, 1, 0); - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) at91_set_b_periph(AT91_PIO_PORTB, 3, 0); - if (cs_mask & (1 << 4)) + if (cs_mask & BIT(4)) at91_set_pio_output(AT91_PIO_PORTA, 14, 0); - if (cs_mask & (1 << 5)) + if (cs_mask & BIT(5)) at91_set_pio_output(AT91_PIO_PORTA, 7, 0); - if (cs_mask & (1 << 6)) + if (cs_mask & BIT(6)) at91_set_pio_output(AT91_PIO_PORTA, 1, 0); - if (cs_mask & (1 << 7)) + if (cs_mask & BIT(7)) at91_set_pio_output(AT91_PIO_PORTB, 3, 0); } @@ -158,21 +158,21 @@ void at91_spi1_hw_init(unsigned long cs_mask) /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - if (cs_mask & (1 << 0)) + if (cs_mask & BIT(0)) at91_set_b_periph(AT91_PIO_PORTA, 8, 0); - if (cs_mask & (1 << 1)) + if (cs_mask & BIT(1)) at91_set_b_periph(AT91_PIO_PORTA, 0, 0); - if (cs_mask & (1 << 2)) + if (cs_mask & BIT(2)) at91_set_b_periph(AT91_PIO_PORTA, 31, 0); - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) at91_set_b_periph(AT91_PIO_PORTA, 30, 0); - if (cs_mask & (1 << 4)) + if (cs_mask & BIT(4)) at91_set_pio_output(AT91_PIO_PORTA, 8, 0); - if (cs_mask & (1 << 5)) + if (cs_mask & BIT(5)) at91_set_pio_output(AT91_PIO_PORTA, 0, 0); - if (cs_mask & (1 << 6)) + if (cs_mask & BIT(6)) at91_set_pio_output(AT91_PIO_PORTA, 31, 0); - if (cs_mask & (1 << 7)) + if (cs_mask & BIT(7)) at91_set_pio_output(AT91_PIO_PORTA, 30, 0); } #endif diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 0bf453e..b316f5a 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -83,7 +83,7 @@ int at91_clock_init(unsigned long main_clock) mckr = readl(&pmc->mckr); /* plla divisor by 2 */ - if (mckr & (1 << 12)) + if (mckr & BIT(12)) gd->arch.plla_rate_hz >>= 1; gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 78ecfc8..cfaf2a4 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -94,13 +94,13 @@ void at91_spi0_hw_init(unsigned long cs_mask) at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ - if (cs_mask & (1 << 0)) + if (cs_mask & BIT(0)) at91_set_pio_output(AT91_PIO_PORTD, 13, 1); - if (cs_mask & (1 << 1)) + if (cs_mask & BIT(1)) at91_set_pio_output(AT91_PIO_PORTD, 14, 1); - if (cs_mask & (1 << 2)) + if (cs_mask & BIT(2)) at91_set_pio_output(AT91_PIO_PORTD, 15, 1); - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) at91_set_pio_output(AT91_PIO_PORTD, 16, 1); /* Enable clock */ diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h index 2379dd4..682c817 100644 --- a/arch/arm/mach-at91/include/mach/at91_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91_matrix.h @@ -99,9 +99,9 @@ typedef struct at91_matrix { #if defined CONFIG_AT91SAM9261 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_MCFG_RCB0 (1 << 0) +#define AT91_MATRIX_MCFG_RCB0 BIT(0) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_MCFG_RCB1 (1 << 1) +#define AT91_MATRIX_MCFG_RCB1 BIT(1) #endif /* Undefined Length Burst Type */ @@ -149,9 +149,9 @@ typedef struct at91_matrix { #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ defined(CONFIG_AT91SAM9G45) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_MRCR_RCB0 (1 << 0) +#define AT91_MATRIX_MRCR_RCB0 BIT(0) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_MRCR_RCB1 (1 << 1) +#define AT91_MATRIX_MRCR_RCB1 BIT(1) #endif #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) #define AT91_MATRIX_MRCR_RCB2 0x00000004 diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index ebb7dec..5acdac8 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -73,7 +73,7 @@ typedef struct at91_pmc { #define AT91_PMC_MOR_MOSCRCEN 0x08 #define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) #define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16) -#define AT91_PMC_MOR_MOSCSEL (1 << 24) +#define AT91_PMC_MOR_MOSCSEL BIT(24) #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) @@ -164,10 +164,10 @@ typedef struct at91_pmc { #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#define AT91_PMC_PCK2 BIT(10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 BIT(11) /* Programmable Clock 3 */ +#define AT91_PMC_HCK0 BIT(16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 BIT(17) /* AHB Clock (LCD) [AT91SAM9261 only] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ @@ -187,19 +187,19 @@ typedef struct at91_pmc { #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ #define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_2 BIT(28) #define AT91_PMC_USBDIV_4 (2 << 28) #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_MAIN BIT(0) #define AT91_PMC_CSS_PLLA (2 << 0) #define AT91_PMC_CSS_PLLB (3 << 0) #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ #define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_2 BIT(2) #define AT91_PMC_PRES_4 (2 << 2) #define AT91_PMC_PRES_8 (3 << 2) #define AT91_PMC_PRES_16 (4 << 2) @@ -207,17 +207,17 @@ typedef struct at91_pmc { #define AT91_PMC_PRES_64 (6 << 2) #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_2 BIT(8) #define AT91RM9200_PMC_MDIV_3 (2 << 8) #define AT91RM9200_PMC_MDIV_4 (3 << 8) #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_2 BIT(8) #define AT91SAM9_PMC_MDIV_4 (2 << 8) #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ #define AT91SAM9_PMC_MDIV_6 (3 << 8) -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV BIT(12) /* Processor Clock Division [some SAM9 only] */ #define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PDIV_2 BIT(12) #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ @@ -233,8 +233,8 @@ typedef struct at91_pmc { #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_PCK2RDY BIT(10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY BIT(11) /* Programmable Clock 3 */ #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ #endif diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h index e4eb3da..f7e07e0 100644 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h @@ -42,7 +42,7 @@ typedef struct at91_rstc { #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP BIT(8) #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) #define AT91_RSTC_RSTTYP_USER (4 << 8) diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h index b18665b..2e69fc4 100644 --- a/arch/arm/mach-at91/include/mach/at91_spi.h +++ b/arch/arm/mach-at91/include/mach/at91_spi.h @@ -36,13 +36,13 @@ typedef struct at91_spi { #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ +#define AT91_SPI_LASTXFER BIT(24) /* Last Transfer [SAM9261 only] */ #define AT91_SPI_MR 0x04 /* Mode Register */ #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ #define AT91_SPI_PS_FIXED (0 << 1) -#define AT91_SPI_PS_VARIABLE (1 << 1) +#define AT91_SPI_PS_VARIABLE BIT(1) #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ @@ -70,7 +70,7 @@ typedef struct at91_spi { #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ -#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ +#define AT91_SPI_SPIENS BIT(16) /* SPI Enable Status */ #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ @@ -82,7 +82,7 @@ typedef struct at91_spi { #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ #define AT91_SPI_BITS_8 (0 << 4) -#define AT91_SPI_BITS_9 (1 << 4) +#define AT91_SPI_BITS_9 BIT(4) #define AT91_SPI_BITS_10 (2 << 4) #define AT91_SPI_BITS_11 (3 << 4) #define AT91_SPI_BITS_12 (4 << 4) diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h index dc61f48..2d37b84 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h @@ -32,17 +32,17 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY BIT(24) #define AT91_MATRIX_M0PR_SHIFT 0 #define AT91_MATRIX_M1PR_SHIFT 4 @@ -51,17 +51,17 @@ struct at91_matrix { #define AT91_MATRIX_M4PR_SHIFT 16 #define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_CS1A_SDRAMC BIT(1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA BIT(3) +#define AT91_MATRIX_CS4A_SMC_CF1 BIT(4) +#define AT91_MATRIX_CS5A_SMC_CF2 BIT(5) +#define AT91_MATRIX_DBPUC BIT(8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) +#define AT91_MATRIX_VDDIOMSEL_3_3V BIT(16) +#define AT91_MATRIX_EBI_IOSR_SEL BIT(17) /* Maximum Number of Allowed Cycles for a Burst */ #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h index fc5f083..e70d6bd 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h @@ -23,17 +23,17 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY BIT(24) #define AT91_MATRIX_M0PR_SHIFT 0 #define AT91_MATRIX_M1PR_SHIFT 4 @@ -42,15 +42,15 @@ struct at91_matrix { #define AT91_MATRIX_M4PR_SHIFT 16 #define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_CS1A_SDRAMC BIT(1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA BIT(3) +#define AT91_MATRIX_CS4A_SMC_CF1 BIT(4) +#define AT91_MATRIX_CS5A_SMC_CF2 BIT(5) +#define AT91_MATRIX_DBPUC BIT(8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V BIT(16) #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h index 54d8622..a97a67f 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h @@ -31,17 +31,17 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY BIT(24) #define AT91_MATRIX_M0PR_SHIFT 0 #define AT91_MATRIX_M1PR_SHIFT 4 @@ -50,15 +50,15 @@ struct at91_matrix { #define AT91_MATRIX_M4PR_SHIFT 16 #define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_CS1A_SDRAMC BIT(1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA BIT(3) +#define AT91_MATRIX_CS4A_SMC_CF1 BIT(4) +#define AT91_MATRIX_CS5A_SMC_CF2 BIT(5) +#define AT91_MATRIX_DBPUC BIT(8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V BIT(16) #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 3a076c6..f5cf686 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -59,23 +59,23 @@ int sdramc_initialize(unsigned int sdram_address, #define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ #define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_9 BIT(0) #define AT91_SDRAMC_NC_10 (2 << 0) #define AT91_SDRAMC_NC_11 (3 << 0) #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ #define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_12 BIT(2) #define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB BIT(4) /* Number of Banks */ #define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_NB_4 BIT(4) #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) +#define AT91_SDRAMC_CAS_1 BIT(5) #define AT91_SDRAMC_CAS_2 (2 << 5) #define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ +#define AT91_SDRAMC_DBW BIT(7) /* Data Bus Width */ #define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) +#define AT91_SDRAMC_DBW_16 BIT(7) #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ #define AT91_SDRAMC_TWR_VAL(x) (x << 8) #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ @@ -100,14 +100,14 @@ int sdramc_initialize(unsigned int sdram_address, #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES BIT(12) #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) #define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ #define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ #define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ #define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ +#define AT91_SDRAMC_RES BIT(0) /* Refresh Error Status */ #define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */ #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h index 80e49e3..36154ca 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h @@ -33,7 +33,7 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) @@ -42,7 +42,7 @@ struct at91_matrix { #define AT91_MATRIX_ULBT_128 (7 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 @@ -60,33 +60,33 @@ struct at91_matrix { #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) +#define AT91_MATRIX_RCB2 BIT(2) +#define AT91_MATRIX_RCB3 BIT(3) +#define AT91_MATRIX_RCB4 BIT(4) +#define AT91_MATRIX_RCB5 BIT(5) +#define AT91_MATRIX_RCB6 BIT(6) +#define AT91_MATRIX_RCB7 BIT(7) +#define AT91_MATRIX_RCB8 BIT(8) +#define AT91_MATRIX_RCB9 BIT(9) +#define AT91_MATRIX_RCB10 BIT(10) #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC BIT(1) #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA BIT(3) #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 BIT(4) #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 BIT(5) #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF BIT(8) #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V BIT(16) #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL BIT(17) #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL BIT(18) #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h index 295f768..e326ed9 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h @@ -28,17 +28,17 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY BIT(24) #define AT91_MATRIX_M0PR_SHIFT 0 #define AT91_MATRIX_M1PR_SHIFT 4 @@ -47,15 +47,15 @@ struct at91_matrix { #define AT91_MATRIX_M4PR_SHIFT 16 #define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_CS1A_SDRAMC BIT(1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA BIT(3) +#define AT91_MATRIX_CS4A_SMC_CF1 BIT(4) +#define AT91_MATRIX_CS5A_SMC_CF2 BIT(5) +#define AT91_MATRIX_DBPUC BIT(8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V BIT(16) #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h index bd0b25a..ff37da1 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h @@ -40,7 +40,7 @@ struct at91_matrix { #endif /* __ASSEMBLY__ */ #define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_SINGLE BIT(0) #define AT91_MATRIX_ULBT_FOUR (2 << 0) #define AT91_MATRIX_ULBT_EIGHT (3 << 0) #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) @@ -49,7 +49,7 @@ struct at91_matrix { #define AT91_MATRIX_ULBT_128 (7 << 0) #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST BIT(16) #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 @@ -67,33 +67,33 @@ struct at91_matrix { #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) +#define AT91_MATRIX_RCB0 BIT(0) +#define AT91_MATRIX_RCB1 BIT(1) +#define AT91_MATRIX_RCB2 BIT(2) +#define AT91_MATRIX_RCB3 BIT(3) +#define AT91_MATRIX_RCB4 BIT(4) +#define AT91_MATRIX_RCB5 BIT(5) +#define AT91_MATRIX_RCB6 BIT(6) +#define AT91_MATRIX_RCB7 BIT(7) +#define AT91_MATRIX_RCB8 BIT(8) +#define AT91_MATRIX_RCB9 BIT(9) +#define AT91_MATRIX_RCB10 BIT(10) #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC BIT(1) #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA BIT(3) #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF BIT(8) #define AT91_MATRIX_EBI_DBPD_ON (0 << 9) -#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) +#define AT91_MATRIX_EBI_DBPD_OFF BIT(9) #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V BIT(16) #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL BIT(17) #define AT91_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) +#define AT91_MATRIX_NFD0_ON_D16 BIT(24) #define AT91_MATRIX_MP_OFF (0 << 25) -#define AT91_MATRIX_MP_ON (1 << 25) +#define AT91_MATRIX_MP_ON BIT(25) #endif diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 54d369c..5677b83 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -201,9 +201,9 @@ struct bcm2835_mbox_tag_get_arm_mem { #define BCM2835_MBOX_POWER_DEVID_SPI 7 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 -#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) +#define BCM2835_MBOX_POWER_STATE_RESP_ON BIT(0) /* Device doesn't exist */ -#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) +#define BCM2835_MBOX_POWER_STATE_RESP_NODEV BIT(1) #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 @@ -222,8 +222,8 @@ struct bcm2835_mbox_tag_get_power_state { #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 -#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) -#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON BIT(0) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT BIT(1) struct bcm2835_mbox_tag_set_power_state { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h index fc7aec7..5ddb2cd 100644 --- a/arch/arm/mach-bcm283x/include/mach/timer.h +++ b/arch/arm/mach-bcm283x/include/mach/timer.h @@ -23,10 +23,10 @@ struct bcm2835_timer_regs { u32 c3; }; -#define BCM2835_TIMER_CS_M3 (1 << 3) -#define BCM2835_TIMER_CS_M2 (1 << 2) -#define BCM2835_TIMER_CS_M1 (1 << 1) -#define BCM2835_TIMER_CS_M0 (1 << 0) +#define BCM2835_TIMER_CS_M3 BIT(3) +#define BCM2835_TIMER_CS_M2 BIT(2) +#define BCM2835_TIMER_CS_M1 BIT(1) +#define BCM2835_TIMER_CS_M0 BIT(0) extern ulong get_timer_us(ulong base); diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index f9550a1..4c60b81 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -25,6 +25,6 @@ void davinci_enable_i2c(void) lpsc_on(DAVINCI_LPSC_I2C); /* Enable I2C pin Mux */ - REG(PINMUX3) |= (1 << 20) | (1 << 19); + REG(PINMUX3) |= BIT(20) | BIT(19); } #endif diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index c58e271..1931823 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -12,9 +12,9 @@ #include -#define PINMUX0_EMACEN (1 << 31) -#define PINMUX0_AECS5 (1 << 11) -#define PINMUX0_AECS4 (1 << 10) +#define PINMUX0_EMACEN BIT(31) +#define PINMUX0_AECS5 BIT(11) +#define PINMUX0_AECS4 BIT(10) #define PINMUX1_I2C (1 << 7) #define PINMUX1_UART1 (1 << 1) diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c index 151020d..da00844 100644 --- a/arch/arm/mach-davinci/et1011c.c +++ b/arch/arm/mach-davinci/et1011c.c @@ -21,7 +21,7 @@ #define MII_PHY_CONFIG_REG 22 /* PHY Config bits */ -#define PHY_SYS_CLK_EN (1 << 4) +#define PHY_SYS_CLK_EN BIT(4) int et1011c_get_link_speed(int phy_addr) { diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h index 5063e39..4a4ae3e 100644 --- a/arch/arm/mach-davinci/include/mach/aintc_defs.h +++ b/arch/arm/mach-davinci/include/mach/aintc_defs.h @@ -31,6 +31,6 @@ struct dv_aintc_regs { #define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) -#define DV_AINTC_INTCTL_IDMODE (1 << 2) +#define DV_AINTC_INTCTL_IDMODE BIT(2) #endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/mach-davinci/include/mach/da850_lowlevel.h b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h index 45a325c..c92ffe9 100644 --- a/arch/arm/mach-davinci/include/mach/da850_lowlevel.h +++ b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h @@ -20,8 +20,8 @@ extern const int lpsc_size; /* NOR Boot Configuration Word Field Descriptions */ #define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8) -#define DA850_NORBOOT_METHOD_DIRECT (1 << 4) -#define DA850_NORBOOT_16BIT (1 << 0) +#define DA850_NORBOOT_METHOD_DIRECT BIT(4) +#define DA850_NORBOOT_16BIT BIT(0) #define dv_maskbits(addr, val) \ writel((readl(addr) & val), addr) diff --git a/arch/arm/mach-davinci/include/mach/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h index f091e49..a0c9d99 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx-usb.h +++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h @@ -63,29 +63,29 @@ struct da8xx_usb_regs { (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ -#define CFGCHIP2_PHYCLKGD (1 << 17) -#define CFGCHIP2_VBUSSENSE (1 << 16) -#define CFGCHIP2_RESET (1 << 15) +#define CFGCHIP2_PHYCLKGD BIT(17) +#define CFGCHIP2_VBUSSENSE BIT(16) +#define CFGCHIP2_RESET BIT(15) #define CFGCHIP2_OTGMODE (3 << 13) #define CFGCHIP2_NO_OVERRIDE (0 << 13) -#define CFGCHIP2_FORCE_HOST (1 << 13) +#define CFGCHIP2_FORCE_HOST BIT(13) #define CFGCHIP2_FORCE_DEVICE (2 << 13) #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) -#define CFGCHIP2_USB1PHYCLKMUX (1 << 12) -#define CFGCHIP2_USB2PHYCLKMUX (1 << 11) -#define CFGCHIP2_PHYPWRDN (1 << 10) -#define CFGCHIP2_OTGPWRDN (1 << 9) -#define CFGCHIP2_DATPOL (1 << 8) -#define CFGCHIP2_USB1SUSPENDM (1 << 7) -#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ -#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ -#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ +#define CFGCHIP2_USB1PHYCLKMUX BIT(12) +#define CFGCHIP2_USB2PHYCLKMUX BIT(11) +#define CFGCHIP2_PHYPWRDN BIT(10) +#define CFGCHIP2_OTGPWRDN BIT(9) +#define CFGCHIP2_DATPOL BIT(8) +#define CFGCHIP2_USB1SUSPENDM BIT(7) +#define CFGCHIP2_PHY_PLLON BIT(6) /* override PLL suspend */ +#define CFGCHIP2_SESENDEN BIT(5) /* Vsess_end comparator */ +#define CFGCHIP2_VBDTCTEN BIT(4) /* Vbus comparator */ #define CFGCHIP2_REFFREQ (0xf << 0) -#define CFGCHIP2_REFFREQ_12MHZ (1 << 0) +#define CFGCHIP2_REFFREQ_12MHZ BIT(0) #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) -#define DA8XX_USB_VBUS_GPIO (1 << 15) +#define DA8XX_USB_VBUS_GPIO BIT(15) int usb_phy_on(void); void usb_phy_off(void); diff --git a/arch/arm/mach-davinci/include/mach/ddr2_defs.h b/arch/arm/mach-davinci/include/mach/ddr2_defs.h index 24afd9d..7ee1463 100644 --- a/arch/arm/mach-davinci/include/mach/ddr2_defs.h +++ b/arch/arm/mach-davinci/include/mach/ddr2_defs.h @@ -69,8 +69,8 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDCR_IBANK_SHIFT 4 #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 -#define DV_DDR_SDRCR_LPMODEN (1 << 31) -#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) +#define DV_DDR_SDRCR_LPMODEN BIT(31) +#define DV_DDR_SDRCR_MCLKSTOPEN BIT(30) #define DV_DDR_SRCR_LPMODEN_SHIFT 31 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index a4eb0bd..81add3c 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -382,9 +382,9 @@ struct davinci_uart_ctrl_regs { #define DAVINCI_UART_CTRL_BASE 0x28 /* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) +#define DAVINCI_UART_PWREMU_MGMT_FREE BIT(0) +#define DAVINCI_UART_PWREMU_MGMT_URRST BIT(13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST BIT(14) #else /* CONFIG_SOC_DA8XX */ @@ -433,7 +433,7 @@ struct davinci_pllc_regs { /* flags to select PLL controller */ #define DAVINCI_PLLC0_FLAG (0) -#define DAVINCI_PLLC1_FLAG (1 << 16) +#define DAVINCI_PLLC1_FLAG BIT(16) enum davinci_clk_ids { /* @@ -498,13 +498,13 @@ struct davinci_syscfg_regs { #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) /* Emulation suspend bits */ -#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) -#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) -#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) -#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) -#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) -#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) -#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) +#define DAVINCI_SYSCFG_SUSPSRC_EMAC BIT(5) +#define DAVINCI_SYSCFG_SUSPSRC_I2C BIT(16) +#define DAVINCI_SYSCFG_SUSPSRC_SPI0 BIT(21) +#define DAVINCI_SYSCFG_SUSPSRC_SPI1 BIT(22) +#define DAVINCI_SYSCFG_SUSPSRC_UART0 BIT(18) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 BIT(20) +#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 BIT(27) struct davinci_syscfg1_regs { dv_reg vtpio_ctl; @@ -522,11 +522,11 @@ struct davinci_syscfg1_regs { #define DDR_SLEW_CMOSEN_BIT 4 #define DDR_SLEW_DDR_PDENA_BIT 5 -#define VTP_POWERDWN (1 << 6) -#define VTP_LOCK (1 << 7) -#define VTP_CLKRZ (1 << 13) -#define VTP_READY (1 << 15) -#define VTP_IOPWRDWN (1 << 14) +#define VTP_POWERDWN BIT(6) +#define VTP_LOCK BIT(7) +#define VTP_CLKRZ BIT(13) +#define VTP_READY BIT(15) +#define VTP_IOPWRDWN BIT(14) #define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13 #define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0 @@ -567,9 +567,9 @@ struct davinci_uart_ctrl_regs { ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) /* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) +#define DAVINCI_UART_PWREMU_MGMT_FREE BIT(0) +#define DAVINCI_UART_PWREMU_MGMT_URRST BIT(13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST BIT(14) static inline int cpu_is_da830(void) { diff --git a/arch/arm/mach-davinci/include/mach/pll_defs.h b/arch/arm/mach-davinci/include/mach/pll_defs.h index d083ccc..6708a60 100644 --- a/arch/arm/mach-davinci/include/mach/pll_defs.h +++ b/arch/arm/mach-davinci/include/mach/pll_defs.h @@ -41,33 +41,33 @@ struct dv_pll_regs { unsigned int plldiv9; /* 0x174 */ }; -#define PLL_MASTER_LOCK (1 << 4) +#define PLL_MASTER_LOCK BIT(4) #define PLLCTL_CLOCK_MODE_SHIFT 8 -#define PLLCTL_PLLEN (1 << 0) -#define PLLCTL_PLLPWRDN (1 << 1) -#define PLLCTL_PLLRST (1 << 3) -#define PLLCTL_PLLDIS (1 << 4) -#define PLLCTL_PLLENSRC (1 << 5) -#define PLLCTL_RES_9 (1 << 8) -#define PLLCTL_EXTCLKSRC (1 << 9) +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_RES_9 BIT(8) +#define PLLCTL_EXTCLKSRC BIT(9) -#define PLL_DIVEN (1 << 15) +#define PLL_DIVEN BIT(15) #define PLL_POSTDEN PLL_DIVEN -#define PLL_SCSCFG3_DIV45PENA (1 << 2) -#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1) +#define PLL_SCSCFG3_DIV45PENA BIT(2) +#define PLL_SCSCFG3_EMA_CLKSRC BIT(1) -#define PLL_RSTYPE_POR (1 << 0) -#define PLL_RSTYPE_XWRST (1 << 1) +#define PLL_RSTYPE_POR BIT(0) +#define PLL_RSTYPE_XWRST BIT(1) -#define PLLSECCTL_TINITZ (1 << 16) -#define PLLSECCTL_TENABLE (1 << 17) -#define PLLSECCTL_TENABLEDIV (1 << 18) -#define PLLSECCTL_STOPMODE (1 << 22) +#define PLLSECCTL_TINITZ BIT(16) +#define PLLSECCTL_TENABLE BIT(17) +#define PLLSECCTL_TENABLEDIV BIT(18) +#define PLLSECCTL_STOPMODE BIT(22) -#define PLLCMD_GOSET (1 << 0) -#define PLLCMD_GOSTAT (1 << 0) +#define PLLCMD_GOSET BIT(0) +#define PLLCMD_GOSTAT BIT(0) #define PLL0_LOCK 0x07000000 #define PLL1_LOCK 0x07000000 diff --git a/arch/arm/mach-davinci/include/mach/psc_defs.h b/arch/arm/mach-davinci/include/mach/psc_defs.h index bcb5580..3b3d309 100644 --- a/arch/arm/mach-davinci/include/mach/psc_defs.h +++ b/arch/arm/mach-davinci/include/mach/psc_defs.h @@ -60,10 +60,10 @@ struct dv_psc_regs { #define PSC_SYNCRESET (0x1) #define PSC_SWRSTDISABLE (0x0) -#define PSC_GOSTAT (1 << 0) +#define PSC_GOSTAT BIT(0) #define PSC_MD_STATE_MSK (0x1f) -#define PSC_CMD_GO (1 << 0) +#define PSC_CMD_GO BIT(0) #define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) diff --git a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h index 9aa3f4a..86dea7a 100644 --- a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h +++ b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h @@ -12,60 +12,60 @@ #include /* MMC Control Reg fields */ -#define MMCCTL_DATRST (1 << 0) -#define MMCCTL_CMDRST (1 << 1) -#define MMCCTL_WIDTH_4_BIT (1 << 2) +#define MMCCTL_DATRST BIT(0) +#define MMCCTL_CMDRST BIT(1) +#define MMCCTL_WIDTH_4_BIT BIT(2) #define MMCCTL_DATEG_DISABLED (0 << 6) -#define MMCCTL_DATEG_RISING (1 << 6) +#define MMCCTL_DATEG_RISING BIT(6) #define MMCCTL_DATEG_FALLING (2 << 6) #define MMCCTL_DATEG_BOTH (3 << 6) #define MMCCTL_PERMDR_LE (0 << 9) -#define MMCCTL_PERMDR_BE (1 << 9) +#define MMCCTL_PERMDR_BE BIT(9) #define MMCCTL_PERMDX_LE (0 << 10) -#define MMCCTL_PERMDX_BE (1 << 10) +#define MMCCTL_PERMDX_BE BIT(10) /* MMC Clock Control Reg fields */ -#define MMCCLK_CLKEN (1 << 8) +#define MMCCLK_CLKEN BIT(8) #define MMCCLK_CLKRT_MASK (0xFF << 0) /* MMC Status Reg0 fields */ -#define MMCST0_DATDNE (1 << 0) -#define MMCST0_BSYDNE (1 << 1) -#define MMCST0_RSPDNE (1 << 2) -#define MMCST0_TOUTRD (1 << 3) -#define MMCST0_TOUTRS (1 << 4) -#define MMCST0_CRCWR (1 << 5) -#define MMCST0_CRCRD (1 << 6) -#define MMCST0_CRCRS (1 << 7) -#define MMCST0_DXRDY (1 << 9) -#define MMCST0_DRRDY (1 << 10) -#define MMCST0_DATED (1 << 11) -#define MMCST0_TRNDNE (1 << 12) +#define MMCST0_DATDNE BIT(0) +#define MMCST0_BSYDNE BIT(1) +#define MMCST0_RSPDNE BIT(2) +#define MMCST0_TOUTRD BIT(3) +#define MMCST0_TOUTRS BIT(4) +#define MMCST0_CRCWR BIT(5) +#define MMCST0_CRCRD BIT(6) +#define MMCST0_CRCRS BIT(7) +#define MMCST0_DXRDY BIT(9) +#define MMCST0_DRRDY BIT(10) +#define MMCST0_DATED BIT(11) +#define MMCST0_TRNDNE BIT(12) #define MMCST0_ERR_MASK (0x00F8) /* MMC Status Reg1 fields */ -#define MMCST1_BUSY (1 << 0) -#define MMCST1_CLKSTP (1 << 1) -#define MMCST1_DXEMP (1 << 2) -#define MMCST1_DRFUL (1 << 3) -#define MMCST1_DAT3ST (1 << 4) -#define MMCST1_FIFOEMP (1 << 5) -#define MMCST1_FIFOFUL (1 << 6) +#define MMCST1_BUSY BIT(0) +#define MMCST1_CLKSTP BIT(1) +#define MMCST1_DXEMP BIT(2) +#define MMCST1_DRFUL BIT(3) +#define MMCST1_DAT3ST BIT(4) +#define MMCST1_FIFOEMP BIT(5) +#define MMCST1_FIFOFUL BIT(6) /* MMC INT Mask Reg fields */ -#define MMCIM_EDATDNE (1 << 0) -#define MMCIM_EBSYDNE (1 << 1) -#define MMCIM_ERSPDNE (1 << 2) -#define MMCIM_ETOUTRD (1 << 3) -#define MMCIM_ETOUTRS (1 << 4) -#define MMCIM_ECRCWR (1 << 5) -#define MMCIM_ECRCRD (1 << 6) -#define MMCIM_ECRCRS (1 << 7) -#define MMCIM_EDXRDY (1 << 9) -#define MMCIM_EDRRDY (1 << 10) -#define MMCIM_EDATED (1 << 11) -#define MMCIM_ETRNDNE (1 << 12) +#define MMCIM_EDATDNE BIT(0) +#define MMCIM_EBSYDNE BIT(1) +#define MMCIM_ERSPDNE BIT(2) +#define MMCIM_ETOUTRD BIT(3) +#define MMCIM_ETOUTRS BIT(4) +#define MMCIM_ECRCWR BIT(5) +#define MMCIM_ECRCRD BIT(6) +#define MMCIM_ECRCRS BIT(7) +#define MMCIM_EDXRDY BIT(9) +#define MMCIM_EDRRDY BIT(10) +#define MMCIM_EDATED BIT(11) +#define MMCIM_ETRNDNE BIT(12) #define MMCIM_MASKALL (0xFFFFFFFF) @@ -88,25 +88,25 @@ /* MMC Cmd Reg fields */ #define MMCCMD_CMD_MASK (0x3F) -#define MMCCMD_PPLEN (1 << 7) -#define MMCCMD_BSYEXP (1 << 8) +#define MMCCMD_PPLEN BIT(7) +#define MMCCMD_BSYEXP BIT(8) #define MMCCMD_RSPFMT_NONE (0 << 9) -#define MMCCMD_RSPFMT_R1567 (1 << 9) +#define MMCCMD_RSPFMT_R1567 BIT(9) #define MMCCMD_RSPFMT_R2 (2 << 9) #define MMCCMD_RSPFMT_R3 (3 << 9) -#define MMCCMD_DTRW (1 << 11) -#define MMCCMD_STRMTP (1 << 12) -#define MMCCMD_WDATX (1 << 13) -#define MMCCMD_INITCK (1 << 14) -#define MMCCMD_DCLR (1 << 15) -#define MMCCMD_DMATRIG (1 << 16) +#define MMCCMD_DTRW BIT(11) +#define MMCCMD_STRMTP BIT(12) +#define MMCCMD_WDATX BIT(13) +#define MMCCMD_INITCK BIT(14) +#define MMCCMD_DCLR BIT(15) +#define MMCCMD_DMATRIG BIT(16) /* FIFO control Reg fields */ -#define MMCFIFOCTL_FIFORST (1 << 0) -#define MMCFIFOCTL_FIFODIR (1 << 1) -#define MMCFIFOCTL_FIFOLEV (1 << 2) +#define MMCFIFOCTL_FIFORST BIT(0) +#define MMCFIFOCTL_FIFODIR BIT(1) +#define MMCFIFOCTL_FIFOLEV BIT(2) #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ -#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ +#define MMCFIFOCTL_ACCWD_3 BIT(3) /* access width of 3 bytes */ #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ diff --git a/arch/arm/mach-davinci/include/mach/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h index 812088f..bd51f1c 100644 --- a/arch/arm/mach-davinci/include/mach/syscfg_defs.h +++ b/arch/arm/mach-davinci/include/mach/syscfg_defs.h @@ -35,13 +35,13 @@ struct dv_sys_module_regs { unsigned int pll1_config; /* 0x88 */ }; -#define VPTIO_RDY (1 << 15) -#define VPTIO_IOPWRDN (1 << 14) -#define VPTIO_CLRZ (1 << 13) -#define VPTIO_LOCK (1 << 7) -#define VPTIO_PWRDN (1 << 6) +#define VPTIO_RDY BIT(15) +#define VPTIO_IOPWRDN BIT(14) +#define VPTIO_CLRZ BIT(13) +#define VPTIO_LOCK BIT(7) +#define VPTIO_PWRDN BIT(6) -#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) +#define VPSS_CLK_CTL_VPSS_CLKMD BIT(7) #define dv_sys_module_regs \ ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index e699d61..925ea71 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -73,9 +73,9 @@ void davinci_emac_mii_mode_sel(int mode_sel) val = readl(&davinci_syscfg_regs->cfgchip3); if (mode_sel == 0) - val &= ~(1 << 8); + val &= ~BIT(8); else - val |= (1 << 8); + val |= BIT(8); writel(val, &davinci_syscfg_regs->cfgchip3); } #endif diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 4c9d3fd..3606fa0 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -19,7 +19,7 @@ void reset_cpu(unsigned long ignored) struct kwcpu_registers *cpureg = (struct kwcpu_registers *)KW_CPU_REG_BASE; - writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + writel(readl(&cpureg->rstoutn_mask) | BIT(2), &cpureg->rstoutn_mask); writel(readl(&cpureg->sys_soft_rst) | 1, &cpureg->sys_soft_rst); @@ -238,7 +238,7 @@ int arch_cpu_init(void) * By default it is set to 3.3V */ reg = readl(KW_REG_MPP_OUT_DRV_REG); - reg |= (1 << 7); + reg |= BIT(7); writel(reg, KW_REG_MPP_OUT_DRV_REG); #endif #ifdef CONFIG_KIRKWOOD_EGIGA_INIT @@ -249,10 +249,10 @@ int arch_cpu_init(void) * and if u-boot is build without network support, network may fail at OS level */ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0)); - reg &= ~(1 << 4); /* Clear PortReset Bit */ + reg &= ~BIT(4); /* Clear PortReset Bit */ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0))); reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1)); - reg &= ~(1 << 4); /* Clear PortReset Bit */ + reg &= ~BIT(4); /* Clear PortReset Bit */ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1))); #endif #ifdef CONFIG_KIRKWOOD_PCIE_INIT @@ -260,7 +260,7 @@ int arch_cpu_init(void) * Enable PCI Express Port0 */ reg = readl(&cpureg->ctrl_stat); - reg |= (1 << 0); /* Set PEX0En Bit */ + reg |= BIT(0); /* Set PEX0En Bit */ writel(reg, &cpureg->ctrl_stat); #endif return 0; @@ -277,19 +277,19 @@ int arch_misc_init(void) /*CPU streaming & write allocate */ temp = readfr_extra_feature_reg(); - temp &= ~(1 << 28); /* disable wr alloc */ + temp &= ~BIT(28); /* disable wr alloc */ writefr_extra_feature_reg(temp); temp = readfr_extra_feature_reg(); - temp &= ~(1 << 29); /* streaming disabled */ + temp &= ~BIT(29); /* streaming disabled */ writefr_extra_feature_reg(temp); /* L2Cache settings */ temp = readfr_extra_feature_reg(); /* Disable L2C pre fetch - Set bit 24 */ - temp |= (1 << 24); + temp |= BIT(24); /* enable L2C - Set bit 22 */ - temp |= (1 << 22); + temp |= BIT(22); writefr_extra_feature_reg(temp); icache_enable(); diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h index aa8c5da..abaf784 100644 --- a/arch/arm/mach-kirkwood/include/mach/gpio.h +++ b/arch/arm/mach-kirkwood/include/mach/gpio.h @@ -43,7 +43,7 @@ void kw_gpio_set_value(unsigned pin, int value); void kw_gpio_set_blink(unsigned pin, int blink); void kw_gpio_set_unused(unsigned pin); -#define GPIO_INPUT_OK (1 << 0) -#define GPIO_OUTPUT_OK (1 << 1) +#define GPIO_INPUT_OK BIT(0) +#define GPIO_OUTPUT_OK BIT(1) #endif diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index 2ecd385..397884b 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -23,7 +23,7 @@ void reset_cpu(unsigned long ignored) struct orion5x_cpu_registers *cpureg = (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; - writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + writel(readl(&cpureg->rstoutn_mask) | BIT(2), &cpureg->rstoutn_mask); writel(readl(&cpureg->sys_soft_rst) | 1, &cpureg->sys_soft_rst); @@ -252,19 +252,19 @@ int arch_misc_init(void) /*CPU streaming & write allocate */ temp = readfr_extra_feature_reg(); - temp &= ~(1 << 28); /* disable wr alloc */ + temp &= ~BIT(28); /* disable wr alloc */ writefr_extra_feature_reg(temp); temp = readfr_extra_feature_reg(); - temp &= ~(1 << 29); /* streaming disabled */ + temp &= ~BIT(29); /* streaming disabled */ writefr_extra_feature_reg(temp); /* L2Cache settings */ temp = readfr_extra_feature_reg(); /* Disable L2C pre fetch - Set bit 24 */ - temp |= (1 << 24); + temp |= BIT(24); /* enable L2C - Set bit 22 */ - temp |= (1 << 22); + temp |= BIT(22); writefr_extra_feature_reg(temp); icache_enable(); diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index ec4f6be..98af1ac 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -48,7 +48,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT(1) #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index b4ca44f..aa74ab0 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -21,7 +21,7 @@ #error "Unknown Tegra chip!" #endif -#define PLLX_ENABLED (1 << 30) +#define PLLX_ENABLED BIT(30) #define CCLK_BURST_POLICY 0x20008888 #define SUPER_CCLK_DIVIDER 0x80000000 @@ -45,9 +45,9 @@ #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) #define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) +#define HALT_COP_EVENT_JTAG BIT(28) +#define HALT_COP_EVENT_IRQ_1 BIT(11) +#define HALT_COP_EVENT_FIQ_1 BIT(9) #define FLOW_MODE_NONE 0 diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index b4a1432..8f3eb47 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -732,7 +732,7 @@ static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, assert(mux != -1); val = readl(reg); - val &= ~(1 << 1); + val &= ~BIT(1); val |= (mux << 1); writel(val, reg); } diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 439cff3..15c5db6 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -14,7 +14,7 @@ #include #define PWRGATE_TOGGLE 0x30 -#define PWRGATE_TOGGLE_START (1 << 8) +#define PWRGATE_TOGGLE_START BIT(8) #define REMOVE_CLAMPING 0x34 diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index fc8bd19..bef4f64 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -828,31 +828,31 @@ void arch_timer_init(void) #define PLLE_SS_CNTL 0x68 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) -#define PLLE_SS_CNTL_SSCINVERT (1 << 15) -#define PLLE_SS_CNTL_SSCCENTER (1 << 14) -#define PLLE_SS_CNTL_SSCBYP (1 << 12) -#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) -#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCINVERT BIT(15) +#define PLLE_SS_CNTL_SSCCENTER BIT(14) +#define PLLE_SS_CNTL_SSCBYP BIT(12) +#define PLLE_SS_CNTL_INTERP_RESET BIT(11) +#define PLLE_SS_CNTL_BYPASS_SS BIT(10) #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) #define PLLE_BASE 0x0e8 -#define PLLE_BASE_ENABLE (1 << 30) -#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) +#define PLLE_BASE_ENABLE BIT(30) +#define PLLE_BASE_LOCK_OVERRIDE BIT(29) #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) #define PLLE_MISC 0x0ec -#define PLLE_MISC_IDDQ_SWCTL (1 << 14) -#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) -#define PLLE_MISC_LOCK_ENABLE (1 << 9) -#define PLLE_MISC_PTS (1 << 8) +#define PLLE_MISC_IDDQ_SWCTL BIT(14) +#define PLLE_MISC_IDDQ_OVERRIDE BIT(13) +#define PLLE_MISC_LOCK_ENABLE BIT(9) +#define PLLE_MISC_PTS BIT(8) #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) #define PLLE_AUX 0x48c -#define PLLE_AUX_SEQ_ENABLE (1 << 24) -#define PLLE_AUX_ENABLE_SWCTL (1 << 4) +#define PLLE_AUX_SEQ_ENABLE BIT(24) +#define PLLE_AUX_ENABLE_SWCTL BIT(4) int tegra_plle_enable(void) { diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 43af883..a7fc075 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -19,30 +19,30 @@ #include #define XUSB_PADCTL_ELPG_PROGRAM 0x01c -#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) -#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) -#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN BIT(26) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY BIT(25) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN BIT(24) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 -#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET BIT(19) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) -#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST BIT(1) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 -#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) -#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) -#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN BIT(6) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN BIT(5) +#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL BIT(4) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 -#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) -#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) -#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) -#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) -#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET BIT(27) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE BIT(24) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD BIT(3) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST BIT(1) +#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ BIT(0) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 -#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) -#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD BIT(1) +#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ BIT(0) enum tegra124_function { TEGRA124_FUNC_SNPS, diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 7b9e10c..d433017 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -551,20 +551,20 @@ void arch_timer_init(void) } #define PMC_SATA_PWRGT 0x1ac -#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) -#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) +#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE BIT(5) +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) #define PLLE_SS_CNTL 0x68 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) -#define PLLE_SS_CNTL_SSCBYP (1 << 12) -#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) -#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCBYP BIT(12) +#define PLLE_SS_CNTL_INTERP_RESET BIT(11) +#define PLLE_SS_CNTL_BYPASS_SS BIT(10) #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) #define PLLE_BASE 0x0e8 -#define PLLE_BASE_ENABLE_CML (1 << 31) -#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_ENABLE_CML BIT(31) +#define PLLE_BASE_ENABLE BIT(30) #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) @@ -572,9 +572,9 @@ void arch_timer_init(void) #define PLLE_MISC 0x0ec #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) -#define PLLE_MISC_PLL_READY (1 << 15) -#define PLLE_MISC_LOCK (1 << 11) -#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_PLL_READY BIT(15) +#define PLLE_MISC_LOCK BIT(11) +#define PLLE_MISC_LOCK_ENABLE BIT(9) #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) static int tegra_plle_train(void) diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 7b86acb..4b8750a 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h @@ -20,44 +20,44 @@ #define USEC_CFG_DIVISOR_MASK 0xffff -#define CONFIG_CTL_TBE (1 << 7) -#define CONFIG_CTL_JTAG (1 << 6) +#define CONFIG_CTL_TBE BIT(7) +#define CONFIG_CTL_JTAG BIT(6) -#define CPU_RST (1 << 0) -#define CLK_ENB_CPU (1 << 0) -#define SWR_TRIG_SYS_RST (1 << 2) -#define SWR_CSITE_RST (1 << 9) +#define CPU_RST BIT(0) +#define CLK_ENB_CPU BIT(0) +#define SWR_TRIG_SYS_RST BIT(2) +#define SWR_CSITE_RST BIT(9) -#define PWRGATE_STATUS_CPU (1 << 0) +#define PWRGATE_STATUS_CPU BIT(0) #define PWRGATE_TOGGLE_PARTID_CPU (0 << 0) -#define PWRGATE_TOGGLE_START (1 << 8) +#define PWRGATE_TOGGLE_START BIT(8) #define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0) -#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) +#define CPU_CMPLX_CPU0_CLK_STP_STOP BIT(8) #define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) -#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) +#define CPU_CMPLX_CPU1_CLK_STP_STOP BIT(9) #define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) -#define CPU_CMPLX_CPURESET0 (1 << 0) -#define CPU_CMPLX_CPURESET1 (1 << 1) -#define CPU_CMPLX_DERESET0 (1 << 4) -#define CPU_CMPLX_DERESET1 (1 << 5) -#define CPU_CMPLX_DBGRESET0 (1 << 12) -#define CPU_CMPLX_DBGRESET1 (1 << 13) +#define CPU_CMPLX_CPURESET0 BIT(0) +#define CPU_CMPLX_CPURESET1 BIT(1) +#define CPU_CMPLX_DERESET0 BIT(4) +#define CPU_CMPLX_DERESET1 BIT(5) +#define CPU_CMPLX_DBGRESET0 BIT(12) +#define CPU_CMPLX_DBGRESET1 BIT(13) -#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) -#define PLLM_OUT1_CLKEN_ENABLE (1 << 1) +#define PLLM_OUT1_RSTN_RESET_DISABLE BIT(0) +#define PLLM_OUT1_CLKEN_ENABLE BIT(1) #define PLLM_OUT1_RATIO_VAL_8 (8 << 8) -#define SCLK_SYS_STATE_IDLE (1 << 28) +#define SCLK_SYS_STATE_IDLE BIT(28) #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) #define EVENT_ZERO_VAL_20 (20 << 0) -#define EVENT_MSEC (1 << 24) -#define EVENT_JTAG (1 << 28) +#define EVENT_MSEC BIT(24) +#define EVENT_JTAG BIT(28) #define EVENT_MODE_STOP (2 << 29) #define CCLK_PLLP_BURST_POLICY 0x20004444 diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 0eb0f0a..f4effdb 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -591,20 +591,20 @@ void arch_timer_init(void) } #define PMC_SATA_PWRGT 0x1ac -#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5) -#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4) +#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE BIT(5) +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) #define PLLE_SS_CNTL 0x68 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24) #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) -#define PLLE_SS_CNTL_SSCBYP (1 << 12) -#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) -#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCBYP BIT(12) +#define PLLE_SS_CNTL_INTERP_RESET BIT(11) +#define PLLE_SS_CNTL_BYPASS_SS BIT(10) #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) #define PLLE_BASE 0x0e8 -#define PLLE_BASE_ENABLE_CML (1 << 31) -#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_ENABLE_CML BIT(31) +#define PLLE_BASE_ENABLE BIT(30) #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16) #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) @@ -612,9 +612,9 @@ void arch_timer_init(void) #define PLLE_MISC 0x0ec #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) -#define PLLE_MISC_PLL_READY (1 << 15) -#define PLLE_MISC_LOCK (1 << 11) -#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_PLL_READY BIT(15) +#define PLLE_MISC_LOCK BIT(11) +#define PLLE_MISC_LOCK_ENABLE BIT(9) #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2) static int tegra_plle_train(void) diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 6b7d600..12ad3e0 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -84,16 +84,16 @@ struct ddrphy { #define PIR_DRAMRST (1 << 7) /* DRAM Reset */ #define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ #define PIR_WL (1 << 9) /* Write Leveling */ -#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ -#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ -#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ -#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ -#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ -#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ -#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ -#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ -#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ -#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ +#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */ +#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */ +#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ +#define PIR_RDEYE BIT(14) /* Read Data Eye Training */ +#define PIR_WREYE BIT(15) /* Write Data Eye Training */ +#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */ +#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ +#define PIR_INITBYP BIT(31) /* Initialization Bypass */ #define PGSR0_IDONE (1 << 0) /* Initialization Done */ #define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ @@ -105,26 +105,26 @@ struct ddrphy { #define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ #define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ #define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ -#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ -#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ -#define PGSR0_IERR (1 << 16) /* Initialization Error */ -#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ -#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ -#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ -#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ -#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ -#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ -#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ -#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ -#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ -#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ -#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */ +#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ +#define PGSR0_IERR BIT(16) /* Initialization Error */ +#define PGSR0_PLERR BIT(17) /* PLL Lock Error */ +#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */ +#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */ +#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */ +#define PGSR0_WLERR BIT(21) /* Write Leveling Error */ +#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ +#define PGSR0_REERR BIT(26) /* Read Eye Training Error */ +#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */ #define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ #define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) -#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ +#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */ #define DXCCR_DQSRES_OPEN (0 << 5) -#define DXCCR_DQSRES_688_OHM (1 << 5) +#define DXCCR_DQSRES_688_OHM BIT(5) #define DXCCR_DQSRES_611_OHM (2 << 5) #define DXCCR_DQSRES_550_OHM (3 << 5) #define DXCCR_DQSRES_500_OHM (4 << 5) @@ -133,7 +133,7 @@ struct ddrphy { #define DXCCR_DQSRES_344_OHM (7 << 5) #define DXCCR_DQSNRES_OPEN (0 << 9) -#define DXCCR_DQSNRES_688_OHM (1 << 9) +#define DXCCR_DQSNRES_688_OHM BIT(9) #define DXCCR_DQSNRES_611_OHM (2 << 9) #define DXCCR_DQSNRES_550_OHM (3 << 9) #define DXCCR_DQSNRES_500_OHM (4 << 9) @@ -143,7 +143,7 @@ struct ddrphy { #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) -#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ +#define DTCR_DTMPR BIT(6) /* Data Training using MPR */ #define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ #define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index 5d694d8..586ba76 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -21,16 +21,16 @@ #include -#define TIMER_ENABLE (1 << 7) -#define TIMER_MODE_MSK (1 << 6) +#define TIMER_ENABLE BIT(7) +#define TIMER_MODE_MSK BIT(6) #define TIMER_MODE_FR (0 << 6) -#define TIMER_MODE_PD (1 << 6) +#define TIMER_MODE_PD BIT(6) -#define TIMER_INT_EN (1 << 5) +#define TIMER_INT_EN BIT(5) #define TIMER_PRS_MSK (3 << 2) -#define TIMER_PRS_8S (1 << 3) -#define TIMER_SIZE_MSK (1 << 2) -#define TIMER_ONE_SHT (1 << 0) +#define TIMER_PRS_8S BIT(3) +#define TIMER_SIZE_MSK BIT(2) +#define TIMER_ONE_SHT BIT(0) int timer_init (void) { diff --git a/arch/arm/mvebu-common/dram.c b/arch/arm/mvebu-common/dram.c index db18791..62df290 100644 --- a/arch/arm/mvebu-common/dram.c +++ b/arch/arm/mvebu-common/dram.c @@ -23,8 +23,8 @@ struct sdram_addr_dec { struct sdram_bank sdram_bank[4]; }; -#define REG_CPUCS_WIN_ENABLE (1 << 0) -#define REG_CPUCS_WIN_WR_PROTECT (1 << 1) +#define REG_CPUCS_WIN_ENABLE BIT(0) +#define REG_CPUCS_WIN_WR_PROTECT BIT(1) #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) diff --git a/arch/arm/mvebu-common/serdes/board_env_spec.h b/arch/arm/mvebu-common/serdes/board_env_spec.h index 36e0ed8..113abe9 100644 --- a/arch/arm/mvebu-common/serdes/board_env_spec.h +++ b/arch/arm/mvebu-common/serdes/board_env_spec.h @@ -113,7 +113,7 @@ #define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0 #define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40) -#define MV_GPP66 (1 << 2) +#define MV_GPP66 BIT(2) /* Relevant for MV78XX0 */ #define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20) @@ -202,9 +202,9 @@ #define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) #define PXSR_DL_DOWN 0x1 /* DL_Down indication. */ -#define PXCAR_CONFIG_EN (1 << 31) +#define PXCAR_CONFIG_EN BIT(31) #define PEX_STATUS_AND_COMMAND 0x004 -#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */ +#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */ /* PCI Express Configuration Address Register */ diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_lib.c b/arch/arm/mvebu-common/serdes/high_speed_env_lib.c index 702273a..6a23b46 100644 --- a/arch/arm/mvebu-common/serdes/high_speed_env_lib.c +++ b/arch/arm/mvebu-common/serdes/high_speed_env_lib.c @@ -282,7 +282,7 @@ int serdes_phy_config(void) u8 fabric_freq; cpu_avs = reg_read(CPU_AVS_CONTROL2_REG); DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs); - cpu_avs &= ~(1 << 9); + cpu_avs &= ~BIT(9); if ((0x4 == freq) || (0xB == freq)) { u32 tmp2; @@ -293,8 +293,8 @@ int serdes_phy_config(void) tmp2 |= 0x0FF; reg_write(CPU_AVS_CONTROL0_REG, tmp2); DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2); - cpu_avs |= (1 << 9); /* cpu avs enable */ - cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */ + cpu_avs |= BIT(9); /* cpu avs enable */ + cpu_avs |= BIT(18); /* AvsAvddDetEn enable */ fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) & SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET; if ((0xB == freq) && (5 == fabric_freq)) { @@ -314,7 +314,7 @@ int serdes_phy_config(void) core_avs = reg_read(CORE_AVS_CONTROL_2REG); DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs); - core_avs |= (1 << 9); /* core AVS enable */ + core_avs |= BIT(9); /* core AVS enable */ reg_write(CORE_AVS_CONTROL_2REG, core_avs); DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs); @@ -480,9 +480,9 @@ int serdes_phy_config(void) /* QSGMII Active bit set to true */ tmp = reg_read(QSGMII_CONTROL_1_REG); DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp); - tmp |= (1 << 30); + tmp |= BIT(30); #ifdef ERRATA_GL_6572255 - tmp |= (1 << 27); + tmp |= BIT(27); #endif reg_write(QSGMII_CONTROL_1_REG, tmp); DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp); @@ -643,7 +643,7 @@ int serdes_phy_config(void) /* set Common Clock Configuration */ tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if)); DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); - tmp |= (1 << 6); + tmp |= BIT(6); reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp); @@ -738,28 +738,28 @@ int serdes_phy_config(void) */ /* Use Maximum PLL Rate(Bit 8) */ reg_write(PEX_PHY_ACCESS_REG(pex_unit), - (0x02 << 16) | (1 << 31) | + (0x02 << 16) | BIT(31) | (pex_line_num << 24)); /* read command */ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), - (0x02 << 16) | (1 << 31) | + (0x02 << 16) | BIT(31) | (pex_line_num << 24)); tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); - tmp &= ~(1 << 31); - tmp |= (1 << 8); + tmp &= ~BIT(31); + tmp |= BIT(8); reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); /* Use Maximum PLL Rate(Bits [10:9]) */ reg_write(PEX_PHY_ACCESS_REG(pex_unit), - (0x81 << 16) | (1 << 31) | + (0x81 << 16) | BIT(31) | (pex_line_num << 24)); /* read command */ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), - (0x81 << 16) | (1 << 31) | + (0x81 << 16) | BIT(31) | (pex_line_num << 24)); tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); - tmp &= ~(1 << 31); + tmp &= ~BIT(31); tmp |= (3 << 9); reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp); @@ -1292,7 +1292,7 @@ int serdes_phy_config(void) (PEX_LINK_CTRL_STATUS2_REG (pex_if), tmp); tmp &= ~(0x1 | 1 << 1); - tmp |= (1 << 1); + tmp |= BIT(1); reg_write (PEX_LINK_CTRL_STATUS2_REG (pex_if), tmp); @@ -1307,7 +1307,7 @@ int serdes_phy_config(void) DEBUG_RD_REG (PEX_CTRL_REG (pex_if), tmp); - tmp |= (1 << 10); + tmp |= BIT(10); reg_write(PEX_CTRL_REG (pex_if), tmp); diff --git a/arch/avr32/cpu/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c index 58327ba..36da1ac 100644 --- a/arch/avr32/cpu/at32ap700x/portmux.c +++ b/arch/avr32/cpu/at32ap700x/portmux.c @@ -32,7 +32,7 @@ void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, if (flags & PORTMUX_EBI_CS(5)) porte_mask |= 1 << 22; if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1))) - porte_mask |= (1 << 19) | (1 << 20) | (1 << 23); + porte_mask |= BIT(19) | BIT(20) | BIT(23); portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, PORTMUX_FUNC_A, 0); @@ -47,29 +47,29 @@ void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength) { unsigned long portc_mask; - portc_mask = (1 << 3) /* TXD0 */ - | (1 << 4) /* TXD1 */ - | (1 << 7) /* TXEN */ - | (1 << 8) /* TXCK */ - | (1 << 9) /* RXD0 */ - | (1 << 10) /* RXD1 */ - | (1 << 13) /* RXER */ - | (1 << 15) /* RXDV */ - | (1 << 16) /* MDC */ - | (1 << 17); /* MDIO */ + portc_mask = BIT(3) /* TXD0 */ + | BIT(4) /* TXD1 */ + | BIT(7) /* TXEN */ + | BIT(8) /* TXCK */ + | BIT(9) /* RXD0 */ + | BIT(10) /* RXD1 */ + | BIT(13) /* RXER */ + | BIT(15) /* RXDV */ + | BIT(16) /* MDC */ + | BIT(17); /* MDIO */ if (flags & PORTMUX_MACB_MII) - portc_mask |= (1 << 0) /* COL */ - | (1 << 1) /* CRS */ - | (1 << 2) /* TXER */ - | (1 << 5) /* TXD2 */ - | (1 << 6) /* TXD3 */ - | (1 << 11) /* RXD2 */ - | (1 << 12) /* RXD3 */ - | (1 << 14); /* RXCK */ + portc_mask |= BIT(0) /* COL */ + | BIT(1) /* CRS */ + | BIT(2) /* TXER */ + | BIT(5) /* TXD2 */ + | BIT(6) /* TXD3 */ + | BIT(11) /* RXD2 */ + | BIT(12) /* RXD3 */ + | BIT(14); /* RXCK */ if (flags & PORTMUX_MACB_SPEED) - portc_mask |= (1 << 18);/* SPD */ + portc_mask |= BIT(18);/* SPD */ /* REVISIT: Some pins are probably pure outputs */ portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, @@ -81,29 +81,29 @@ void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) unsigned long portc_mask = 0; unsigned long portd_mask; - portd_mask = (1 << 13) /* TXD0 */ - | (1 << 14) /* TXD1 */ - | (1 << 11) /* TXEN */ - | (1 << 12) /* TXCK */ - | (1 << 10) /* RXD0 */ - | (1 << 6) /* RXD1 */ - | (1 << 5) /* RXER */ - | (1 << 4) /* RXDV */ - | (1 << 3) /* MDC */ - | (1 << 2); /* MDIO */ + portd_mask = BIT(13) /* TXD0 */ + | BIT(14) /* TXD1 */ + | BIT(11) /* TXEN */ + | BIT(12) /* TXCK */ + | BIT(10) /* RXD0 */ + | BIT(6) /* RXD1 */ + | BIT(5) /* RXER */ + | BIT(4) /* RXDV */ + | BIT(3) /* MDC */ + | BIT(2); /* MDIO */ if (flags & PORTMUX_MACB_MII) - portc_mask = (1 << 19) /* COL */ - | (1 << 23) /* CRS */ - | (1 << 26) /* TXER */ - | (1 << 27) /* TXD2 */ - | (1 << 28) /* TXD3 */ - | (1 << 29) /* RXD2 */ - | (1 << 30) /* RXD3 */ - | (1 << 24); /* RXCK */ + portc_mask = BIT(19) /* COL */ + | BIT(23) /* CRS */ + | BIT(26) /* TXER */ + | BIT(27) /* TXD2 */ + | BIT(28) /* TXD3 */ + | BIT(29) /* RXD2 */ + | BIT(30) /* RXD3 */ + | BIT(24); /* RXCK */ if (flags & PORTMUX_MACB_SPEED) - portd_mask |= (1 << 15);/* SPD */ + portd_mask |= BIT(15);/* SPD */ /* REVISIT: Some pins are probably pure outputs */ portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, @@ -130,18 +130,18 @@ void portmux_enable_mmci(unsigned int slot, unsigned long flags, /* Then, the per-slot signals */ switch (slot) { case 0: - mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */ + mask = BIT(11) | BIT(12); /* CMD and DATA0 */ if (flags & PORTMUX_MMCI_4BIT) /* DATA1..DATA3 */ - mask |= (1 << 13) | (1 << 14) | (1 << 15); + mask |= BIT(13) | BIT(14) | BIT(15); portmux_select_peripheral(PORTMUX_PORT_A, mask, PORTMUX_FUNC_A, portmux_flags); break; case 1: - mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */ + mask = BIT(6) | BIT(7); /* CMD and DATA0 */ if (flags & PORTMUX_MMCI_4BIT) /* DATA1..DATA3 */ - mask |= (1 << 8) | (1 << 9) | (1 << 10); + mask |= BIT(8) | BIT(9) | BIT(10); portmux_select_peripheral(PORTMUX_PORT_B, mask, PORTMUX_FUNC_B, portmux_flags); break; @@ -155,7 +155,7 @@ void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) unsigned long pin_mask; /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2), + portmux_select_peripheral(PORTMUX_PORT_A, BIT(1) | BIT(2), PORTMUX_FUNC_A, 0); /* MISO may float */ portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0, @@ -163,7 +163,7 @@ void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) /* Set up NPCSx as GPIO outputs, initially high */ pin_mask = (cs_mask & 7) << 3; - if (cs_mask & (1 << 3)) + if (cs_mask & BIT(3)) pin_mask |= 1 << 20; portmux_select_gpio(PORTMUX_PORT_A, pin_mask, @@ -173,7 +173,7 @@ void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) { /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5), + portmux_select_peripheral(PORTMUX_PORT_B, BIT(1) | BIT(5), PORTMUX_FUNC_B, 0); /* MISO may float */ portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0, @@ -196,74 +196,74 @@ void portmux_enable_lcdc(int pin_config) switch (pin_config) { case 0: - portc_mask = (1 << 19) /* CC */ - | (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 23) /* DVAL */ - | (1 << 24) /* MODE */ - | (1 << 25) /* PWR */ - | (1 << 26) /* DATA0 */ - | (1 << 27) /* DATA1 */ - | (1 << 28) /* DATA2 */ - | (1 << 29) /* DATA3 */ - | (1 << 30) /* DATA4 */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 2) /* DATA8 */ - | (1 << 3) /* DATA9 */ - | (1 << 4) /* DATA10 */ - | (1 << 5) /* DATA11 */ - | (1 << 6) /* DATA12 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 10) /* DATA16 */ - | (1 << 11) /* DATA17 */ - | (1 << 12) /* DATA18 */ - | (1 << 13) /* DATA19 */ - | (1 << 14) /* DATA20 */ - | (1 << 15) /* DATA21 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ + portc_mask = BIT(19) /* CC */ + | BIT(20) /* HSYNC */ + | BIT(21) /* PCLK */ + | BIT(22) /* VSYNC */ + | BIT(23) /* DVAL */ + | BIT(24) /* MODE */ + | BIT(25) /* PWR */ + | BIT(26) /* DATA0 */ + | BIT(27) /* DATA1 */ + | BIT(28) /* DATA2 */ + | BIT(29) /* DATA3 */ + | BIT(30) /* DATA4 */ + | BIT(31); /* DATA5 */ + + portd_mask = BIT(0) /* DATA6 */ + | BIT(1) /* DATA7 */ + | BIT(2) /* DATA8 */ + | BIT(3) /* DATA9 */ + | BIT(4) /* DATA10 */ + | BIT(5) /* DATA11 */ + | BIT(6) /* DATA12 */ + | BIT(7) /* DATA13 */ + | BIT(8) /* DATA14 */ + | BIT(9) /* DATA15 */ + | BIT(10) /* DATA16 */ + | BIT(11) /* DATA17 */ + | BIT(12) /* DATA18 */ + | BIT(13) /* DATA19 */ + | BIT(14) /* DATA20 */ + | BIT(15) /* DATA21 */ + | BIT(16) /* DATA22 */ + | BIT(17); /* DATA23 */ break; case 1: - portc_mask = (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 25) /* PWR */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ - - porte_mask = (1 << 0) /* CC */ - | (1 << 1) /* DVAL */ - | (1 << 2) /* MODE */ - | (1 << 3) /* DATA0 */ - | (1 << 4) /* DATA1 */ - | (1 << 5) /* DATA2 */ - | (1 << 6) /* DATA3 */ - | (1 << 7) /* DATA4 */ - | (1 << 8) /* DATA8 */ - | (1 << 9) /* DATA9 */ - | (1 << 10) /* DATA10 */ - | (1 << 11) /* DATA11 */ - | (1 << 12) /* DATA12 */ - | (1 << 13) /* DATA16 */ - | (1 << 14) /* DATA17 */ - | (1 << 15) /* DATA18 */ - | (1 << 16) /* DATA19 */ - | (1 << 17) /* DATA20 */ - | (1 << 18); /* DATA21 */ + portc_mask = BIT(20) /* HSYNC */ + | BIT(21) /* PCLK */ + | BIT(22) /* VSYNC */ + | BIT(25) /* PWR */ + | BIT(31); /* DATA5 */ + + portd_mask = BIT(0) /* DATA6 */ + | BIT(1) /* DATA7 */ + | BIT(7) /* DATA13 */ + | BIT(8) /* DATA14 */ + | BIT(9) /* DATA15 */ + | BIT(16) /* DATA22 */ + | BIT(17); /* DATA23 */ + + porte_mask = BIT(0) /* CC */ + | BIT(1) /* DVAL */ + | BIT(2) /* MODE */ + | BIT(3) /* DATA0 */ + | BIT(4) /* DATA1 */ + | BIT(5) /* DATA2 */ + | BIT(6) /* DATA3 */ + | BIT(7) /* DATA4 */ + | BIT(8) /* DATA8 */ + | BIT(9) /* DATA9 */ + | BIT(10) /* DATA10 */ + | BIT(11) /* DATA11 */ + | BIT(12) /* DATA12 */ + | BIT(13) /* DATA16 */ + | BIT(14) /* DATA17 */ + | BIT(15) /* DATA18 */ + | BIT(16) /* DATA19 */ + | BIT(17) /* DATA20 */ + | BIT(18); /* DATA21 */ break; } diff --git a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h index 7b25e2e..03c1882 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/addrspace.h +++ b/arch/avr32/include/asm/arch-at32ap700x/addrspace.h @@ -52,9 +52,9 @@ static inline void * phys_to_virt(unsigned long address) * well as above 3.5GiB (internal peripherals.) */ #define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (1 << 7) -#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) -#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) +#define MAP_WRCOMBINE BIT(7) +#define MAP_WRBACK (MAP_WRCOMBINE | BIT(9)) +#define MAP_WRTHROUGH (MAP_WRBACK | BIT(0)) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) diff --git a/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/arch/avr32/include/asm/arch-at32ap700x/portmux.h index 7ae0540..4e851c6 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/portmux.h +++ b/arch/avr32/include/asm/arch-at32ap700x/portmux.h @@ -18,32 +18,32 @@ void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, unsigned long flags, unsigned long drive_strength); #define PORTMUX_EBI_CS(x) (1 << (x)) -#define PORTMUX_EBI_NAND (1 << 6) +#define PORTMUX_EBI_NAND BIT(6) #define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) -#define PORTMUX_EBI_NWAIT (1 << 9) +#define PORTMUX_EBI_NWAIT BIT(9) #ifdef AT32AP700x_CHIP_HAS_USART static inline void portmux_enable_usart0(unsigned long drive_strength) { - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), + portmux_select_peripheral(PORTMUX_PORT_A, BIT(8) | BIT(9), PORTMUX_FUNC_B, 0); } static inline void portmux_enable_usart1(unsigned long drive_strength) { - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), + portmux_select_peripheral(PORTMUX_PORT_A, BIT(17) | BIT(18), PORTMUX_FUNC_A, 0); } static inline void portmux_enable_usart2(unsigned long drive_strength) { - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), + portmux_select_peripheral(PORTMUX_PORT_B, BIT(26) | BIT(27), PORTMUX_FUNC_B, 0); } static inline void portmux_enable_usart3(unsigned long drive_strength) { - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), + portmux_select_peripheral(PORTMUX_PORT_B, BIT(17) | BIT(18), PORTMUX_FUNC_B, 0); } #endif @@ -52,17 +52,17 @@ void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); #define PORTMUX_MACB_RMII (0) -#define PORTMUX_MACB_MII (1 << 0) -#define PORTMUX_MACB_SPEED (1 << 1) +#define PORTMUX_MACB_MII BIT(0) +#define PORTMUX_MACB_SPEED BIT(1) #endif #ifdef AT32AP700x_CHIP_HAS_MMCI void portmux_enable_mmci(unsigned int slot, unsigned long flags, unsigned long drive_strength); -#define PORTMUX_MMCI_4BIT (1 << 0) -#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) -#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) +#define PORTMUX_MMCI_4BIT BIT(0) +#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | BIT(1)) +#define PORTMUX_MMCI_EXT_PULLUP BIT(2) #endif #ifdef AT32AP700x_CHIP_HAS_SPI diff --git a/arch/avr32/include/asm/arch-common/portmux-pio.h b/arch/avr32/include/asm/arch-common/portmux-pio.h index 0d4d6e0..3420bb9 100644 --- a/arch/avr32/include/asm/arch-common/portmux-pio.h +++ b/arch/avr32/include/asm/arch-common/portmux-pio.h @@ -54,17 +54,17 @@ enum portmux_function { /* Pull-down, buskeeper and drive strength are not supported */ #define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) +#define PORTMUX_DIR_OUTPUT BIT(0) #define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) +#define PORTMUX_INIT_HIGH BIT(1) +#define PORTMUX_PULL_UP BIT(2) #define PORTMUX_PULL_DOWN (0) #define PORTMUX_BUSKEEPER PORTMUX_PULL_UP #define PORTMUX_DRIVE_MIN (0) #define PORTMUX_DRIVE_LOW (0) #define PORTMUX_DRIVE_HIGH (0) #define PORTMUX_DRIVE_MAX (0) -#define PORTMUX_OPEN_DRAIN (1 << 3) +#define PORTMUX_OPEN_DRAIN BIT(3) void portmux_select_peripheral(void *port, unsigned long pin_mask, enum portmux_function func, unsigned long flags); diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 91aa5cc..02f6d02 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -49,7 +49,7 @@ void bfin_core1_start(void) bfin_write32(RCU0_CRCTL, 0); /* flag to notify cces core 1 application */ - bfin_write32(SDU0_MSG_SET, (1 << 19)); + bfin_write32(SDU0_MSG_SET, BIT(19)); #endif } #endif diff --git a/arch/blackfin/include/asm/mach-bf561/ports.h b/arch/blackfin/include/asm/mach-bf561/ports.h index 194d4a3..45b747b 100644 --- a/arch/blackfin/include/asm/mach-bf561/ports.h +++ b/arch/blackfin/include/asm/mach-bf561/ports.h @@ -8,37 +8,37 @@ #include "../mach-common/bits/ports-f.h" /* The non-standard PF16+ */ -#define PF16 (1 << 0) -#define PF17 (1 << 1) -#define PF18 (1 << 2) -#define PF19 (1 << 3) -#define PF20 (1 << 4) -#define PF21 (1 << 5) -#define PF22 (1 << 6) -#define PF23 (1 << 7) -#define PF24 (1 << 8) -#define PF25 (1 << 9) -#define PF26 (1 << 10) -#define PF27 (1 << 11) -#define PF28 (1 << 12) -#define PF29 (1 << 13) -#define PF30 (1 << 14) -#define PF31 (1 << 15) -#define PF32 (1 << 0) -#define PF33 (1 << 1) -#define PF34 (1 << 2) -#define PF35 (1 << 3) -#define PF36 (1 << 4) -#define PF37 (1 << 5) -#define PF38 (1 << 6) -#define PF39 (1 << 7) -#define PF40 (1 << 8) -#define PF41 (1 << 9) -#define PF42 (1 << 10) -#define PF43 (1 << 11) -#define PF44 (1 << 12) -#define PF45 (1 << 13) -#define PF46 (1 << 14) -#define PF47 (1 << 15) +#define PF16 BIT(0) +#define PF17 BIT(1) +#define PF18 BIT(2) +#define PF19 BIT(3) +#define PF20 BIT(4) +#define PF21 BIT(5) +#define PF22 BIT(6) +#define PF23 BIT(7) +#define PF24 BIT(8) +#define PF25 BIT(9) +#define PF26 BIT(10) +#define PF27 BIT(11) +#define PF28 BIT(12) +#define PF29 BIT(13) +#define PF30 BIT(14) +#define PF31 BIT(15) +#define PF32 BIT(0) +#define PF33 BIT(1) +#define PF34 BIT(2) +#define PF35 BIT(3) +#define PF36 BIT(4) +#define PF37 BIT(5) +#define PF38 BIT(6) +#define PF39 BIT(7) +#define PF40 BIT(8) +#define PF41 BIT(9) +#define PF42 BIT(10) +#define PF43 BIT(11) +#define PF44 BIT(12) +#define PF45 BIT(13) +#define PF46 BIT(14) +#define PF47 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h index cdf7349..829b85f 100644 --- a/arch/blackfin/include/asm/mach-common/bits/cgu.h +++ b/arch/blackfin/include/asm/mach-common/bits/cgu.h @@ -6,7 +6,7 @@ #define __BFIN_PERIPHERAL_CGU__ /* CGU_CTL Masks */ -#define DF (1 << 0) +#define DF BIT(0) #define MSEL (0x7f << MSEL_P) #define WIDLE (1 << WIDLE_P) #define LOCK (1 << LOCK_P) @@ -19,22 +19,22 @@ #define DF_MASK 0x1 /* CGU_STAT Masks */ -#define PLLEN (1 << 0) -#define PLLBP (1 << 1) -#define PLLLK (1 << 2) -#define CLKSALGN (1 << 3) -#define CCBF0EN (1 << 4) -#define CCBF1EN (1 << 5) -#define SCBF0EN (1 << 6) -#define SCBF1EN (1 << 7) -#define DCBFEN (1 << 8) -#define OCBFEN (1 << 9) -#define ADRERR (1 << 16) -#define LWERR (1 << 17) -#define DIVERR (1 << 18) -#define WDFMSERR (1 << 19) -#define WDIVERR (1 << 20) -#define PLLLKERR (1 << 21) +#define PLLEN BIT(0) +#define PLLBP BIT(1) +#define PLLLK BIT(2) +#define CLKSALGN BIT(3) +#define CCBF0EN BIT(4) +#define CCBF1EN BIT(5) +#define SCBF0EN BIT(6) +#define SCBF1EN BIT(7) +#define DCBFEN BIT(8) +#define OCBFEN BIT(9) +#define ADRERR BIT(16) +#define LWERR BIT(17) +#define DIVERR BIT(18) +#define WDFMSERR BIT(19) +#define WDIVERR BIT(20) +#define PLLLKERR BIT(21) /* CGU_DIV Masks */ #define CSEL (0x1f << CSEL_P) diff --git a/arch/blackfin/include/asm/mach-common/bits/eppi.h b/arch/blackfin/include/asm/mach-common/bits/eppi.h index fb1456f..b4702ad 100644 --- a/arch/blackfin/include/asm/mach-common/bits/eppi.h +++ b/arch/blackfin/include/asm/mach-common/bits/eppi.h @@ -44,7 +44,7 @@ #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ #define DLEN_8 (0 << 15) /* 000 - 8 bits */ -#define DLEN_10 (1 << 15) /* 001 - 10 bits */ +#define DLEN_10 BIT(15) /* 001 - 10 bits */ #define DLEN_12 (2 << 15) /* 010 - 12 bits */ #define DLEN_14 (3 << 15) /* 011 - 14 bits */ #define DLEN_16 (4 << 15) /* 100 - 16 bits */ diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-a.h b/arch/blackfin/include/asm/mach-common/bits/ports-a.h index 9f78a76..c4a97ef 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-a.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-a.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_A__ #define __BFIN_PERIPHERAL_PORT_A__ -#define PA0 (1 << 0) -#define PA1 (1 << 1) -#define PA2 (1 << 2) -#define PA3 (1 << 3) -#define PA4 (1 << 4) -#define PA5 (1 << 5) -#define PA6 (1 << 6) -#define PA7 (1 << 7) -#define PA8 (1 << 8) -#define PA9 (1 << 9) -#define PA10 (1 << 10) -#define PA11 (1 << 11) -#define PA12 (1 << 12) -#define PA13 (1 << 13) -#define PA14 (1 << 14) -#define PA15 (1 << 15) +#define PA0 BIT(0) +#define PA1 BIT(1) +#define PA2 BIT(2) +#define PA3 BIT(3) +#define PA4 BIT(4) +#define PA5 BIT(5) +#define PA6 BIT(6) +#define PA7 BIT(7) +#define PA8 BIT(8) +#define PA9 BIT(9) +#define PA10 BIT(10) +#define PA11 BIT(11) +#define PA12 BIT(12) +#define PA13 BIT(13) +#define PA14 BIT(14) +#define PA15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-b.h b/arch/blackfin/include/asm/mach-common/bits/ports-b.h index b81702f..c84cff4 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-b.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-b.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_B__ #define __BFIN_PERIPHERAL_PORT_B__ -#define PB0 (1 << 0) -#define PB1 (1 << 1) -#define PB2 (1 << 2) -#define PB3 (1 << 3) -#define PB4 (1 << 4) -#define PB5 (1 << 5) -#define PB6 (1 << 6) -#define PB7 (1 << 7) -#define PB8 (1 << 8) -#define PB9 (1 << 9) -#define PB10 (1 << 10) -#define PB11 (1 << 11) -#define PB12 (1 << 12) -#define PB13 (1 << 13) -#define PB14 (1 << 14) -#define PB15 (1 << 15) +#define PB0 BIT(0) +#define PB1 BIT(1) +#define PB2 BIT(2) +#define PB3 BIT(3) +#define PB4 BIT(4) +#define PB5 BIT(5) +#define PB6 BIT(6) +#define PB7 BIT(7) +#define PB8 BIT(8) +#define PB9 BIT(9) +#define PB10 BIT(10) +#define PB11 BIT(11) +#define PB12 BIT(12) +#define PB13 BIT(13) +#define PB14 BIT(14) +#define PB15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-c.h b/arch/blackfin/include/asm/mach-common/bits/ports-c.h index 3cc665e..3253855 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-c.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-c.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_C__ #define __BFIN_PERIPHERAL_PORT_C__ -#define PC0 (1 << 0) -#define PC1 (1 << 1) -#define PC2 (1 << 2) -#define PC3 (1 << 3) -#define PC4 (1 << 4) -#define PC5 (1 << 5) -#define PC6 (1 << 6) -#define PC7 (1 << 7) -#define PC8 (1 << 8) -#define PC9 (1 << 9) -#define PC10 (1 << 10) -#define PC11 (1 << 11) -#define PC12 (1 << 12) -#define PC13 (1 << 13) -#define PC14 (1 << 14) -#define PC15 (1 << 15) +#define PC0 BIT(0) +#define PC1 BIT(1) +#define PC2 BIT(2) +#define PC3 BIT(3) +#define PC4 BIT(4) +#define PC5 BIT(5) +#define PC6 BIT(6) +#define PC7 BIT(7) +#define PC8 BIT(8) +#define PC9 BIT(9) +#define PC10 BIT(10) +#define PC11 BIT(11) +#define PC12 BIT(12) +#define PC13 BIT(13) +#define PC14 BIT(14) +#define PC15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-d.h b/arch/blackfin/include/asm/mach-common/bits/ports-d.h index 868c6a0..c782afd 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-d.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-d.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_D__ #define __BFIN_PERIPHERAL_PORT_D__ -#define PD0 (1 << 0) -#define PD1 (1 << 1) -#define PD2 (1 << 2) -#define PD3 (1 << 3) -#define PD4 (1 << 4) -#define PD5 (1 << 5) -#define PD6 (1 << 6) -#define PD7 (1 << 7) -#define PD8 (1 << 8) -#define PD9 (1 << 9) -#define PD10 (1 << 10) -#define PD11 (1 << 11) -#define PD12 (1 << 12) -#define PD13 (1 << 13) -#define PD14 (1 << 14) -#define PD15 (1 << 15) +#define PD0 BIT(0) +#define PD1 BIT(1) +#define PD2 BIT(2) +#define PD3 BIT(3) +#define PD4 BIT(4) +#define PD5 BIT(5) +#define PD6 BIT(6) +#define PD7 BIT(7) +#define PD8 BIT(8) +#define PD9 BIT(9) +#define PD10 BIT(10) +#define PD11 BIT(11) +#define PD12 BIT(12) +#define PD13 BIT(13) +#define PD14 BIT(14) +#define PD15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-e.h b/arch/blackfin/include/asm/mach-common/bits/ports-e.h index c88b0d0..63c7ecc 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-e.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-e.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_E__ #define __BFIN_PERIPHERAL_PORT_E__ -#define PE0 (1 << 0) -#define PE1 (1 << 1) -#define PE2 (1 << 2) -#define PE3 (1 << 3) -#define PE4 (1 << 4) -#define PE5 (1 << 5) -#define PE6 (1 << 6) -#define PE7 (1 << 7) -#define PE8 (1 << 8) -#define PE9 (1 << 9) -#define PE10 (1 << 10) -#define PE11 (1 << 11) -#define PE12 (1 << 12) -#define PE13 (1 << 13) -#define PE14 (1 << 14) -#define PE15 (1 << 15) +#define PE0 BIT(0) +#define PE1 BIT(1) +#define PE2 BIT(2) +#define PE3 BIT(3) +#define PE4 BIT(4) +#define PE5 BIT(5) +#define PE6 BIT(6) +#define PE7 BIT(7) +#define PE8 BIT(8) +#define PE9 BIT(9) +#define PE10 BIT(10) +#define PE11 BIT(11) +#define PE12 BIT(12) +#define PE13 BIT(13) +#define PE14 BIT(14) +#define PE15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-f.h b/arch/blackfin/include/asm/mach-common/bits/ports-f.h index d6af206..bedd9ac 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-f.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-f.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_F__ #define __BFIN_PERIPHERAL_PORT_F__ -#define PF0 (1 << 0) -#define PF1 (1 << 1) -#define PF2 (1 << 2) -#define PF3 (1 << 3) -#define PF4 (1 << 4) -#define PF5 (1 << 5) -#define PF6 (1 << 6) -#define PF7 (1 << 7) -#define PF8 (1 << 8) -#define PF9 (1 << 9) -#define PF10 (1 << 10) -#define PF11 (1 << 11) -#define PF12 (1 << 12) -#define PF13 (1 << 13) -#define PF14 (1 << 14) -#define PF15 (1 << 15) +#define PF0 BIT(0) +#define PF1 BIT(1) +#define PF2 BIT(2) +#define PF3 BIT(3) +#define PF4 BIT(4) +#define PF5 BIT(5) +#define PF6 BIT(6) +#define PF7 BIT(7) +#define PF8 BIT(8) +#define PF9 BIT(9) +#define PF10 BIT(10) +#define PF11 BIT(11) +#define PF12 BIT(12) +#define PF13 BIT(13) +#define PF14 BIT(14) +#define PF15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-g.h b/arch/blackfin/include/asm/mach-common/bits/ports-g.h index 09355d3..07081d6 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-g.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-g.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_G__ #define __BFIN_PERIPHERAL_PORT_G__ -#define PG0 (1 << 0) -#define PG1 (1 << 1) -#define PG2 (1 << 2) -#define PG3 (1 << 3) -#define PG4 (1 << 4) -#define PG5 (1 << 5) -#define PG6 (1 << 6) -#define PG7 (1 << 7) -#define PG8 (1 << 8) -#define PG9 (1 << 9) -#define PG10 (1 << 10) -#define PG11 (1 << 11) -#define PG12 (1 << 12) -#define PG13 (1 << 13) -#define PG14 (1 << 14) -#define PG15 (1 << 15) +#define PG0 BIT(0) +#define PG1 BIT(1) +#define PG2 BIT(2) +#define PG3 BIT(3) +#define PG4 BIT(4) +#define PG5 BIT(5) +#define PG6 BIT(6) +#define PG7 BIT(7) +#define PG8 BIT(8) +#define PG9 BIT(9) +#define PG10 BIT(10) +#define PG11 BIT(11) +#define PG12 BIT(12) +#define PG13 BIT(13) +#define PG14 BIT(14) +#define PG15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-h.h b/arch/blackfin/include/asm/mach-common/bits/ports-h.h index fa3910c..e97cba7 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-h.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-h.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_H__ #define __BFIN_PERIPHERAL_PORT_H__ -#define PH0 (1 << 0) -#define PH1 (1 << 1) -#define PH2 (1 << 2) -#define PH3 (1 << 3) -#define PH4 (1 << 4) -#define PH5 (1 << 5) -#define PH6 (1 << 6) -#define PH7 (1 << 7) -#define PH8 (1 << 8) -#define PH9 (1 << 9) -#define PH10 (1 << 10) -#define PH11 (1 << 11) -#define PH12 (1 << 12) -#define PH13 (1 << 13) -#define PH14 (1 << 14) -#define PH15 (1 << 15) +#define PH0 BIT(0) +#define PH1 BIT(1) +#define PH2 BIT(2) +#define PH3 BIT(3) +#define PH4 BIT(4) +#define PH5 BIT(5) +#define PH6 BIT(6) +#define PH7 BIT(7) +#define PH8 BIT(8) +#define PH9 BIT(9) +#define PH10 BIT(10) +#define PH11 BIT(11) +#define PH12 BIT(12) +#define PH13 BIT(13) +#define PH14 BIT(14) +#define PH15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-i.h b/arch/blackfin/include/asm/mach-common/bits/ports-i.h index f176f08..e219f64 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-i.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-i.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_I__ #define __BFIN_PERIPHERAL_PORT_I__ -#define PI0 (1 << 0) -#define PI1 (1 << 1) -#define PI2 (1 << 2) -#define PI3 (1 << 3) -#define PI4 (1 << 4) -#define PI5 (1 << 5) -#define PI6 (1 << 6) -#define PI7 (1 << 7) -#define PI8 (1 << 8) -#define PI9 (1 << 9) -#define PI10 (1 << 10) -#define PI11 (1 << 11) -#define PI12 (1 << 12) -#define PI13 (1 << 13) -#define PI14 (1 << 14) -#define PI15 (1 << 15) +#define PI0 BIT(0) +#define PI1 BIT(1) +#define PI2 BIT(2) +#define PI3 BIT(3) +#define PI4 BIT(4) +#define PI5 BIT(5) +#define PI6 BIT(6) +#define PI7 BIT(7) +#define PI8 BIT(8) +#define PI9 BIT(9) +#define PI10 BIT(10) +#define PI11 BIT(11) +#define PI12 BIT(12) +#define PI13 BIT(13) +#define PI14 BIT(14) +#define PI15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-j.h b/arch/blackfin/include/asm/mach-common/bits/ports-j.h index 924123e..a0dea25 100644 --- a/arch/blackfin/include/asm/mach-common/bits/ports-j.h +++ b/arch/blackfin/include/asm/mach-common/bits/ports-j.h @@ -5,21 +5,21 @@ #ifndef __BFIN_PERIPHERAL_PORT_J__ #define __BFIN_PERIPHERAL_PORT_J__ -#define PJ0 (1 << 0) -#define PJ1 (1 << 1) -#define PJ2 (1 << 2) -#define PJ3 (1 << 3) -#define PJ4 (1 << 4) -#define PJ5 (1 << 5) -#define PJ6 (1 << 6) -#define PJ7 (1 << 7) -#define PJ8 (1 << 8) -#define PJ9 (1 << 9) -#define PJ10 (1 << 10) -#define PJ11 (1 << 11) -#define PJ12 (1 << 12) -#define PJ13 (1 << 13) -#define PJ14 (1 << 14) -#define PJ15 (1 << 15) +#define PJ0 BIT(0) +#define PJ1 BIT(1) +#define PJ2 BIT(2) +#define PJ3 BIT(3) +#define PJ4 BIT(4) +#define PJ5 BIT(5) +#define PJ6 BIT(6) +#define PJ7 BIT(7) +#define PJ8 BIT(8) +#define PJ9 BIT(9) +#define PJ10 BIT(10) +#define PJ11 BIT(11) +#define PJ12 BIT(12) +#define PJ13 BIT(13) +#define PJ14 BIT(14) +#define PJ15 BIT(15) #endif diff --git a/arch/blackfin/include/asm/mach-common/bits/uart4.h b/arch/blackfin/include/asm/mach-common/bits/uart4.h index 37808de..ab66cf4 100644 --- a/arch/blackfin/include/asm/mach-common/bits/uart4.h +++ b/arch/blackfin/include/asm/mach-common/bits/uart4.h @@ -6,61 +6,61 @@ #define __BFIN_PERIPHERAL_UART4__ /* UART_CONTROL */ -#define UEN (1 << 0) -#define LOOP_ENA (1 << 1) +#define UEN BIT(0) +#define LOOP_ENA BIT(1) #define UMOD (3 << 4) #define UMOD_UART (0 << 4) -#define UMOD_MDB (1 << 4) -#define UMOD_IRDA (1 << 4) +#define UMOD_MDB BIT(4) +#define UMOD_IRDA BIT(4) #define WLS (3 << 8) #define WLS_5 (0 << 8) -#define WLS_6 (1 << 8) +#define WLS_6 BIT(8) #define WLS_7 (2 << 8) #define WLS_8 (3 << 8) -#define STB (1 << 12) -#define STBH (1 << 13) -#define PEN (1 << 14) -#define EPS (1 << 15) -#define STP (1 << 16) -#define FPE (1 << 17) -#define FFE (1 << 18) -#define SB (1 << 19) -#define FCPOL (1 << 22) -#define RPOLC (1 << 23) -#define TPOLC (1 << 24) -#define MRTS (1 << 25) -#define XOFF (1 << 26) -#define ARTS (1 << 27) -#define ACTS (1 << 28) -#define RFIT (1 << 29) -#define RFRT (1 << 30) +#define STB BIT(12) +#define STBH BIT(13) +#define PEN BIT(14) +#define EPS BIT(15) +#define STP BIT(16) +#define FPE BIT(17) +#define FFE BIT(18) +#define SB BIT(19) +#define FCPOL BIT(22) +#define RPOLC BIT(23) +#define TPOLC BIT(24) +#define MRTS BIT(25) +#define XOFF BIT(26) +#define ARTS BIT(27) +#define ACTS BIT(28) +#define RFIT BIT(29) +#define RFRT BIT(30) /* UART_STATUS */ -#define DR (1 << 0) -#define OE (1 << 1) -#define PE (1 << 2) -#define FE (1 << 3) -#define BI (1 << 4) -#define THRE (1 << 5) -#define TEMT (1 << 7) -#define TFI (1 << 8) -#define ASTKY (1 << 9) -#define ADDR (1 << 10) -#define RO (1 << 11) -#define SCTS (1 << 12) -#define CTS (1 << 16) -#define RFCS (1 << 17) +#define DR BIT(0) +#define OE BIT(1) +#define PE BIT(2) +#define FE BIT(3) +#define BI BIT(4) +#define THRE BIT(5) +#define TEMT BIT(7) +#define TFI BIT(8) +#define ASTKY BIT(9) +#define ADDR BIT(10) +#define RO BIT(11) +#define SCTS BIT(12) +#define CTS BIT(16) +#define RFCS BIT(17) /* UART_EMASK */ -#define ERBFI (1 << 0) -#define ETBEI (1 << 1) -#define ELSI (1 << 2) -#define EDSSI (1 << 3) -#define EDTPTI (1 << 4) -#define ETFI (1 << 5) -#define ERFCI (1 << 6) -#define EAWI (1 << 7) -#define ERXS (1 << 8) -#define ETXS (1 << 9) +#define ERBFI BIT(0) +#define ETBEI BIT(1) +#define ELSI BIT(2) +#define EDSSI BIT(3) +#define EDTPTI BIT(4) +#define ETFI BIT(5) +#define ERFCI BIT(6) +#define EAWI BIT(7) +#define ERXS BIT(8) +#define ETXS BIT(9) #endif diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c index 44de4a6..d7641bb 100644 --- a/arch/m68k/cpu/mcf5227x/speed.c +++ b/arch/m68k/cpu/mcf5227x/speed.c @@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; /* * Low Power Divider specifications */ -#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ -#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ +#define CLOCK_LPD_MIN BIT(0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX BIT(15) /* Divider (decoded) */ #define CLOCK_PLL_FVCO_MAX 540000000 #define CLOCK_PLL_FVCO_MIN 300000000 diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index a440bbb..c82e53a 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -40,9 +40,9 @@ DECLARE_GLOBAL_DATA_PTR; #define MIN_MFD 88 /* Multiplier */ /* Low Power Divider specifications */ -#define MIN_LPD (1 << 0) /* Divider (not encoded) */ -#define MAX_LPD (1 << 15) /* Divider (not encoded) */ -#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ +#define MIN_LPD BIT(0) /* Divider (not encoded) */ +#define MAX_LPD BIT(15) /* Divider (not encoded) */ +#define DEFAULT_LPD BIT(1) /* Divider (not encoded) */ #endif #define BUSDIV 6 /* Divider */ diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 4e363a4..8dda64c 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; /* * Low Power Divider specifications */ -#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ -#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ +#define CLOCK_LPD_MIN BIT(0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX BIT(15) /* Divider (decoded) */ #define CLOCK_PLL_FVCO_MAX 540000000 #define CLOCK_PLL_FVCO_MIN 300000000 diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 812f25c..5585e50 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -30,23 +30,23 @@ /* V2 Core */ #ifdef CONFIG_CF_V2 -#define CF_CACR_CENB (1 << 31) -#define CF_CACR_CPD (1 << 28) -#define CF_CACR_CFRZ (1 << 27) -#define CF_CACR_CEIB (1 << 10) -#define CF_CACR_DCM (1 << 9) -#define CF_CACR_DBWE (1 << 8) +#define CF_CACR_CENB BIT(31) +#define CF_CACR_CPD BIT(28) +#define CF_CACR_CFRZ BIT(27) +#define CF_CACR_CEIB BIT(10) +#define CF_CACR_DCM BIT(9) +#define CF_CACR_DBWE BIT(8) #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) -#define CF_CACR_DWP (1 << 6) +#define CF_CACR_DWP BIT(6) #else -#define CF_CACR_CINV (1 << 24) -#define CF_CACR_DISI (1 << 23) -#define CF_CACR_DISD (1 << 22) -#define CF_CACR_INVI (1 << 21) -#define CF_CACR_INVD (1 << 20) -#define CF_CACR_DWP (1 << 5) -#define CF_CACR_EUSP (1 << 4) +#define CF_CACR_CINV BIT(24) +#define CF_CACR_DISI BIT(23) +#define CF_CACR_DISD BIT(22) +#define CF_CACR_INVI BIT(21) +#define CF_CACR_INVD BIT(20) +#define CF_CACR_DWP BIT(5) +#define CF_CACR_EUSP BIT(4) #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ #endif /* CONFIG_CF_V2 */ @@ -54,54 +54,54 @@ /* V3 Core */ #ifdef CONFIG_CF_V3 -#define CF_CACR_EC (1 << 31) -#define CF_CACR_ESB (1 << 29) -#define CF_CACR_DPI (1 << 28) -#define CF_CACR_HLCK (1 << 27) -#define CF_CACR_CINVA (1 << 24) -#define CF_CACR_DNFB (1 << 10) +#define CF_CACR_EC BIT(31) +#define CF_CACR_ESB BIT(29) +#define CF_CACR_DPI BIT(28) +#define CF_CACR_HLCK BIT(27) +#define CF_CACR_CINVA BIT(24) +#define CF_CACR_DNFB BIT(10) #define CF_CACR_DCM_UNMASK 0xFFFFFCFF #define CF_CACR_DCM_WT (0 << 8) -#define CF_CACR_DCM_CB (1 << 8) +#define CF_CACR_DCM_CB BIT(8) #define CF_CACR_DCM_P (2 << 8) #define CF_CACR_DCM_IP (3 << 8) -#define CF_CACR_DW (1 << 5) -#define CF_CACR_EUSP (1 << 4) +#define CF_CACR_DW BIT(5) +#define CF_CACR_EUSP BIT(4) #endif /* CONFIG_CF_V3 */ /* V4 Core */ #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) -#define CF_CACR_DEC (1 << 31) -#define CF_CACR_DW (1 << 30) -#define CF_CACR_DESB (1 << 29) -#define CF_CACR_DDPI (1 << 28) -#define CF_CACR_DHLCK (1 << 27) +#define CF_CACR_DEC BIT(31) +#define CF_CACR_DW BIT(30) +#define CF_CACR_DESB BIT(29) +#define CF_CACR_DDPI BIT(28) +#define CF_CACR_DHLCK BIT(27) #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) #define CF_CACR_DDCM_WT (0 << 25) -#define CF_CACR_DDCM_CB (1 << 25) +#define CF_CACR_DDCM_CB BIT(25) #define CF_CACR_DDCM_P (2 << 25) #define CF_CACR_DDCM_IP (3 << 25) -#define CF_CACR_DCINVA (1 << 24) - -#define CF_CACR_DDSP (1 << 23) -#define CF_CACR_BEC (1 << 19) -#define CF_CACR_BCINVA (1 << 18) -#define CF_CACR_IEC (1 << 15) -#define CF_CACR_DNFB (1 << 13) -#define CF_CACR_IDPI (1 << 12) -#define CF_CACR_IHLCK (1 << 11) -#define CF_CACR_IDCM (1 << 10) -#define CF_CACR_ICINVA (1 << 8) -#define CF_CACR_IDSP (1 << 7) -#define CF_CACR_EUSP (1 << 5) +#define CF_CACR_DCINVA BIT(24) + +#define CF_CACR_DDSP BIT(23) +#define CF_CACR_BEC BIT(19) +#define CF_CACR_BCINVA BIT(18) +#define CF_CACR_IEC BIT(15) +#define CF_CACR_DNFB BIT(13) +#define CF_CACR_IDPI BIT(12) +#define CF_CACR_IHLCK BIT(11) +#define CF_CACR_IDCM BIT(10) +#define CF_CACR_ICINVA BIT(8) +#define CF_CACR_IDSP BIT(7) +#define CF_CACR_EUSP BIT(5) #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) -#define CF_CACR_IVO (1 << 20) -#define CF_CACR_SPA (1 << 14) +#define CF_CACR_IVO BIT(20) +#define CF_CACR_SPA BIT(14) #else -#define CF_CACR_DF (1 << 4) +#define CF_CACR_DF BIT(4) #endif #endif /* CONFIG_CF_V4 */ @@ -111,30 +111,30 @@ #define CF_ACR_ADR(x) ((x & 0xFF) << 24) #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) -#define CF_ACR_EN (1 << 15) +#define CF_ACR_EN BIT(15) #define CF_ACR_SM_UNMASK (0xFFFF9FFF) #define CF_ACR_SM_UM (0 << 13) -#define CF_ACR_SM_SM (1 << 13) +#define CF_ACR_SM_SM BIT(13) #define CF_ACR_SM_ALL (3 << 13) -#define CF_ACR_WP (1 << 2) +#define CF_ACR_WP BIT(2) /* V2 Core */ #ifdef CONFIG_CF_V2 -#define CF_ACR_CM (1 << 6) -#define CF_ACR_BWE (1 << 5) +#define CF_ACR_CM BIT(6) +#define CF_ACR_BWE BIT(5) #else /* V3 & V4 */ #define CF_ACR_CM_UNMASK (0xFFFFFF9F) #define CF_ACR_CM_WT (0 << 5) -#define CF_ACR_CM_CB (1 << 5) +#define CF_ACR_CM_CB BIT(5) #define CF_ACR_CM_P (2 << 5) #define CF_ACR_CM_IP (3 << 5) #endif /* CONFIG_CF_V2 */ /* V4 Core */ #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) -#define CF_ACR_AMM (1 << 10) -#define CF_ACR_SP (1 << 3) +#define CF_ACR_AMM BIT(10) +#define CF_ACR_SP BIT(3) #endif /* CONFIG_CF_V4 */ diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h index e44cbb3..a4d1e93 100644 --- a/arch/m68k/include/asm/coldfire/flexbus.h +++ b/arch/m68k/include/asm/coldfire/flexbus.h @@ -132,16 +132,16 @@ typedef struct fbcs { #ifdef CONFIG_M5235 #define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) #define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) -#define FBCS_CSCR_AA_ON (1 << 8) +#define FBCS_CSCR_AA_ON BIT(8) #define FBCS_CSCR_AA_OFF (0 << 8) #define FBCS_CSCR_PS_32 (0 << 6) #define FBCS_CSCR_PS_16 (2 << 6) -#define FBCS_CSCR_PS_8 (1 << 6) -#define FBCS_CSCR_BEM_ON (1 << 5) +#define FBCS_CSCR_PS_8 BIT(6) +#define FBCS_CSCR_BEM_ON BIT(5) #define FBCS_CSCR_BEM_OFF (0 << 5) -#define FBCS_CSCR_BSTR_ON (1 << 4) +#define FBCS_CSCR_BSTR_ON BIT(4) #define FBCS_CSCR_BSTR_OFF (0 << 4) -#define FBCS_CSCR_BSTW_ON (1 << 3) +#define FBCS_CSCR_BSTW_ON BIT(3) #define FBCS_CSCR_BSTW_OFF (0 << 3) #define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) #else diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h index 7a7cfff..4f1baef 100644 --- a/arch/mips/include/asm/jz4740.h +++ b/arch/mips/include/asm/jz4740.h @@ -133,14 +133,14 @@ #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) +#define EMC_SMCR_BCM BIT(3) #define EMC_SMCR_BL_BIT 1 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) +#define EMC_SMCR_SMT BIT(0) /* Static Memory Bank Addr Config Reg */ #define EMC_SACR_BASE_BIT 8 @@ -149,23 +149,23 @@ #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) /* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) +#define EMC_NFCSR_NFCE4 BIT(7) /* NAND Flash Enable */ +#define EMC_NFCSR_NFE4 BIT(6) /* NAND Flash FCE# Assertion Enable */ +#define EMC_NFCSR_NFCE3 BIT(5) +#define EMC_NFCSR_NFE3 BIT(4) +#define EMC_NFCSR_NFCE2 BIT(3) +#define EMC_NFCSR_NFE2 BIT(2) +#define EMC_NFCSR_NFCE1 BIT(1) +#define EMC_NFCSR_NFE1 BIT(0) /* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ +#define EMC_NFECR_PRDY BIT(4) /* Parity Ready */ #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ +#define EMC_NFECR_RS_ENCODING BIT(3) /* RS is in encoding phase */ #define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ +#define EMC_NFECR_RS BIT(2) /* Select RS Correction Algorithm */ +#define EMC_NFECR_ERST BIT(1) /* ECC Reset */ +#define EMC_NFECR_ECCE BIT(0) /* ECC Enable */ /* NAND Flash ECC Data Register */ #define EMC_NFECC_ECC2_BIT 16 @@ -178,18 +178,18 @@ /* NAND Flash Interrupt Status Register */ #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ +#define EMC_NFINTS_PADF BIT(4) /* Padding Finished */ +#define EMC_NFINTS_DECF BIT(3) /* Decoding Finished */ +#define EMC_NFINTS_ENCF BIT(2) /* Encoding Finished */ +#define EMC_NFINTS_UNCOR BIT(1) /* Uncorrectable Error Occurred */ +#define EMC_NFINTS_ERR BIT(0) /* Error Occurred */ /* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ +#define EMC_NFINTE_PADFE BIT(4) /* Padding Finished Interrupt */ +#define EMC_NFINTE_DECFE BIT(3) /* Decoding Finished Interrupt */ +#define EMC_NFINTE_ENCFE BIT(2) /* Encoding Finished Interrupt */ +#define EMC_NFINTE_UNCORE BIT(1) /* Uncorrectable Error Occurred Intr */ +#define EMC_NFINTE_ERRE BIT(0) /* Error Occurred Interrupt */ /* NAND Flash RS Error Report Register */ #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ @@ -207,9 +207,9 @@ #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) +#define EMC_DMCR_RMODE BIT(25) +#define EMC_DMCR_RFSH BIT(24) +#define EMC_DMCR_MRSET BIT(23) #define EMC_DMCR_RA_BIT 20 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) @@ -217,8 +217,8 @@ #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) #define EMC_DMCR_BA_BIT 19 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) +#define EMC_DMCR_PDM BIT(18) +#define EMC_DMCR_EPIN BIT(17) #define EMC_DMCR_TRAS_BIT 13 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) #define EMC_DMCR_RCD_BIT 11 @@ -233,7 +233,7 @@ #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) /* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) +#define EMC_RTCSR_CMF BIT(7) #define EMC_RTCSR_CKS_BIT 0 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) @@ -252,7 +252,7 @@ #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) /* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ +#define EMC_SDMR_BM BIT(9) /* Write Burst Mode */ #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) @@ -282,23 +282,23 @@ (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) /* RTC Control Register */ -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ -#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ +#define RTC_RCR_WRDY BIT(7) /* Write Ready Flag */ +#define RTC_RCR_HZ BIT(6) /* 1Hz Flag */ +#define RTC_RCR_HZIE BIT(5) /* 1Hz Interrupt Enable */ +#define RTC_RCR_AF BIT(4) /* Alarm Flag */ +#define RTC_RCR_AIE BIT(3) /* Alarm Interrupt Enable */ +#define RTC_RCR_AE BIT(2) /* Alarm Enable */ +#define RTC_RCR_RTCE BIT(0) /* RTC Enable */ /* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ +#define RTC_RGR_LOCK BIT(31) /* Lock Bit */ #define RTC_RGR_ADJC_BIT 16 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) #define RTC_RGR_NC1HZ_BIT 0 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) /* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ +#define RTC_HCR_PD BIT(0) /* Power Down */ /* Hibernate Wakeup Filter Counter Register */ #define RTC_HWFCR_BIT 5 @@ -309,22 +309,22 @@ #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) /* Hibernate Wakeup Control Register */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ +#define RTC_HWCR_EALM BIT(0) /* RTC alarm wakeup enable */ /* Hibernate Wakeup Status Register */ -#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ -#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ +#define RTC_HWRSR_HR BIT(5) /* Hibernate reset */ +#define RTC_HWRSR_PPR BIT(4) /* PPR reset */ +#define RTC_HWRSR_PIN BIT(1) /* Wakeup pin status bit */ +#define RTC_HWRSR_ALM BIT(0) /* RTC alarm status bit */ /* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_CLKOEN (1 << 30) -#define CPM_CPCCR_UCS (1 << 29) +#define CPM_CPCCR_I2CS BIT(31) +#define CPM_CPCCR_CLKOEN BIT(30) +#define CPM_CPCCR_UCS BIT(29) #define CPM_CPCCR_UDIV_BIT 23 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) +#define CPM_CPCCR_CE BIT(22) +#define CPM_CPCCR_PCS BIT(21) #define CPM_CPCCR_LDIV_BIT 16 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) #define CPM_CPCCR_MDIV_BIT 12 @@ -355,48 +355,48 @@ #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) #define CPM_CPPCR_PLLOD_BIT 16 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) +#define CPM_CPPCR_PLLS BIT(10) +#define CPM_CPPCR_PLLBP BIT(9) +#define CPM_CPPCR_PLLEN BIT(8) #define CPM_CPPCR_PLLST_BIT 0 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) /* Low Power Control Register */ #define CPM_LCR_DOZE_DUTY_BIT 3 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) -#define CPM_LCR_DOZE_ON (1 << 2) +#define CPM_LCR_DOZE_ON BIT(2) #define CPM_LCR_LPM_BIT 0 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) /* Clock Gate Register */ -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) +#define CPM_CLKGR_UART1 BIT(15) +#define CPM_CLKGR_UHC BIT(14) +#define CPM_CLKGR_IPU BIT(13) +#define CPM_CLKGR_DMAC BIT(12) +#define CPM_CLKGR_UDC BIT(11) +#define CPM_CLKGR_LCD BIT(10) +#define CPM_CLKGR_CIM BIT(9) +#define CPM_CLKGR_SADC BIT(8) +#define CPM_CLKGR_MSC BIT(7) +#define CPM_CLKGR_AIC1 BIT(6) +#define CPM_CLKGR_AIC2 BIT(5) +#define CPM_CLKGR_SSI BIT(4) +#define CPM_CLKGR_I2C BIT(3) +#define CPM_CLKGR_RTC BIT(2) +#define CPM_CLKGR_TCU BIT(1) +#define CPM_CLKGR_UART0 BIT(0) /* Sleep Control Register */ #define CPM_SCR_O1ST_BIT 8 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_SCR_UDCPHY_ENABLE (1 << 6) -#define CPM_SCR_USBPHY_DISABLE (1 << 7) -#define CPM_SCR_OSC_ENABLE (1 << 4) +#define CPM_SCR_UDCPHY_ENABLE BIT(6) +#define CPM_SCR_USBPHY_DISABLE BIT(7) +#define CPM_SCR_OSC_ENABLE BIT(4) /* Hibernate Control Register */ -#define CPM_HCR_PD (1 << 0) +#define CPM_HCR_PD BIT(0) /* Wakeup Filter Counter Register in Hibernate Mode */ #define CPM_HWFCR_TIME_BIT 0 @@ -408,23 +408,23 @@ /* Wakeup Control Register in Hibernate Mode */ #define CPM_HWCR_WLE_LOW (0 << 2) -#define CPM_HWCR_WLE_HIGH (1 << 2) -#define CPM_HWCR_PIN_WAKEUP (1 << 1) -#define CPM_HWCR_RTC_WAKEUP (1 << 0) +#define CPM_HWCR_WLE_HIGH BIT(2) +#define CPM_HWCR_PIN_WAKEUP BIT(1) +#define CPM_HWCR_RTC_WAKEUP BIT(0) /* Wakeup Status Register in Hibernate Mode */ -#define CPM_HWSR_WSR_PIN (1 << 1) -#define CPM_HWSR_WSR_RTC (1 << 0) +#define CPM_HWSR_WSR_PIN BIT(1) +#define CPM_HWSR_WSR_RTC BIT(0) /* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) -#define CPM_RSR_WR (1 << 1) -#define CPM_RSR_PR (1 << 0) +#define CPM_RSR_HR BIT(2) +#define CPM_RSR_WR BIT(1) +#define CPM_RSR_PR BIT(0) /* Register definitions */ -#define TCU_TCSR_PWM_SD (1 << 9) -#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) -#define TCU_TCSR_PWM_EN (1 << 7) +#define TCU_TCSR_PWM_SD BIT(9) +#define TCU_TCSR_PWM_INITL_HIGH BIT(8) +#define TCU_TCSR_PWM_EN BIT(7) #define TCU_TCSR_PRESCALE_BIT 3 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) @@ -433,132 +433,132 @@ #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_EXT_EN (1 << 2) -#define TCU_TCSR_RTC_EN (1 << 1) -#define TCU_TCSR_PCK_EN (1 << 0) - -#define TCU_TER_TCEN5 (1 << 5) -#define TCU_TER_TCEN4 (1 << 4) -#define TCU_TER_TCEN3 (1 << 3) -#define TCU_TER_TCEN2 (1 << 2) -#define TCU_TER_TCEN1 (1 << 1) -#define TCU_TER_TCEN0 (1 << 0) - -#define TCU_TESR_TCST5 (1 << 5) -#define TCU_TESR_TCST4 (1 << 4) -#define TCU_TESR_TCST3 (1 << 3) -#define TCU_TESR_TCST2 (1 << 2) -#define TCU_TESR_TCST1 (1 << 1) -#define TCU_TESR_TCST0 (1 << 0) - -#define TCU_TECR_TCCL5 (1 << 5) -#define TCU_TECR_TCCL4 (1 << 4) -#define TCU_TECR_TCCL3 (1 << 3) -#define TCU_TECR_TCCL2 (1 << 2) -#define TCU_TECR_TCCL1 (1 << 1) -#define TCU_TECR_TCCL0 (1 << 0) - -#define TCU_TFR_HFLAG5 (1 << 21) -#define TCU_TFR_HFLAG4 (1 << 20) -#define TCU_TFR_HFLAG3 (1 << 19) -#define TCU_TFR_HFLAG2 (1 << 18) -#define TCU_TFR_HFLAG1 (1 << 17) -#define TCU_TFR_HFLAG0 (1 << 16) -#define TCU_TFR_FFLAG5 (1 << 5) -#define TCU_TFR_FFLAG4 (1 << 4) -#define TCU_TFR_FFLAG3 (1 << 3) -#define TCU_TFR_FFLAG2 (1 << 2) -#define TCU_TFR_FFLAG1 (1 << 1) -#define TCU_TFR_FFLAG0 (1 << 0) - -#define TCU_TFSR_HFLAG5 (1 << 21) -#define TCU_TFSR_HFLAG4 (1 << 20) -#define TCU_TFSR_HFLAG3 (1 << 19) -#define TCU_TFSR_HFLAG2 (1 << 18) -#define TCU_TFSR_HFLAG1 (1 << 17) -#define TCU_TFSR_HFLAG0 (1 << 16) -#define TCU_TFSR_FFLAG5 (1 << 5) -#define TCU_TFSR_FFLAG4 (1 << 4) -#define TCU_TFSR_FFLAG3 (1 << 3) -#define TCU_TFSR_FFLAG2 (1 << 2) -#define TCU_TFSR_FFLAG1 (1 << 1) -#define TCU_TFSR_FFLAG0 (1 << 0) - -#define TCU_TFCR_HFLAG5 (1 << 21) -#define TCU_TFCR_HFLAG4 (1 << 20) -#define TCU_TFCR_HFLAG3 (1 << 19) -#define TCU_TFCR_HFLAG2 (1 << 18) -#define TCU_TFCR_HFLAG1 (1 << 17) -#define TCU_TFCR_HFLAG0 (1 << 16) -#define TCU_TFCR_FFLAG5 (1 << 5) -#define TCU_TFCR_FFLAG4 (1 << 4) -#define TCU_TFCR_FFLAG3 (1 << 3) -#define TCU_TFCR_FFLAG2 (1 << 2) -#define TCU_TFCR_FFLAG1 (1 << 1) -#define TCU_TFCR_FFLAG0 (1 << 0) - -#define TCU_TMR_HMASK5 (1 << 21) -#define TCU_TMR_HMASK4 (1 << 20) -#define TCU_TMR_HMASK3 (1 << 19) -#define TCU_TMR_HMASK2 (1 << 18) -#define TCU_TMR_HMASK1 (1 << 17) -#define TCU_TMR_HMASK0 (1 << 16) -#define TCU_TMR_FMASK5 (1 << 5) -#define TCU_TMR_FMASK4 (1 << 4) -#define TCU_TMR_FMASK3 (1 << 3) -#define TCU_TMR_FMASK2 (1 << 2) -#define TCU_TMR_FMASK1 (1 << 1) -#define TCU_TMR_FMASK0 (1 << 0) - -#define TCU_TMSR_HMST5 (1 << 21) -#define TCU_TMSR_HMST4 (1 << 20) -#define TCU_TMSR_HMST3 (1 << 19) -#define TCU_TMSR_HMST2 (1 << 18) -#define TCU_TMSR_HMST1 (1 << 17) -#define TCU_TMSR_HMST0 (1 << 16) -#define TCU_TMSR_FMST5 (1 << 5) -#define TCU_TMSR_FMST4 (1 << 4) -#define TCU_TMSR_FMST3 (1 << 3) -#define TCU_TMSR_FMST2 (1 << 2) -#define TCU_TMSR_FMST1 (1 << 1) -#define TCU_TMSR_FMST0 (1 << 0) - -#define TCU_TMCR_HMCL5 (1 << 21) -#define TCU_TMCR_HMCL4 (1 << 20) -#define TCU_TMCR_HMCL3 (1 << 19) -#define TCU_TMCR_HMCL2 (1 << 18) -#define TCU_TMCR_HMCL1 (1 << 17) -#define TCU_TMCR_HMCL0 (1 << 16) -#define TCU_TMCR_FMCL5 (1 << 5) -#define TCU_TMCR_FMCL4 (1 << 4) -#define TCU_TMCR_FMCL3 (1 << 3) -#define TCU_TMCR_FMCL2 (1 << 2) -#define TCU_TMCR_FMCL1 (1 << 1) -#define TCU_TMCR_FMCL0 (1 << 0) - -#define TCU_TSR_WDTS (1 << 16) -#define TCU_TSR_STOP5 (1 << 5) -#define TCU_TSR_STOP4 (1 << 4) -#define TCU_TSR_STOP3 (1 << 3) -#define TCU_TSR_STOP2 (1 << 2) -#define TCU_TSR_STOP1 (1 << 1) -#define TCU_TSR_STOP0 (1 << 0) - -#define TCU_TSSR_WDTSS (1 << 16) -#define TCU_TSSR_STPS5 (1 << 5) -#define TCU_TSSR_STPS4 (1 << 4) -#define TCU_TSSR_STPS3 (1 << 3) -#define TCU_TSSR_STPS2 (1 << 2) -#define TCU_TSSR_STPS1 (1 << 1) -#define TCU_TSSR_STPS0 (1 << 0) - -#define TCU_TSSR_WDTSC (1 << 16) -#define TCU_TSSR_STPC5 (1 << 5) -#define TCU_TSSR_STPC4 (1 << 4) -#define TCU_TSSR_STPC3 (1 << 3) -#define TCU_TSSR_STPC2 (1 << 2) -#define TCU_TSSR_STPC1 (1 << 1) -#define TCU_TSSR_STPC0 (1 << 0) +#define TCU_TCSR_EXT_EN BIT(2) +#define TCU_TCSR_RTC_EN BIT(1) +#define TCU_TCSR_PCK_EN BIT(0) + +#define TCU_TER_TCEN5 BIT(5) +#define TCU_TER_TCEN4 BIT(4) +#define TCU_TER_TCEN3 BIT(3) +#define TCU_TER_TCEN2 BIT(2) +#define TCU_TER_TCEN1 BIT(1) +#define TCU_TER_TCEN0 BIT(0) + +#define TCU_TESR_TCST5 BIT(5) +#define TCU_TESR_TCST4 BIT(4) +#define TCU_TESR_TCST3 BIT(3) +#define TCU_TESR_TCST2 BIT(2) +#define TCU_TESR_TCST1 BIT(1) +#define TCU_TESR_TCST0 BIT(0) + +#define TCU_TECR_TCCL5 BIT(5) +#define TCU_TECR_TCCL4 BIT(4) +#define TCU_TECR_TCCL3 BIT(3) +#define TCU_TECR_TCCL2 BIT(2) +#define TCU_TECR_TCCL1 BIT(1) +#define TCU_TECR_TCCL0 BIT(0) + +#define TCU_TFR_HFLAG5 BIT(21) +#define TCU_TFR_HFLAG4 BIT(20) +#define TCU_TFR_HFLAG3 BIT(19) +#define TCU_TFR_HFLAG2 BIT(18) +#define TCU_TFR_HFLAG1 BIT(17) +#define TCU_TFR_HFLAG0 BIT(16) +#define TCU_TFR_FFLAG5 BIT(5) +#define TCU_TFR_FFLAG4 BIT(4) +#define TCU_TFR_FFLAG3 BIT(3) +#define TCU_TFR_FFLAG2 BIT(2) +#define TCU_TFR_FFLAG1 BIT(1) +#define TCU_TFR_FFLAG0 BIT(0) + +#define TCU_TFSR_HFLAG5 BIT(21) +#define TCU_TFSR_HFLAG4 BIT(20) +#define TCU_TFSR_HFLAG3 BIT(19) +#define TCU_TFSR_HFLAG2 BIT(18) +#define TCU_TFSR_HFLAG1 BIT(17) +#define TCU_TFSR_HFLAG0 BIT(16) +#define TCU_TFSR_FFLAG5 BIT(5) +#define TCU_TFSR_FFLAG4 BIT(4) +#define TCU_TFSR_FFLAG3 BIT(3) +#define TCU_TFSR_FFLAG2 BIT(2) +#define TCU_TFSR_FFLAG1 BIT(1) +#define TCU_TFSR_FFLAG0 BIT(0) + +#define TCU_TFCR_HFLAG5 BIT(21) +#define TCU_TFCR_HFLAG4 BIT(20) +#define TCU_TFCR_HFLAG3 BIT(19) +#define TCU_TFCR_HFLAG2 BIT(18) +#define TCU_TFCR_HFLAG1 BIT(17) +#define TCU_TFCR_HFLAG0 BIT(16) +#define TCU_TFCR_FFLAG5 BIT(5) +#define TCU_TFCR_FFLAG4 BIT(4) +#define TCU_TFCR_FFLAG3 BIT(3) +#define TCU_TFCR_FFLAG2 BIT(2) +#define TCU_TFCR_FFLAG1 BIT(1) +#define TCU_TFCR_FFLAG0 BIT(0) + +#define TCU_TMR_HMASK5 BIT(21) +#define TCU_TMR_HMASK4 BIT(20) +#define TCU_TMR_HMASK3 BIT(19) +#define TCU_TMR_HMASK2 BIT(18) +#define TCU_TMR_HMASK1 BIT(17) +#define TCU_TMR_HMASK0 BIT(16) +#define TCU_TMR_FMASK5 BIT(5) +#define TCU_TMR_FMASK4 BIT(4) +#define TCU_TMR_FMASK3 BIT(3) +#define TCU_TMR_FMASK2 BIT(2) +#define TCU_TMR_FMASK1 BIT(1) +#define TCU_TMR_FMASK0 BIT(0) + +#define TCU_TMSR_HMST5 BIT(21) +#define TCU_TMSR_HMST4 BIT(20) +#define TCU_TMSR_HMST3 BIT(19) +#define TCU_TMSR_HMST2 BIT(18) +#define TCU_TMSR_HMST1 BIT(17) +#define TCU_TMSR_HMST0 BIT(16) +#define TCU_TMSR_FMST5 BIT(5) +#define TCU_TMSR_FMST4 BIT(4) +#define TCU_TMSR_FMST3 BIT(3) +#define TCU_TMSR_FMST2 BIT(2) +#define TCU_TMSR_FMST1 BIT(1) +#define TCU_TMSR_FMST0 BIT(0) + +#define TCU_TMCR_HMCL5 BIT(21) +#define TCU_TMCR_HMCL4 BIT(20) +#define TCU_TMCR_HMCL3 BIT(19) +#define TCU_TMCR_HMCL2 BIT(18) +#define TCU_TMCR_HMCL1 BIT(17) +#define TCU_TMCR_HMCL0 BIT(16) +#define TCU_TMCR_FMCL5 BIT(5) +#define TCU_TMCR_FMCL4 BIT(4) +#define TCU_TMCR_FMCL3 BIT(3) +#define TCU_TMCR_FMCL2 BIT(2) +#define TCU_TMCR_FMCL1 BIT(1) +#define TCU_TMCR_FMCL0 BIT(0) + +#define TCU_TSR_WDTS BIT(16) +#define TCU_TSR_STOP5 BIT(5) +#define TCU_TSR_STOP4 BIT(4) +#define TCU_TSR_STOP3 BIT(3) +#define TCU_TSR_STOP2 BIT(2) +#define TCU_TSR_STOP1 BIT(1) +#define TCU_TSR_STOP0 BIT(0) + +#define TCU_TSSR_WDTSS BIT(16) +#define TCU_TSSR_STPS5 BIT(5) +#define TCU_TSSR_STPS4 BIT(4) +#define TCU_TSSR_STPS3 BIT(3) +#define TCU_TSSR_STPS2 BIT(2) +#define TCU_TSSR_STPS1 BIT(1) +#define TCU_TSSR_STPS0 BIT(0) + +#define TCU_TSSR_WDTSC BIT(16) +#define TCU_TSSR_STPC5 BIT(5) +#define TCU_TSSR_STPC4 BIT(4) +#define TCU_TSSR_STPC3 BIT(3) +#define TCU_TSSR_STPC2 BIT(2) +#define TCU_TSSR_STPC1 BIT(1) +#define TCU_TSSR_STPC0 BIT(0) /* Register definition */ #define WDT_TCSR_PRESCALE_BIT 3 @@ -569,29 +569,29 @@ #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) -#define WDT_TCER_TCEN (1 << 0) +#define WDT_TCSR_EXT_EN BIT(2) +#define WDT_TCSR_RTC_EN BIT(1) +#define WDT_TCSR_PCK_EN BIT(0) +#define WDT_TCER_TCEN BIT(0) /* * Define macros for UART_IER * UART Interrupt Enable Register */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ +#define UART_IER_RIE BIT(0) /* 0: receive fifo full interrupt disable */ +#define UART_IER_TIE BIT(1) /* 0: transmit fifo empty interrupt disable */ +#define UART_IER_RLIE BIT(2) /* 0: receive line status interrupt disable */ +#define UART_IER_MIE BIT(3) /* 0: modem status interrupt disable */ +#define UART_IER_RTIE BIT(4) /* 0: receive timeout interrupt disable */ /* * Define macros for UART_ISR * UART Interrupt Status Register */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ +#define UART_ISR_IP BIT(0) /* 0: interrupt is pending 1: no interrupt */ #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ +#define UART_ISR_IID_THRI BIT(1) /* Transmitter holding register empty */ #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ /* FIFO mode select, set when UART_FCR.FE is set to 1 */ @@ -603,14 +603,14 @@ * Define macros for UART_FCR * UART FIFO Control Register */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ +#define UART_FCR_FE BIT(0) /* 0: non-FIFO mode 1: FIFO mode */ +#define UART_FCR_RFLS BIT(1) /* write 1 to flush receive FIFO */ +#define UART_FCR_TFLS BIT(2) /* write 1 to flush transmit FIFO */ +#define UART_FCR_DMS BIT(3) /* 0: disable DMA mode */ +#define UART_FCR_UUE BIT(4) /* 0: disable UART */ #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ #define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) +#define UART_FCR_RTRG_4 BIT(6) #define UART_FCR_RTRG_8 (2 << 6) #define UART_FCR_RTRG_15 (3 << 6) @@ -620,109 +620,109 @@ */ #define UART_LCR_WLEN (3 << 0) /* word length */ #define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) +#define UART_LCR_WLEN_6 BIT(0) #define UART_LCR_WLEN_7 (2 << 0) #define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) +#define UART_LCR_STOP BIT(2) /* 0: 1 stop bit when word length is 5,6,7,8 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) +#define UART_LCR_STOP_2 BIT(2) /* 0: 1 stop bit when word length is 5,6,7,8 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ +#define UART_LCR_PE BIT(3) /* 0: parity disable */ +#define UART_LCR_PROE BIT(4) /* 0: even parity 1: odd parity */ +#define UART_LCR_SPAR BIT(5) /* 0: sticky parity disable */ +#define UART_LCR_SBRK BIT(6) /* write 0 normal, write 1 send break */ /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ -#define UART_LCR_DLAB (1 << 7) +#define UART_LCR_DLAB BIT(7) /* * Define macros for UART_LSR * UART Line Status Register */ /* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_DR (1 << 0) +#define UART_LSR_DR BIT(0) /* 0: no overrun error */ -#define UART_LSR_ORER (1 << 1) +#define UART_LSR_ORER BIT(1) /* 0: no parity error */ -#define UART_LSR_PER (1 << 2) +#define UART_LSR_PER BIT(2) /* 0; no framing error */ -#define UART_LSR_FER (1 << 3) +#define UART_LSR_FER BIT(3) /* 0: no break detected 1: receive a break signal */ -#define UART_LSR_BRK (1 << 4) +#define UART_LSR_BRK BIT(4) /* 1: transmit FIFO half "empty" */ -#define UART_LSR_TDRQ (1 << 5) +#define UART_LSR_TDRQ BIT(5) /* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_TEMT (1 << 6) +#define UART_LSR_TEMT BIT(6) /* 0: no receive error 1: receive error in FIFO mode */ -#define UART_LSR_RFER (1 << 7) +#define UART_LSR_RFER BIT(7) /* * Define macros for UART_MCR * UART Modem Control Register */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ +#define UART_MCR_DTR BIT(0) /* 0: DTR_ ouput high */ +#define UART_MCR_RTS BIT(1) /* 0: RTS_ output high */ /* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT1 (1 << 2) +#define UART_MCR_OUT1 BIT(2) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_OUT2 (1 << 3) -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ +#define UART_MCR_OUT2 BIT(3) +#define UART_MCR_LOOP BIT(4) /* 0: normal 1: loopback mode */ +#define UART_MCR_MCE BIT(7) /* 0: modem function is disable */ /* * Define macros for UART_MSR * UART Modem Status Register */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ +#define UART_MSR_DCTS BIT(0) /* 0: no change on CTS_ since last read */ +#define UART_MSR_DDSR BIT(1) /* 0: no change on DSR_ since last read */ +#define UART_MSR_DRI BIT(2) /* 0: no change on RI_ since last read */ +#define UART_MSR_DDCD BIT(3) /* 0: no change on DCD_ since last read */ +#define UART_MSR_CTS BIT(4) /* 0: CTS_ pin is high */ +#define UART_MSR_DSR BIT(5) /* 0: DSR_ pin is high */ +#define UART_MSR_RI BIT(6) /* 0: RI_ pin is high */ +#define UART_MSR_DCD BIT(7) /* 0: DCD_ pin is high */ /* * Define macros for SIRCR * Slow IrDA Control Register */ -#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length +#define SIRCR_TSIRE BIT(0) /* 0: TX is in UART mode 1: IrDA mode */ +#define SIRCR_RSIRE BIT(1) /* 0: RX is in UART mode 1: IrDA mode */ +#define SIRCR_TPWS BIT(2) /* 0: transmit 0 pulse width is 3/16 of bit length 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ +#define SIRCR_TXPL BIT(3) /* 0: encoder generates a positive pulse for 0 */ +#define SIRCR_RXPL BIT(4) /* 0: decoder interprets positive pulse as 0 */ /* MSC Clock and Control Register (MSC_STRPCL) */ -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) +#define MSC_STRPCL_EXIT_MULTIPLE BIT(7) +#define MSC_STRPCL_EXIT_TRANSFER BIT(6) +#define MSC_STRPCL_START_READWAIT BIT(5) +#define MSC_STRPCL_STOP_READWAIT BIT(4) +#define MSC_STRPCL_RESET BIT(3) +#define MSC_STRPCL_START_OP BIT(2) #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* MSC Status Register (MSC_STAT) */ -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) +#define MSC_STAT_IS_RESETTING BIT(15) +#define MSC_STAT_SDIO_INT_ACTIVE BIT(14) +#define MSC_STAT_PRG_DONE BIT(13) +#define MSC_STAT_DATA_TRAN_DONE BIT(12) +#define MSC_STAT_END_CMD_RES BIT(11) +#define MSC_STAT_DATA_FIFO_AFULL BIT(10) +#define MSC_STAT_IS_READWAIT BIT(9) +#define MSC_STAT_CLK_EN BIT(8) +#define MSC_STAT_DATA_FIFO_FULL BIT(7) +#define MSC_STAT_DATA_FIFO_EMPTY BIT(6) +#define MSC_STAT_CRC_RES_ERR BIT(5) +#define MSC_STAT_CRC_READ_ERROR BIT(4) #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ @@ -731,8 +731,8 @@ #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) +#define MSC_STAT_TIME_OUT_RES BIT(1) +#define MSC_STAT_TIME_OUT_READ BIT(0) /* MSC Bus Clock Control Register (MSC_CLKRT) */ #define MSC_CLKRT_CLK_RATE_BIT 0 @@ -747,18 +747,18 @@ #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* MSC Command Sequence Control Register (MSC_CMDAT) */ -#define MSC_CMDAT_IO_ABORT (1 << 11) +#define MSC_CMDAT_IO_ABORT BIT(11) #define MSC_CMDAT_BUS_WIDTH_BIT 9 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE (1 << 4) +#define MSC_CMDAT_DMA_EN BIT(8) +#define MSC_CMDAT_INIT BIT(7) +#define MSC_CMDAT_BUSY BIT(6) +#define MSC_CMDAT_STREAM_BLOCK BIT(5) +#define MSC_CMDAT_WRITE BIT(4) #define MSC_CMDAT_READ (0 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) +#define MSC_CMDAT_DATA_EN BIT(3) #define MSC_CMDAT_RESPONSE_BIT 0 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) @@ -770,12 +770,12 @@ #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* MSC Interrupts Mask Register (MSC_IMASK) */ -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) +#define MSC_IMASK_SDIO BIT(7) +#define MSC_IMASK_TXFIFO_WR_REQ BIT(6) +#define MSC_IMASK_RXFIFO_RD_REQ BIT(5) +#define MSC_IMASK_END_CMD_RES BIT(2) +#define MSC_IMASK_PRG_DONE BIT(1) +#define MSC_IMASK_DATA_TRAN_DONE BIT(0) #ifndef __ASSEMBLY__ /* INTC (Interrupt Controller) */ diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d9ffc15..540db26 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -59,14 +59,14 @@ #define PCI_CFG_PIIX4_SERIRQC 0x64 #define PCI_CFG_PIIX4_GENCFG 0xb0 -#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) -#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) +#define PCI_CFG_PIIX4_SERIRQC_EN BIT(7) +#define PCI_CFG_PIIX4_SERIRQC_CONT BIT(6) -#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) +#define PCI_CFG_PIIX4_GENCFG_SERIRQ BIT(16) #define PCI_CFG_PIIX4_IDETIM_PRI 0x40 #define PCI_CFG_PIIX4_IDETIM_SEC 0x42 -#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15) +#define PCI_CFG_PIIX4_IDETIM_IDE BIT(15) #endif /* _MIPS_ASM_MALTA_H */ diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.h b/arch/mips/mach-au1x00/au1x00_usb_ohci.h index bb9f351..abdc8df 100644 --- a/arch/mips/mach-au1x00/au1x00_usb_ohci.h +++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.h @@ -117,7 +117,7 @@ struct td { } __attribute__((aligned(32))); typedef struct td td_t; -#define OHCI_ED_SKIP (1 << 14) +#define OHCI_ED_SKIP BIT(14) /* * The HCCA (Host Controller Communications Area) is a 256 byte @@ -183,28 +183,28 @@ struct ohci_regs { * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_PLE BIT(2) /* periodic list enable */ +#define OHCI_CTRL_IE BIT(3) /* isochronous enable */ +#define OHCI_CTRL_CLE BIT(4) /* control list enable */ +#define OHCI_CTRL_BLE BIT(5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ +#define OHCI_CTRL_IR BIT(8) /* interrupt routing */ +#define OHCI_CTRL_RWC BIT(9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE BIT(10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_RESUME BIT(6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_HCR BIT(0) /* host controller reset */ +#define OHCI_CLF BIT(1) /* control list filled */ +#define OHCI_BLF BIT(2) /* bulk list filled */ +#define OHCI_OCR BIT(3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* @@ -213,15 +213,15 @@ struct ohci_regs { * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ +#define OHCI_INTR_SO BIT(0) /* scheduling overrun */ +#define OHCI_INTR_WDH BIT(1) /* writeback of done_head */ +#define OHCI_INTR_SF BIT(2) /* start frame */ +#define OHCI_INTR_RD BIT(3) /* resume detect */ +#define OHCI_INTR_UE BIT(4) /* unrecoverable error */ +#define OHCI_INTR_FNO BIT(5) /* frame number overflow */ +#define OHCI_INTR_RHSC BIT(6) /* root hub status change */ +#define OHCI_INTR_OC BIT(30) /* ownership change */ +#define OHCI_INTR_MIE BIT(31) /* master interrupt enable */ /* Virtual Root HUB */ @@ -317,11 +317,11 @@ struct virt_root_hub { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 9d7e193..860aa88 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -30,14 +30,14 @@ typedef volatile struct { } nios_timer_t; /* status register */ -#define NIOS_TIMER_TO (1 << 0) /* Timeout */ -#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ +#define NIOS_TIMER_TO BIT(0) /* Timeout */ +#define NIOS_TIMER_RUN BIT(1) /* Timer running */ /* control register */ -#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ -#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ -#define NIOS_TIMER_START (1 << 2) /* Start timer */ -#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ +#define NIOS_TIMER_ITO BIT(0) /* Timeout int ena */ +#define NIOS_TIMER_CONT BIT(1) /* Continuous mode */ +#define NIOS_TIMER_START BIT(2) /* Start timer */ +#define NIOS_TIMER_STOP BIT(3) /* Stop timer */ #if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) #error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) diff --git a/arch/powerpc/cpu/mpc5xxx/cpu_init.c b/arch/powerpc/cpu/mpc5xxx/cpu_init.c index f9b57ba..ed8f3d0 100644 --- a/arch/powerpc/cpu/mpc5xxx/cpu_init.c +++ b/arch/powerpc/cpu/mpc5xxx/cpu_init.c @@ -36,7 +36,7 @@ void cpu_init_f (void) volatile struct mpc5xxx_gpt *gpt0 = (struct mpc5xxx_gpt *) MPC5XXX_GPT; #endif /* CONFIG_WATCHDOG */ - unsigned long addecr = (1 << 25); /* Boot_CS */ + unsigned long addecr = BIT(25); /* Boot_CS */ /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -60,7 +60,7 @@ void cpu_init_f (void) out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE)); /* CS0 and BOOT_CS cannot be enabled at once. */ - /* addecr |= (1 << 16); */ + /* addecr |= BIT(16); */ #endif #if defined(CONFIG_SYS_CS0_CFG) out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG); @@ -70,7 +70,7 @@ void cpu_init_f (void) out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START)); out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE)); - addecr |= (1 << 17); + addecr |= BIT(17); #endif #if defined(CONFIG_SYS_CS1_CFG) out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG); @@ -80,7 +80,7 @@ void cpu_init_f (void) out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START)); out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE)); - addecr |= (1 << 18); + addecr |= BIT(18); #endif #if defined(CONFIG_SYS_CS2_CFG) out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG); @@ -90,7 +90,7 @@ void cpu_init_f (void) out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START)); out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE)); - addecr |= (1 << 19); + addecr |= BIT(19); #endif #if defined(CONFIG_SYS_CS3_CFG) out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG); @@ -100,7 +100,7 @@ void cpu_init_f (void) out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START)); out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE)); - addecr |= (1 << 20); + addecr |= BIT(20); #endif #if defined(CONFIG_SYS_CS4_CFG) out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG); @@ -110,7 +110,7 @@ void cpu_init_f (void) out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START)); out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE)); - addecr |= (1 << 21); + addecr |= BIT(21); #endif #if defined(CONFIG_SYS_CS5_CFG) out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); @@ -121,7 +121,7 @@ void cpu_init_f (void) out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE)); - addecr |= (1 << 26); + addecr |= BIT(26); #endif #if defined(CONFIG_SYS_CS6_CFG) out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG); @@ -131,7 +131,7 @@ void cpu_init_f (void) out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START)); out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE)); - addecr |= (1 << 27); + addecr |= BIT(27); #endif #if defined(CONFIG_SYS_CS7_CFG) out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG); @@ -146,7 +146,7 @@ void cpu_init_f (void) /* Enable chip selects */ out_be32(&mm->ipbi_ws_ctrl, addecr); - out_be32(&lpb->cs_ctrl, (1 << 24)); + out_be32(&lpb->cs_ctrl, BIT(24)); /* Setup pin multiplexing */ #if defined(CONFIG_SYS_GPS_PORT_CONFIG) @@ -168,10 +168,10 @@ void cpu_init_f (void) #endif /* enable timebase */ - setbits_be32(&xlb->config, (1 << 13)); + setbits_be32(&xlb->config, BIT(13)); /* Enable snooping for RAM */ - setbits_be32(&xlb->config, (1 << 15)); + setbits_be32(&xlb->config, BIT(15)); out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) @@ -195,7 +195,7 @@ void cpu_init_f (void) #if defined(CONFIG_SYS_XLB_PIPELINING) /* Enable piplining */ - clrbits_be32(&xlb->config, (1 << 31)); + clrbits_be32(&xlb->config, BIT(31)); #endif #if defined(CONFIG_WATCHDOG) diff --git a/arch/powerpc/cpu/mpc5xxx/interrupts.c b/arch/powerpc/cpu/mpc5xxx/interrupts.c index 9121fa0..d0df7e5 100644 --- a/arch/powerpc/cpu/mpc5xxx/interrupts.c +++ b/arch/powerpc/cpu/mpc5xxx/interrupts.c @@ -43,7 +43,7 @@ static void mpc5xxx_ic_disable(unsigned int irq) if (irq == MPC5XXX_IRQ0) { val = in_be32(&intr->ctrl); - val &= ~(1 << 11); + val &= ~BIT(11); out_be32(&intr->ctrl, val); } else if (irq < MPC5XXX_IRQ1) { BUG(); diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c index 70b7e6e..9a152f5 100644 --- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c +++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c @@ -21,16 +21,16 @@ /* PCIIWCR bit fields */ #define IWCR_MEM (0 << 3) -#define IWCR_IO (1 << 3) +#define IWCR_IO BIT(3) #define IWCR_READ (0 << 1) -#define IWCR_READLINE (1 << 1) +#define IWCR_READLINE BIT(1) #define IWCR_READMULT (2 << 1) -#define IWCR_EN (1 << 0) +#define IWCR_EN BIT(0) static int mpc5200_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32* value) { - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + *(volatile u32 *)MPC5XXX_PCI_CAR = BIT(31) | dev | offset; eieio(); udelay(10); *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); @@ -43,7 +43,7 @@ static int mpc5200_read_config_dword(struct pci_controller *hose, static int mpc5200_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 value) { - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + *(volatile u32 *)MPC5XXX_PCI_CAR = BIT(31) | dev | offset; eieio(); udelay(10); out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); @@ -84,7 +84,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose) pci_register_hose(hose); /* GPIO Multiplexing - enable PCI */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~BIT(15); /* Set host bridge as pci master and enable memory decoding */ *(vu_long *)MPC5XXX_PCI_CMD |= @@ -102,7 +102,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose) *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; /* Map RAM to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); + *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | BIT(3); *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; /* Park XLB on PCI */ diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c index 30a0a35..35e42d3 100644 --- a/arch/powerpc/cpu/mpc5xxx/speed.c +++ b/arch/powerpc/cpu/mpc5xxx/speed.c @@ -36,12 +36,12 @@ int get_clocks (void) #endif val = *(vu_long *)MPC5XXX_CDM_PORCFG; - if (val & (1 << 6)) { + if (val & BIT(6)) { vco = CONFIG_SYS_MPC5XXX_CLKIN * 12; } else { vco = CONFIG_SYS_MPC5XXX_CLKIN * 16; } - if (val & (1 << 5)) { + if (val & BIT(5)) { gd->bus_clk = vco / 8; } else { gd->bus_clk = vco / 4; @@ -49,7 +49,7 @@ int get_clocks (void) gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2; val = *(vu_long *)MPC5XXX_CDM_CFG; - if (val & (1 << 8)) { + if (val & BIT(8)) { gd->arch.ipb_clk = gd->bus_clk / 2; } else { gd->arch.ipb_clk = gd->bus_clk; diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h index 629b529..97d34b1 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h @@ -116,7 +116,7 @@ struct td { } __attribute__((aligned(32))); typedef struct td td_t; -#define OHCI_ED_SKIP (1 << 14) +#define OHCI_ED_SKIP BIT(14) /* * The HCCA (Host Controller Communications Area) is a 256 byte @@ -182,28 +182,28 @@ struct ohci_regs { * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_PLE BIT(2) /* periodic list enable */ +#define OHCI_CTRL_IE BIT(3) /* isochronous enable */ +#define OHCI_CTRL_CLE BIT(4) /* control list enable */ +#define OHCI_CTRL_BLE BIT(5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ +#define OHCI_CTRL_IR BIT(8) /* interrupt routing */ +#define OHCI_CTRL_RWC BIT(9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE BIT(10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_RESUME BIT(6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_HCR BIT(0) /* host controller reset */ +#define OHCI_CLF BIT(1) /* control list filled */ +#define OHCI_BLF BIT(2) /* bulk list filled */ +#define OHCI_OCR BIT(3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* @@ -212,15 +212,15 @@ struct ohci_regs { * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ +#define OHCI_INTR_SO BIT(0) /* scheduling overrun */ +#define OHCI_INTR_WDH BIT(1) /* writeback of done_head */ +#define OHCI_INTR_SF BIT(2) /* start frame */ +#define OHCI_INTR_RD BIT(3) /* resume detect */ +#define OHCI_INTR_UE BIT(4) /* unrecoverable error */ +#define OHCI_INTR_FNO BIT(5) /* frame number overflow */ +#define OHCI_INTR_RHSC BIT(6) /* root hub status change */ +#define OHCI_INTR_OC BIT(30) /* ownership change */ +#define OHCI_INTR_MIE BIT(31) /* master interrupt enable */ /* Virtual Root HUB */ @@ -316,11 +316,11 @@ struct virt_root_hub { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index f62e1b7..c47ec52 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -753,7 +753,7 @@ long int spd_sdram() ddr->sdram_cfg2 = (0 | (0 << 26) /* True DQS */ | (odt_cfg << 21) /* ODT only read */ - | (1 << 12) /* 1 refresh at a time */ + | BIT(12) /* 1 refresh at a time */ ); debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853..849b04f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -443,7 +443,7 @@ ulong cpu_init_f(void) * Fixed in silicon rev 2.1. */ if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) - out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); + out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | BIT(16)); #endif disable_tlb(14); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 7202c3f..90819f2 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -231,20 +231,20 @@ void board_add_ram_info(int use_default) #define CMD_NOP (7 << 19) #define CMD_PRECHARGE (2 << 19) -#define CMD_REFRESH (1 << 19) +#define CMD_REFRESH BIT(19) #define CMD_EMR (0 << 19) #define CMD_READ (5 << 19) #define CMD_WRITE (4 << 19) #define SELECT_MR (0 << 16) -#define SELECT_EMR (1 << 16) +#define SELECT_EMR BIT(16) #define SELECT_EMR2 (2 << 16) #define SELECT_EMR3 (3 << 16) /* MR */ #define DLL_RESET 0x00000100 -#define WRITE_RECOV_2 (1 << 9) +#define WRITE_RECOV_2 BIT(9) #define WRITE_RECOV_3 (2 << 9) #define WRITE_RECOV_4 (3 << 9) #define WRITE_RECOV_5 (4 << 9) diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index f0f3462..30291ce 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -495,7 +495,7 @@ int ppc4xx_init_pcie(void) return -1; } /* De-assert reset of PCIe PLL, wait for lock */ - SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~BIT(24)); udelay(300); /* 300 uS is maximum time lock should take */ while (time_out) { @@ -969,7 +969,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) mdelay(100); val = SDR_READ(SDRN_PESDR_RCSSTS(port)); - if (val & (1 << 20)) { + if (val & BIT(20)) { printf("PCIE%d: PGRST failed %08x\n", port, val); return -1; } @@ -1021,7 +1021,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) * Check for VC0 active and assert RDY. */ attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & BIT(16))) { if (!(attempts--)) { printf("PCIE%d: VC0 not active\n", port); return -1; @@ -1265,7 +1265,7 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) out_le32(mbase + 0x208, 0x0b200001); attempts = 10; - while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & BIT(8))) { if (!(attempts--)) { printf("PCIE%d: BME not active\n", port); return -1; diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.h b/arch/powerpc/cpu/ppc4xx/usb_ohci.h index 2c3dc4f..8f3fba9 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.h +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.h @@ -114,7 +114,7 @@ struct td { } __attribute__((aligned(32))); typedef struct td td_t; -#define OHCI_ED_SKIP (1 << 14) +#define OHCI_ED_SKIP BIT(14) /* * The HCCA (Host Controller Communications Area) is a 256 byte @@ -183,28 +183,28 @@ struct ohci_regs { * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_PLE BIT(2) /* periodic list enable */ +#define OHCI_CTRL_IE BIT(3) /* isochronous enable */ +#define OHCI_CTRL_CLE BIT(4) /* control list enable */ +#define OHCI_CTRL_BLE BIT(5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ +#define OHCI_CTRL_IR BIT(8) /* interrupt routing */ +#define OHCI_CTRL_RWC BIT(9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE BIT(10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_RESUME BIT(6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_HCR BIT(0) /* host controller reset */ +#define OHCI_CLF BIT(1) /* control list filled */ +#define OHCI_BLF BIT(2) /* bulk list filled */ +#define OHCI_OCR BIT(3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* @@ -213,15 +213,15 @@ struct ohci_regs { * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ +#define OHCI_INTR_SO BIT(0) /* scheduling overrun */ +#define OHCI_INTR_WDH BIT(1) /* writeback of done_head */ +#define OHCI_INTR_SF BIT(2) /* start frame */ +#define OHCI_INTR_RD BIT(3) /* resume detect */ +#define OHCI_INTR_UE BIT(4) /* unrecoverable error */ +#define OHCI_INTR_FNO BIT(5) /* frame number overflow */ +#define OHCI_INTR_RHSC BIT(6) /* root hub status change */ +#define OHCI_INTR_OC BIT(30) /* ownership change */ +#define OHCI_INTR_MIE BIT(31) /* master interrupt enable */ /* Virtual Root HUB */ struct virt_root_hub { @@ -314,11 +314,11 @@ struct virt_root_hub { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ diff --git a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h index 5a06a09..419e1aa 100644 --- a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h +++ b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h @@ -10,7 +10,7 @@ #include #define FSL_SERDES_CLK_100 (0 << 28) -#define FSL_SERDES_CLK_125 (1 << 28) +#define FSL_SERDES_CLK_125 BIT(28) #define FSL_SERDES_CLK_150 (3 << 28) #define FSL_SERDES_PROTO_SATA 0 #define FSL_SERDES_PROTO_PEX 1 diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h index 92fb777..db02ac2 100644 --- a/arch/powerpc/include/asm/fsl_tgec.h +++ b/arch/powerpc/include/asm/fsl_tgec.h @@ -182,17 +182,17 @@ struct tgec_mdio_controller { }; #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) -#define MDIO_STAT_BSY (1 << 0) -#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_STAT_BSY BIT(0) +#define MDIO_STAT_RD_ER BIT(1) #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) -#define MDIO_CTL_PRE_DIS (1 << 10) -#define MDIO_CTL_SCAN_EN (1 << 11) -#define MDIO_CTL_POST_INC (1 << 14) -#define MDIO_CTL_READ (1 << 15) +#define MDIO_CTL_PRE_DIS BIT(10) +#define MDIO_CTL_SCAN_EN BIT(11) +#define MDIO_CTL_POST_INC BIT(14) +#define MDIO_CTL_READ BIT(15) #define MDIO_DATA(x) (x & 0xffff) -#define MDIO_DATA_BSY (1 << 31) +#define MDIO_DATA_BSY BIT(31) struct fsl_enet_mac; diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index bed80aa..7cfb1c4 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -870,12 +870,12 @@ void iopin_initialize(iopin_t *,int); * support to adjust individual parts of the IO pin setup */ -#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ -#define IO_PIN_OVER_FMUX (1 << 1) -#define IO_PIN_OVER_HOLD (1 << 2) -#define IO_PIN_OVER_PULL (1 << 3) -#define IO_PIN_OVER_STRIG (1 << 4) -#define IO_PIN_OVER_DRVSTR (1 << 5) +#define IO_PIN_OVER_EACH BIT(0) /* for compatibility */ +#define IO_PIN_OVER_FMUX BIT(1) +#define IO_PIN_OVER_HOLD BIT(2) +#define IO_PIN_OVER_PULL BIT(3) +#define IO_PIN_OVER_STRIG BIT(4) +#define IO_PIN_OVER_DRVSTR BIT(5) void iopin_initialize_bits(iopin_t *, int); diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index e6fed83..4e41dff 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -668,7 +668,7 @@ * JEDEC Precharge Command Memory Address Arguments */ #define JEDEC_MA_PRECHARGE_ONE (0 << 10) -#define JEDEC_MA_PRECHARGE_ALL (1 << 10) +#define JEDEC_MA_PRECHARGE_ALL BIT(10) /* * JEDEC DDR EMR Command Bank Address Arguments @@ -682,7 +682,7 @@ * JEDEC DDR Mode Register */ #define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) -#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) +#define JEDEC_MA_MR_PDMODE_SLOW_EXIT BIT(12) #define JEDEC_MA_MR_WR_MASK (0x7 << 9) #define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) #define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) @@ -690,9 +690,9 @@ #define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) #define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) #define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) -#define JEDEC_MA_MR_DLL_RESET (1 << 8) +#define JEDEC_MA_MR_DLL_RESET BIT(8) #define JEDEC_MA_MR_MODE_NORMAL (0 << 8) -#define JEDEC_MA_MR_MODE_TEST (1 << 8) +#define JEDEC_MA_MR_MODE_TEST BIT(8) #define JEDEC_MA_MR_CL_MASK (0x7 << 4) #define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) #define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) @@ -704,7 +704,7 @@ #define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) #define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) #define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) -#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) +#define JEDEC_MA_MR_BTYP_INTERLEAVED BIT(3) #define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) #define JEDEC_MA_MR_BLEN_4 (2 << 0) #define JEDEC_MA_MR_BLEN_8 (3 << 0) @@ -712,20 +712,20 @@ /* * JEDEC DDR Extended Mode Register */ -#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) +#define JEDEC_MA_EMR_OUTPUT_MASK BIT(12) #define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) -#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) -#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) +#define JEDEC_MA_EMR_OUTPUT_DISABLE BIT(12) +#define JEDEC_MA_EMR_RQDS_MASK BIT(11) #define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) -#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) -#define JEDEC_MA_EMR_DQS_MASK (1 << 10) -#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) +#define JEDEC_MA_EMR_RDQS_ENABLE BIT(11) +#define JEDEC_MA_EMR_DQS_MASK BIT(10) +#define JEDEC_MA_EMR_DQS_DISABLE BIT(10) #define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) #define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) #define JEDEC_MA_EMR_OCD_EXIT (0 << 7) #define JEDEC_MA_EMR_OCD_ENTER (7 << 7) #define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) -#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) +#define JEDEC_MA_EMR_AL_DDR2_1_CYC BIT(3) #define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) #define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) #define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) @@ -734,18 +734,18 @@ #define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) #define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) #define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) -#define JEDEC_MA_EMR_ODS_MASK (1 << 1) +#define JEDEC_MA_EMR_ODS_MASK BIT(1) #define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) -#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) -#define JEDEC_MA_EMR_DLL_MASK (1 << 0) +#define JEDEC_MA_EMR_ODS_WEAK BIT(1) +#define JEDEC_MA_EMR_DLL_MASK BIT(0) #define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) -#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) +#define JEDEC_MA_EMR_DLL_DISABLE BIT(0) /* * JEDEC DDR Extended Mode Register 2 */ #define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) -#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) +#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL BIT(7) /* * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c index fc938e6..857bad7 100644 --- a/arch/sh/cpu/sh4/watchdog.c +++ b/arch/sh/cpu/sh4/watchdog.c @@ -9,10 +9,10 @@ #define WDT_BASE WTCNT -#define WDT_WD (1 << 6) +#define WDT_WD BIT(6) #define WDT_RST_P (0) -#define WDT_RST_M (1 << 5) -#define WDT_ENABLE (1 << 7) +#define WDT_RST_M BIT(5) +#define WDT_ENABLE BIT(7) #if defined(CONFIG_WATCHDOG) static unsigned char csr_read(void) diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index ca7d6e8..9562926 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -828,7 +828,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | ((status & USBPORTSC_PEC) >> (3 - 1)) | (rh.c_p_r[wIndex - 1] << (0 + 4)); - status = (status & USBPORTSC_CCS) | ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | (1 << 8) | /* power on ** */ + status = (status & USBPORTSC_CCS) | ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | BIT(8) | /* power on ** */ ((status & USBPORTSC_LSDA) << (-8 + 9)); *(unsigned short *)data = swap_16(status); diff --git a/arch/sparc/cpu/leon3/usb_uhci.h b/arch/sparc/cpu/leon3/usb_uhci.h index 034814a..b17304d 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.h +++ b/arch/sparc/cpu/leon3/usb_uhci.h @@ -66,18 +66,18 @@ #define UHCI_PTR_DEPTH 0x0004 /* for TD : */ -#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ +#define TD_CTRL_SPD BIT(29) /* Short Packet Detect */ #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ -#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ -#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ -#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ -#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ -#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ -#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ -#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ -#define TD_CTRL_NAK (1 << 19) /* NAK Received */ -#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ -#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ +#define TD_CTRL_LS BIT(26) /* Low Speed Device */ +#define TD_CTRL_IOS BIT(25) /* Isochronous Select */ +#define TD_CTRL_IOC BIT(24) /* Interrupt on Complete */ +#define TD_CTRL_ACTIVE BIT(23) /* TD Active */ +#define TD_CTRL_STALLED BIT(22) /* TD Stalled */ +#define TD_CTRL_DBUFERR BIT(21) /* Data Buffer Error */ +#define TD_CTRL_BABBLE BIT(20) /* Babble Detected */ +#define TD_CTRL_NAK BIT(19) /* NAK Received */ +#define TD_CTRL_CRCTIMEO BIT(18) /* CRC/Time Out Error */ +#define TD_CTRL_BITSTUFF BIT(17) /* Bit Stuff Error */ #define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index a9ca50b..cfeb7dd 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -225,7 +225,7 @@ static bool has_cpuid(void) static bool has_mtrr(void) { - return cpuid_edx(0x00000001) & (1 << 12) ? true : false; + return cpuid_edx(0x00000001) & BIT(12) ? true : false; } static int build_vendor_name(char *vendor_name) @@ -475,7 +475,7 @@ static bool can_detect_long_mode(void) static bool has_long_mode(void) { - return cpuid_edx(0x80000001) & (1 << 29) ? true : false; + return cpuid_edx(0x80000001) & BIT(29) ? true : false; } int cpu_has_64bit(void) diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index ca8cccf..adc62b0 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -32,8 +32,8 @@ void bd82x6x_pci_init(pci_dev_t dev) /* disable parity error response and SERR */ reg16 = x86_pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); + reg16 &= ~BIT(0); + reg16 &= ~BIT(1); x86_pci_write_config16(dev, BCTRL, reg16); /* Master Latency Count must be set to 0x04! */ diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 9ca008e..fde643a 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -95,7 +95,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) /* Erratum workarounds */ reg32 = readl(MCHBAR_REG(0x5f00)); - reg32 |= (1 << 9) | (1 << 10); + reg32 |= BIT(9) | BIT(10); writel(reg32, MCHBAR_REG(0x5f00)); /* Enable SA Clock Gating */ @@ -104,16 +104,16 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) /* GPU RC6 workaround for sighting 366252 */ reg32 = readl(MCHBAR_REG(0x5d14)); - reg32 |= (1 << 31); + reg32 |= BIT(31); writel(reg32, MCHBAR_REG(0x5d14)); /* VLW */ reg32 = readl(MCHBAR_REG(0x6120)); - reg32 &= ~(1 << 0); + reg32 &= ~BIT(0); writel(reg32, MCHBAR_REG(0x6120)); reg32 = readl(MCHBAR_REG(0x5418)); - reg32 |= (1 << 4) | (1 << 5); + reg32 |= BIT(4) | BIT(5); writel(reg32, MCHBAR_REG(0x5418)); } @@ -127,7 +127,7 @@ void sandybridge_early_init(int chipset_type) /* Device ID Override Enable should be done very early */ capid0_a = x86_pci_read_config32(pch_dev, 0xe4); - if (capid0_a & (1 << 10)) { + if (capid0_a & BIT(10)) { reg8 = x86_pci_read_config8(pch_dev, 0xf3); reg8 &= ~7; /* Clear 2:0 */ diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index ea169b0..8b81a50 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -363,31 +363,31 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) if (bridge_silicon_revision() < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(gtt_bar, 0xa18c, 0x00000001); - gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); + gtt_poll(gtt_bar, 0x130090, BIT(0), BIT(0)); } else { gtt_write(gtt_bar, 0xa180, 1 << 5); gtt_write(gtt_bar, 0xa188, 0xffff0001); - gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); + gtt_poll(gtt_bar, 0x130040, BIT(0), BIT(0)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(gtt_bar, 0x42004); - reg32 |= (1 << 14) | (1 << 15); + reg32 |= BIT(14) | BIT(15); gtt_write(gtt_bar, 0x42004, reg32); } if (bridge_silicon_revision() >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(gtt_bar, 0x45010); - reg32 |= (1 << 1) | (1 << 0); + reg32 |= BIT(1) | BIT(0); gtt_write(gtt_bar, 0x45010, reg32); } /* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(gtt_bar, 0x911c); if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - if (reg32 & (1 << 13)) { + if (reg32 & BIT(13)) { debug("SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(gtt_bar, snb_pm_gt1); } else { @@ -397,7 +397,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) } else { u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; - if (reg32 & (1 << 13)) { + if (reg32 & BIT(13)) { /* GT1 SKU */ debug("IVB GT1 Power Meter Weights\n"); gtt_write_powermeter(gtt_bar, ivb_pm_gt1); @@ -433,29 +433,29 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) /* 6: ECO bits */ reg32 = gtt_read(gtt_bar, 0xa180); - reg32 |= (1 << 26) | (1 << 31); + reg32 |= BIT(26) | BIT(31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) - reg32 |= (1 << 20); + reg32 |= BIT(20); gtt_write(gtt_bar, 0xa180, reg32); /* 6a: for SnB step D2+ only */ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && (bridge_silicon_revision() >= SNB_STEP_D2)) { reg32 = gtt_read(gtt_bar, 0x9400); - reg32 |= (1 << 7); + reg32 |= BIT(7); gtt_write(gtt_bar, 0x9400, reg32); reg32 = gtt_read(gtt_bar, 0x941c); reg32 &= 0xf; - reg32 |= (1 << 1); + reg32 |= BIT(1); gtt_write(gtt_bar, 0x941c, reg32); - gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); + gtt_poll(gtt_bar, 0x941c, BIT(1), (0 << 1)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { reg32 = gtt_read(gtt_bar, 0x907c); - reg32 |= (1 << 16); + reg32 |= BIT(16); gtt_write(gtt_bar, 0x907c, reg32); /* 6b: Clocking reset controls */ @@ -466,13 +466,13 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) } /* 7 */ - if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { + if (gtt_poll(gtt_bar, 0x138124, BIT(31), (0 << 31))) { gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ /* Mailbox Cmd for RC6 VID */ gtt_write(gtt_bar, 0x138124, 0x80000004); - if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) + if (gtt_poll(gtt_bar, 0x138124, BIT(31), (0 << 31))) gtt_write(gtt_bar, 0x138124, 0x8000000a); - gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); + gtt_poll(gtt_bar, 0x138124, BIT(31), (0 << 31)); } /* 8 */ @@ -548,10 +548,10 @@ int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) /* 15: Deassert Force Wake */ if (bridge_silicon_revision() < IVB_STEP_C0) { gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); - gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); + gtt_poll(gtt_bar, 0x130090, BIT(0), (0 << 0)); } else { gtt_write(gtt_bar, 0xa188, 0x1fffe); - if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { + if (gtt_poll(gtt_bar, 0x130040, BIT(0), (0 << 0))) { gtt_write(gtt_bar, 0xa188, gtt_read(gtt_bar, 0xa188) | 1); } @@ -610,12 +610,12 @@ int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) /* Enable Backlight if needed */ reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); if (reg32) { - gtt_write(gtt_bar, 0x48250, (1 << 31)); + gtt_write(gtt_bar, 0x48250, BIT(31)); gtt_write(gtt_bar, 0x48254, reg32); } reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); if (reg32) { - gtt_write(gtt_bar, 0xc8250, (1 << 31)); + gtt_write(gtt_bar, 0xc8250, BIT(31)); gtt_write(gtt_bar, 0xc8254, reg32); } diff --git a/arch/x86/cpu/ivybridge/gma.h b/arch/x86/cpu/ivybridge/gma.h index e7ec649..c9e0c6c 100644 --- a/arch/x86/cpu/ivybridge/gma.h +++ b/arch/x86/cpu/ivybridge/gma.h @@ -21,11 +21,11 @@ __packed struct opregion_header { #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" #define IGD_OPREGION_VERSION 2 -#define IGD_MBOX1 (1 << 0) -#define IGD_MBOX2 (1 << 1) -#define IGD_MBOX3 (1 << 2) -#define IGD_MBOX4 (1 << 3) -#define IGD_MBOX5 (1 << 4) +#define IGD_MBOX1 BIT(0) +#define IGD_MBOX2 BIT(1) +#define IGD_MBOX3 BIT(2) +#define IGD_MBOX4 BIT(3) +#define IGD_MBOX5 BIT(4) #define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ IGD_MBOX4 | IGD_MBOX5) @@ -85,8 +85,8 @@ __packed struct opregion_mailbox3 { #define IGD_BACKLIGHT_BRIGHTNESS 0xff #define IGD_INITIAL_BRIGHTNESS 0x64 -#define IGD_FIELD_VALID (1 << 31) -#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_FIELD_VALID BIT(31) +#define IGD_WORD_FIELD_VALID BIT(15) #define IGD_PFIT_STRETCH 6 /* mailbox 4: vbt */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index bc1a0f0..2fe5518 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -44,7 +44,7 @@ static int pch_enable_apic(pci_dev_t dev) writel(0, IO_APIC_INDEX); reg32 = readl(IO_APIC_DATA); debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) { + if (reg32 != BIT(25)) { printf("APIC Error - cannot write to registers\n"); return -EPERM; } @@ -71,11 +71,11 @@ static void pch_enable_serial_irqs(pci_dev_t dev) u32 value; /* Set packet length and toggle silent mode bit for one frame. */ - value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); + value = BIT(7) | BIT(6) | ((21 - 17) << 2) | (0 << 0); #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE x86_pci_write_config8(dev, SERIRQ_CNTL, value); #else - x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); + x86_pci_write_config8(dev, SERIRQ_CNTL, value | BIT(6)); #endif } @@ -162,12 +162,12 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) } reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + reg16 |= BIT(3); /* SLP_S4# Assertion Stretch Enable */ - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + reg16 &= ~BIT(10); + reg16 |= BIT(11); /* SLP_S3# Min Assertion Width 50ms */ - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + reg16 |= BIT(12); /* Disable SLP stretch after SUS well */ x86_pci_write_config16(dev, GEN_PMCON_3, reg16); debug("Set power %s after power failure.\n", state); @@ -175,8 +175,8 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) /* Set up NMI on errors. */ reg8 = inb(0x61); reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + reg8 &= ~BIT(3); /* IOCHK# NMI Enable */ + reg8 |= BIT(2); /* PCI SERR# Disable for now */ outb(reg8, 0x61); reg8 = inb(0x70); @@ -184,18 +184,18 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) nmi_option = NMI_OFF; if (nmi_option) { debug("NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ + reg8 &= ~BIT(7); /* Set NMI. */ } else { debug("NMI sources disabled.\n"); /* Can't mask NMI from PCI-E and NMI_NOW */ - reg8 |= (1 << 7); + reg8 |= BIT(7); } outb(reg8, 0x70); /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ - reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ + reg16 &= ~BIT(10); /* Disable BIOS_PCI_EXP_EN for native PME */ #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ reg16 |= (3 << 0); /* Periodic SMI every 8s */ @@ -217,11 +217,11 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); /* PM1_CNT */ reg32 &= ~(7 << 10); /* SLP_TYP */ - reg32 |= (1 << 0); /* SCI_EN */ + reg32 |= BIT(0); /* SCI_EN */ outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ - setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); + setbits_le32(RCB_REG(0x3310), BIT(4) | BIT(5) | BIT(0)); clrbits_le32(RCB_REG(0x3f02), 0xf); return 0; @@ -260,14 +260,14 @@ static void cpt_pm_init(pci_dev_t dev) { debug("CougarPoint PM init\n"); x86_pci_write_config8(dev, 0xa9, 0x47); - setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); + setbits_le32(RCB_REG(0x2238), BIT(6) | BIT(0)); setbits_le32(RCB_REG(0x228c), 1 << 0); - setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le32(RCB_REG(0x1100), BIT(13) | BIT(14)); setbits_le32(RCB_REG(0x0900), 1 << 14); writel(0xc0388400, RCB_REG(0x2304)); - setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); - setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + setbits_le32(RCB_REG(0x2314), BIT(5) | BIT(18)); + setbits_le32(RCB_REG(0x2320), BIT(15) | BIT(1)); clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); writel(0x050f0000, RCB_REG(0x3318)); writel(0x04000000, RCB_REG(0x3324)); @@ -306,16 +306,16 @@ static void ppt_pm_init(pci_dev_t dev) x86_pci_write_config8(dev, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), 1 << 0); setbits_le32(RCB_REG(0x228c), 1 << 0); - setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); + setbits_le16(RCB_REG(0x1100), BIT(13) | BIT(14)); setbits_le16(RCB_REG(0x0900), 1 << 14); writel(0xc03b8400, RCB_REG(0x2304)); - setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); - setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); + setbits_le32(RCB_REG(0x2314), BIT(5) | BIT(18)); + setbits_le32(RCB_REG(0x2320), BIT(15) | BIT(1)); clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); writel(0x054f0000, RCB_REG(0x3318)); writel(0x04000000, RCB_REG(0x3324)); setbits_le32(RCB_REG(0x3340), 0xfffff); - setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); + setbits_le32(RCB_REG(0x3344), BIT(1) | BIT(0)); writel(0x0001c000, RCB_REG(0x3360)); writel(0x00061100, RCB_REG(0x3368)); writel(0x7f8fdfff, RCB_REG(0x3378)); @@ -339,7 +339,7 @@ static void ppt_pm_init(pci_dev_t dev) writel(0x00000001, RCB_REG(0x3a6c)); clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); - setbits_le32(RCB_REG(0x33a4), (1 << 0)); + setbits_le32(RCB_REG(0x33a4), BIT(0)); writel(0, RCB_REG(0x33c8)); setbits_le32(RCB_REG(0x21b0), 0xf); } @@ -358,26 +358,26 @@ static void enable_clock_gating(pci_dev_t dev) setbits_le32(RCB_REG(0x2234), 0xf); reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 |= BIT(2) | BIT(11); x86_pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0UL, BIT(31)); + pch_iobp_update(0xEB004000, ~0UL, BIT(7)); + pch_iobp_update(0xEC007F07, ~0UL, BIT(31)); + pch_iobp_update(0xEC004000, ~0UL, BIT(7)); reg32 = readl(RCB_REG(CG)); - reg32 |= (1 << 31); - reg32 |= (1 << 29) | (1 << 28); - reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); - reg32 |= (1 << 16); - reg32 |= (1 << 17); - reg32 |= (1 << 18); - reg32 |= (1 << 22); - reg32 |= (1 << 23); - reg32 &= ~(1 << 20); - reg32 |= (1 << 19); - reg32 |= (1 << 0); + reg32 |= BIT(31); + reg32 |= BIT(29) | BIT(28); + reg32 |= BIT(27) | BIT(26) | BIT(25) | BIT(24); + reg32 |= BIT(16); + reg32 |= BIT(17); + reg32 |= BIT(18); + reg32 |= BIT(22); + reg32 |= BIT(23); + reg32 &= ~BIT(20); + reg32 |= BIT(19); + reg32 |= BIT(0); reg32 |= (0xf << 1); writel(reg32, RCB_REG(CG)); @@ -416,9 +416,9 @@ static void pch_lock_smm(pci_dev_t dev) reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", (reg8 & 1) ? "rw" : "ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ + reg8 &= ~BIT(0); /* clear BIOSWE */ x86_pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ + reg8 |= BIT(1); /* set BLE */ x86_pci_write_config8(dev, 0xdc, reg8); debug("ok.\n"); reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ @@ -428,7 +428,7 @@ static void pch_lock_smm(pci_dev_t dev) debug("Writing:\n"); writeb(0, 0xfff00000); debug("Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ + reg8 |= BIT(0); /* set BIOSWE */ x86_pci_write_config8(dev, 0xdc, reg8); reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ @@ -445,7 +445,7 @@ static void pch_disable_smm_only_flashing(pci_dev_t dev) debug("Enabling BIOS updates outside of SMM... "); reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - reg8 &= ~(1 << 5); + reg8 &= ~BIT(5); x86_pci_write_config8(dev, 0xdc, reg8); } @@ -455,12 +455,12 @@ static void pch_fixups(pci_dev_t dev) /* Indicate DRAM init done for MRC S3 to know it can resume */ gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); + gen_pmcon_2 |= BIT(7); x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); /* Enable DMI ASPM in the PCH */ clrbits_le32(RCB_REG(0x2304), 1 << 10); - setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); + setbits_le32(RCB_REG(0x21a4), BIT(11) | BIT(10)); setbits_le32(RCB_REG(0x21a8), 0x3); } diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 11dc625..f0488ab 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -38,7 +38,7 @@ static void enable_vmx(void) msr = msr_read(MSR_IA32_FEATURE_CONTROL); - if (msr.lo & (1 << 0)) { + if (msr.lo & BIT(0)) { debug("VMX is locked, so %s will do nothing\n", __func__); /* VMX locked. If we set it again we get an illegal * instruction @@ -71,9 +71,9 @@ static void enable_vmx(void) * cores). */ if (enable) { - msr.lo |= (1 << 2); + msr.lo |= BIT(2); if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); + msr.lo |= BIT(1); } msr_write(MSR_IA32_FEATURE_CONTROL, msr); @@ -224,11 +224,11 @@ static void configure_c_states(void) msr_t msr; msr = msr_read(MSR_PMG_CST_CONFIG_CTL); - msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ - msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ - msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ - msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ - msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ + msr.lo |= BIT(28); /* C1 Auto Undemotion Enable */ + msr.lo |= BIT(27); /* C3 Auto Undemotion Enable */ + msr.lo |= BIT(26); /* C1 Auto Demotion Enable */ + msr.lo |= BIT(25); /* C3 Auto Demotion Enable */ + msr.lo &= ~BIT(10); /* Disable IO MWAIT redirection */ msr.lo |= 7; /* No package C-state limit */ msr_write(MSR_PMG_CST_CONFIG_CTL, msr); @@ -239,13 +239,13 @@ static void configure_c_states(void) msr_write(MSR_PMG_IO_CAPTURE_ADR, msr); msr = msr_read(MSR_MISC_PWR_MGMT); - msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ + msr.lo &= ~BIT(0); /* Enable P-state HW_ALL coordination */ msr_write(MSR_MISC_PWR_MGMT, msr); msr = msr_read(MSR_POWER_CTL); - msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ - msr.lo |= (1 << 1); /* C1E Enable */ - msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ + msr.lo |= BIT(18); /* Enable Energy Perf Bias MSR 0x1b0 */ + msr.lo |= BIT(1); /* C1E Enable */ + msr.lo |= BIT(0); /* Bi-directional PROCHOT# */ msr_write(MSR_POWER_CTL, msr); /* C3 Interrupt Response Time Limit */ @@ -295,7 +295,7 @@ static int configure_thermal_target(void) /* Set TCC activaiton offset if supported */ msr = msr_read(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && tcc_offset) { + if ((msr.lo & BIT(30)) && tcc_offset) { msr = msr_read(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (tcc_offset & 0xf) << 24; @@ -310,9 +310,9 @@ static void configure_misc(void) msr_t msr; msr = msr_read(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= BIT(0); /* Fast String enable */ + msr.lo |= BIT(3); /* TM1/TM2/EMTTM enable */ + msr.lo |= BIT(16); /* Enhanced SpeedStep Enable */ msr_write(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ @@ -331,7 +331,7 @@ static void enable_lapic_tpr(void) msr_t msr; msr = msr_read(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + msr.lo &= ~BIT(10); /* Enable APIC TPR updates */ msr_write(MSR_PIC_MSG_CONTROL, msr); } @@ -342,7 +342,7 @@ static void configure_dca_cap(void) /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ cpuid_regs = cpuid(1); - if (cpuid_regs.ecx & (1 << 18)) { + if (cpuid_regs.ecx & BIT(18)) { msr = msr_read(IA32_PLATFORM_DCA_CAP); msr.lo |= 1; msr_write(IA32_PLATFORM_DCA_CAP, msr); diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e95e60e..445dbaf 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -57,23 +57,23 @@ static int get_pcie_bar(u32 *base, u32 *len) pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR); - if (!(pciexbar_reg & (1 << 0))) + if (!(pciexbar_reg & BIT(0))) return 0; switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); + *base = pciexbar_reg & (BIT(31) | BIT(30) | BIT(29) | + BIT(28)); *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); + *base = pciexbar_reg & (BIT(31) | BIT(30) | BIT(29) | + BIT(28) | BIT(27)); *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); + *base = pciexbar_reg & (BIT(31) | BIT(30) | BIT(29) | + BIT(28) | BIT(27) | BIT(26)); *len = 64 * 1024 * 1024; return 1; } @@ -99,7 +99,7 @@ static void northbridge_dmi_init(pci_dev_t dev) /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), + clrsetbits_le32(DMIBAR_REG(0x250), BIT(22) | BIT(20), 1 << 21); } @@ -109,14 +109,14 @@ static void northbridge_dmi_init(pci_dev_t dev) setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); } else if (bridge_silicon_revision() >= SNB_STEP_D1) { clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); - setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); + setbits_le32(DMIBAR_REG(0x1fc), BIT(12) | BIT(23)); } /* Enable ASPM on SNB link, should happen before PCH link */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) setbits_le32(DMIBAR_REG(0xd04), 1 << 4); - setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); + setbits_le32(DMIBAR_REG(0x88), BIT(1) | BIT(0)); } void northbridge_init(pci_dev_t dev) diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c index 4493870..1bf5950 100644 --- a/arch/x86/cpu/ivybridge/report_platform.c +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -30,9 +30,9 @@ static void report_cpu_info(void) cpuidr = cpuid(1); debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + aes = (cpuidr.ecx & BIT(25)) ? 1 : 0; + txt = (cpuidr.ecx & BIT(6)) ? 1 : 0; + vt = (cpuidr.ecx & BIT(5)) ? 1 : 0; debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); } diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c index f77b804..ec02fba 100644 --- a/arch/x86/cpu/ivybridge/usb_xhci.c +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -22,10 +22,10 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev) /* Enable clock gating */ reg32 = x86_pci_read_config32(dev, 0x40); - reg32 &= ~((1 << 20) | (1 << 21)); - reg32 |= (1 << 19) | (1 << 18) | (1 << 17); - reg32 |= (1 << 10) | (1 << 9) | (1 << 8); - reg32 |= (1 << 31); /* lock */ + reg32 &= ~(BIT(20) | BIT(21)); + reg32 |= BIT(19) | BIT(18) | BIT(17); + reg32 |= BIT(10) | BIT(9) | BIT(8); + reg32 |= BIT(31); /* lock */ x86_pci_write_config32(dev, 0x40, reg32); debug("done.\n"); diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index db601e4..9409dc6 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -44,11 +44,11 @@ static void hte_wait_for_complete(void) ENTERFN(); - do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0); + do {} while ((msg_port_read(HTE, 0x00020012) & BIT(30)) != 0); tmp = msg_port_read(HTE, 0x00020011); - tmp |= (1 << 9); - tmp &= ~((1 << 12) | (1 << 13)); + tmp |= BIT(9); + tmp &= ~(BIT(12) | BIT(13)); msg_port_write(HTE, 0x00020011, tmp); LEAVEFN(); @@ -66,7 +66,7 @@ static void hte_clear_error_regs(void) * for burst and chunk. */ tmp = msg_port_read(HTE, 0x000200a1); - tmp |= (1 << 8); + tmp |= BIT(8); msg_port_write(HTE, 0x000200a1, tmp); } @@ -177,7 +177,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, tmp = 0x10001000 | (loop_cnt << 16); msg_port_write(HTE, 0x00020011, tmp); - msg_port_write(HTE, 0x00020011, tmp | (1 << 8)); + msg_port_write(HTE, 0x00020011, tmp | BIT(8)); hte_wait_for_complete(); diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 49d803d..46c2fcb 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -184,12 +184,12 @@ void set_rcvn(uint8_t channel, uint8_t rank, temp = 0x00; /* enable */ - msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); + msk |= (byte_lane & 1) ? BIT(5) : BIT(2); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); + msk |= (byte_lane & 1) ? BIT(11) : BIT(8); if (pi_count < EARLY_DB) temp |= msk; @@ -378,12 +378,12 @@ void set_wdqs(uint8_t channel, uint8_t rank, temp = 0x00; /* enable */ - msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); + msk |= (byte_lane & 1) ? BIT(4) : BIT(1); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); + msk |= (byte_lane & 1) ? BIT(10) : BIT(7); if (pi_count < EARLY_DB) temp |= msk; @@ -502,12 +502,12 @@ void set_wdq(uint8_t channel, uint8_t rank, temp = 0x00; /* enable */ - msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); + msk |= (byte_lane & 1) ? BIT(3) : BIT(0); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); + msk |= (byte_lane & 1) ? BIT(9) : BIT(6); if (pi_count < EARLY_DB) temp |= msk; @@ -625,12 +625,12 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) temp = 0x00; /* enable */ - msk |= (1 << 16); + msk |= BIT(16); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (1 << 17); + msk |= BIT(17); if (pi_count < EARLY_DB) temp |= msk; @@ -1036,8 +1036,8 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, uint32_t address = get_addr(channel, rank); /* initialise msk[] */ - msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */ - msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */ + msk[0] = rcvn ? BIT(1) : BIT(9); /* BL0 */ + msk[1] = rcvn ? BIT(0) : BIT(8); /* BL1 */ /* cycle through each byte lane group */ for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { @@ -1361,13 +1361,13 @@ void clear_pointers(void) B01PTRCTL1 + channel * DDRIODQ_CH_OFFSET + (bl >> 1) * DDRIODQ_BL_OFFSET, - ~(1 << 8), (1 << 8)); + ~BIT(8), BIT(8)); mrc_alt_write_mask(DDRPHY, B01PTRCTL1 + channel * DDRIODQ_CH_OFFSET + (bl >> 1) * DDRIODQ_BL_OFFSET, - (1 << 8), (1 << 8)); + BIT(8), BIT(8)); } } diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index 3ffe92b..876307a 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -121,7 +121,7 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr1 &= ~DTR1_TRRD_MASK; dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ dtr1 &= ~DTR1_TCMD_MASK; - dtr1 |= (1 << 4); + dtr1 |= BIT(4); dtr1 &= ~DTR1_TRAS_MASK; dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ dtr1 &= ~DTR1_TFAW_MASK; @@ -162,7 +162,7 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr4 &= ~DTR4_WRODTSTRT_MASK; dtr4 |= 1; dtr4 &= ~DTR4_WRODTSTOP_MASK; - dtr4 |= (1 << 4); + dtr4 |= BIT(4); dtr4 &= ~DTR4_XXXX1_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); dtr4 &= ~DTR4_XXXX2_MASK; @@ -287,15 +287,15 @@ void ddrphy_init(struct mrc_params *mrc_params) /* Deassert DDRPHY Initialization Complete */ mrc_alt_write_mask(DDRPHY, CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, - ~(1 << 20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ + ~BIT(20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ /* Deassert IOBUFACT */ mrc_alt_write_mask(DDRPHY, CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, - ~(1 << 2), 1 << 2); /* IOBUFACTRST_N=0 */ + ~BIT(2), 1 << 2); /* IOBUFACTRST_N=0 */ /* Disable WRPTR */ mrc_alt_write_mask(DDRPHY, CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, - ~(1 << 0), 1 << 0); /* WRPTRENABLE=0 */ + ~BIT(0), 1 << 0); /* WRPTRENABLE=0 */ } } @@ -317,7 +317,7 @@ void ddrphy_init(struct mrc_params *mrc_params) DQOBSCKEBBCTL + bl_grp * DDRIODQ_BL_OFFSET + ch * DDRIODQ_CH_OFFSET, - bl_grp ? 0 : (1 << 22), 1 << 22); + bl_grp ? 0 : BIT(22), 1 << 22); /* ODT Strength */ switch (mrc_params->rd_odt_value) { @@ -592,7 +592,7 @@ void ddrphy_init(struct mrc_params *mrc_params) /* DQS Swapped Input Enable */ mrc_alt_write_mask(DDRPHY, COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 19) | (1 << 17), 0xc00ac000); + BIT(19) | BIT(17), 0xc00ac000); /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ /* ODT Vref PU/PD */ @@ -640,32 +640,32 @@ void ddrphy_init(struct mrc_params *mrc_params) /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x10 << 16), + BIT(31) | (0x10 << 16), 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x10 << 16), + BIT(31) | (0x10 << 16), 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, @@ -680,32 +680,32 @@ void ddrphy_init(struct mrc_params *mrc_params) /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x10 << 16), + BIT(31) | (0x10 << 16), 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x10 << 16), + BIT(31) | (0x10 << 16), 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, @@ -720,32 +720,32 @@ void ddrphy_init(struct mrc_params *mrc_params) /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0c << 16), + BIT(31) | (0x0c << 16), 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0c << 16), + BIT(31) | (0x0c << 16), 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x07 << 16), + BIT(31) | (0x07 << 16), 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x07 << 16), + BIT(31) | (0x07 << 16), 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0b << 16), + BIT(31) | (0x0b << 16), 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, @@ -760,80 +760,80 @@ void ddrphy_init(struct mrc_params *mrc_params) /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0d << 16), + BIT(31) | (0x0d << 16), 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0d << 16), + BIT(31) | (0x0d << 16), 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* CTL COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0d << 16), + BIT(31) | (0x0d << 16), 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0d << 16), + BIT(31) | (0x0d << 16), 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x0a << 16), + BIT(31) | (0x0a << 16), 0x801f0000); #else /* DQ TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); /* DQS TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); /* CLK TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, - (1 << 31) | (0x1f << 16), + BIT(31) | (0x1f << 16), 0x801f0000); #endif @@ -1109,7 +1109,7 @@ void ddrphy_init(struct mrc_params *mrc_params) 1 << 24, 1 << 24); while (msg_port_alt_read(DDRPHY, CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & - (1 << 24)) + BIT(24)) ; /* wait for START_CLK_ALIGN=0 */ #endif @@ -1131,7 +1131,7 @@ void ddrphy_init(struct mrc_params *mrc_params) /* disable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, - ~(1 << 5), 1 << 5); + ~BIT(5), 1 << 5); /* IOBUFACT */ @@ -1252,13 +1252,13 @@ void perform_jedec_init(struct mrc_params *mrc_params) * 011 --> RZQ/6 ( 40ohm) * 1** --> RESERVED */ - emrs1_cmd |= (1 << 3); - emrs1_cmd &= ~(1 << 6); + emrs1_cmd |= BIT(3); + emrs1_cmd &= ~BIT(6); if (mrc_params->ron_value == 0) - emrs1_cmd |= (1 << 7); + emrs1_cmd |= BIT(7); else - emrs1_cmd &= ~(1 << 7); + emrs1_cmd &= ~BIT(7); if (mrc_params->rtt_nom_value == 0) emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6); @@ -1293,8 +1293,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) * BIT[02:02] "0" if oem_tCAS <= 11 (1866?) * BIT[06:04] use oem_tCAS-4 */ - mrs0_cmd |= (1 << 14); - mrs0_cmd |= (1 << 18); + mrs0_cmd |= BIT(14); + mrs0_cmd |= BIT(18); mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); tck = t_ck[mrc_params->ddr_speed]; @@ -2412,8 +2412,8 @@ void prog_dra_drb(struct mrc_params *mrc_params) if (mrc_params->rank_enables & 2) drp |= DRP_RKEN1; if (mrc_params->dram_width == X16) { - drp |= (1 << 4); - drp |= (1 << 9); + drp |= BIT(4); + drp |= BIT(9); } /* diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h index 1582b87..c6263f0 100644 --- a/arch/x86/cpu/quark/smc.h +++ b/arch/x86/cpu/quark/smc.h @@ -44,11 +44,11 @@ #define SCRMHI 0x82 /* DRP register defines */ -#define DRP_RKEN0 (1 << 0) -#define DRP_RKEN1 (1 << 1) -#define DRP_PRI64BSPLITEN (1 << 13) -#define DRP_ADDRMAP_MAP0 (1 << 14) -#define DRP_ADDRMAP_MAP1 (1 << 15) +#define DRP_RKEN0 BIT(0) +#define DRP_RKEN1 BIT(1) +#define DRP_PRI64BSPLITEN BIT(13) +#define DRP_ADDRMAP_MAP0 BIT(14) +#define DRP_ADDRMAP_MAP1 BIT(15) #define DRP_ADDRMAP_MASK 0x0000c000 /* DTR0 register defines */ @@ -61,8 +61,8 @@ #define DTR1_TWCL_MASK 0x00000007 #define DTR1_TCMD_MASK 0x00000030 #define DTR1_TWTP_MASK 0x00000f00 -#define DTR1_TCCD_12CLK (1 << 12) -#define DTR1_TCCD_18CLK (1 << 13) +#define DTR1_TCCD_12CLK BIT(12) +#define DTR1_TCCD_18CLK BIT(13) #define DTR1_TCCD_MASK 0x00003000 #define DTR1_TFAW_MASK 0x000f0000 #define DTR1_TRAS_MASK 0x00f00000 @@ -86,52 +86,52 @@ #define DTR4_WRODTSTOP_MASK 0x00000070 #define DTR4_XXXX1_MASK 0x00000700 #define DTR4_XXXX2_MASK 0x00007000 -#define DTR4_ODTDIS (1 << 15) -#define DTR4_TRGSTRDIS (1 << 16) +#define DTR4_ODTDIS BIT(15) +#define DTR4_TRGSTRDIS BIT(16) /* DPMC0 register defines */ #define DPMC0_PCLSTO_MASK 0x00070000 -#define DPMC0_PREAPWDEN (1 << 21) -#define DPMC0_DYNSREN (1 << 23) -#define DPMC0_CLKGTDIS (1 << 24) -#define DPMC0_DISPWRDN (1 << 25) -#define DPMC0_ENPHYCLKGATE (1 << 29) +#define DPMC0_PREAPWDEN BIT(21) +#define DPMC0_DYNSREN BIT(23) +#define DPMC0_CLKGTDIS BIT(24) +#define DPMC0_DISPWRDN BIT(25) +#define DPMC0_ENPHYCLKGATE BIT(29) /* DRFC register defines */ #define DRFC_TREFI_MASK 0x00007000 -#define DRFC_REFDBTCLR (1 << 21) +#define DRFC_REFDBTCLR BIT(21) /* DSCH register defines */ -#define DSCH_OOODIS (1 << 8) -#define DSCH_OOOST3DIS (1 << 9) -#define DSCH_NEWBYPDIS (1 << 12) +#define DSCH_OOODIS BIT(8) +#define DSCH_OOOST3DIS BIT(9) +#define DSCH_NEWBYPDIS BIT(12) /* DCAL register defines */ #define DCAL_ZQCINT_MASK 0x00000700 #define DCAL_SRXZQCL_MASK 0x00003000 /* DRMC register defines */ -#define DRMC_CKEMODE (1 << 4) -#define DRMC_ODTMODE (1 << 12) -#define DRMC_COLDWAKE (1 << 16) +#define DRMC_CKEMODE BIT(4) +#define DRMC_ODTMODE BIT(12) +#define DRMC_COLDWAKE BIT(16) /* PMSTS register defines */ -#define PMSTS_DISR (1 << 0) +#define PMSTS_DISR BIT(0) /* DCO register defines */ -#define DCO_DRPLOCK (1 << 0) -#define DCO_CPGCLOCK (1 << 8) -#define DCO_PMICTL (1 << 28) -#define DCO_PMIDIS (1 << 29) -#define DCO_IC (1 << 31) +#define DCO_DRPLOCK BIT(0) +#define DCO_CPGCLOCK BIT(8) +#define DCO_PMICTL BIT(28) +#define DCO_PMIDIS BIT(29) +#define DCO_IC BIT(31) /* DECCCTRL register defines */ -#define DECCCTRL_SBEEN (1 << 0) -#define DECCCTRL_DBEEN (1 << 1) -#define DECCCTRL_ENCBGEN (1 << 17) +#define DECCCTRL_SBEEN BIT(0) +#define DECCCTRL_DBEEN BIT(1) +#define DECCCTRL_ENCBGEN BIT(17) /* DRAM init command */ -#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) +#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | BIT(3) | ((dat) << 6)) #define DCMD_REF(rnk) (1 | ((rnk) << 22)) #define DCMD_PRE(rnk) (2 | ((rnk) << 22)) #define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6)) @@ -152,8 +152,8 @@ #define DDR3_EMRS1_RTTNOM_20 0x200 #define DDR3_EMRS1_RTTNOM_30 0x204 -#define DDR3_EMRS2_RTTWR_60 (1 << 9) -#define DDR3_EMRS2_RTTWR_120 (1 << 10) +#define DDR3_EMRS2_RTTWR_60 BIT(9) +#define DDR3_EMRS2_RTTWR_120 BIT(10) /* BEGIN DDRIO Registers */ diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 2e5f9da..7b57ab4 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -230,9 +230,9 @@ multiboot_header: /* magic */ .long 0x1BADB002 /* flags */ - .long (1 << 16) + .long BIT(16) /* checksum */ - .long -0x1BADB002 - (1 << 16) + .long -0x1BADB002 - BIT(16) /* header addr */ .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE /* load addr */ diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 7b4f2e7..e76a75b 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -12,12 +12,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) +#define CPUID_VMX BIT(5) +#define CPUID_SMX BIT(6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) +#define FLEX_RATIO_LOCK BIT(20) +#define FLEX_RATIO_EN BIT(16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 @@ -32,19 +32,19 @@ #define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e -#define PLATFORM_INFO_SET_TDP (1 << 29) +#define PLATFORM_INFO_SET_TDP BIT(29) #define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_EIST_HW_DIS BIT(0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc #define MSR_PKGC3_IRTL 0x60a #define MSR_PKGC6_IRTL 0x60b #define MSR_PKGC7_IRTL 0x60c -#define IRTL_VALID (1 << 15) +#define IRTL_VALID BIT(15) #define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) +#define IRTL_32_NS BIT(10) #define IRTL_1024_NS (2 << 10) #define IRTL_32768_NS (3 << 10) #define IRTL_1048576_NS (4 << 10) @@ -53,8 +53,8 @@ /* long duration in low dword, short duration in high dword */ #define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_EN BIT(15) +#define PKG_POWER_LIMIT_CLAMP BIT(16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083..a4b8762 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -45,9 +45,9 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR BIT(6) +#define SEE BIT(1) +#define PERE BIT(0) #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) @@ -66,13 +66,13 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE BIT(18) +#define ETR3_CF9GR BIT(20) /* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) +#define RTC_BATTERY_DEAD BIT(2) +#define RTC_POWER_FAILED BIT(1) +#define SLEEP_AFTER_POWER_FAIL BIT(0) #define PMBASE 0x40 #define ACPI_CNTL 0x44 @@ -94,8 +94,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE BIT(18) +#define ETR3_CF9GR BIT(20) #define PMBASE 0x40 #define ACPI_CNTL 0x44 @@ -106,16 +106,16 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define CNF2_LPC_EN BIT(13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN BIT(12) /* 0x2e/0x2f */ +#define MC_LPC_EN BIT(11) /* 0x62/0x66 */ +#define KBC_LPC_EN BIT(10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN BIT(9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN BIT(8) /* 0x200/0x207 */ +#define FDD_LPC_EN BIT(3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN BIT(2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN BIT(1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN BIT(0) /* LPC_IO_DEC[3:2] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -129,10 +129,10 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) +#define IDE_DECODE_ENABLE BIT(15) +#define IDE_SITRE BIT(14) #define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_4_CLOCKS BIT(12) #define IDE_ISP_3_CLOCKS (2 << 12) #define IDE_RCT_4_CLOCKS (0 << 8) #define IDE_RCT_3_CLOCKS (1 << 8) @@ -158,15 +158,15 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ #define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_TRISTATE BIT(18) #define SIG_MODE_SEC_DRIVELOW (2 << 18) #define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_TRISTATE BIT(16) #define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) +#define FAST_SCB1 BIT(15) +#define FAST_SCB0 BIT(14) +#define FAST_PCB1 BIT(13) +#define FAST_PCB0 BIT(12) #define SCB1 (1 << 3) #define SCB0 (1 << 2) #define PCB1 (1 << 1) @@ -187,9 +187,9 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define SMB_RCV_SLVA 0x09 /* HOSTC bits */ -#define I2C_EN (1 << 2) -#define SMB_SMI_EN (1 << 1) -#define HST_EN (1 << 0) +#define I2C_EN BIT(2) +#define SMB_SMI_EN BIT(1) +#define HST_EN BIT(0) /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 @@ -285,9 +285,9 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) +#define IOBPS_RW_BX (BIT(9)|BIT(10)) +#define IOBPS_WRITE_AX (BIT(9)|BIT(10)) +#define IOBPS_READ_AX (BIT(8)|BIT(9)|BIT(10)) #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -345,32 +345,32 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) +#define PCH_DISABLE_GBE BIT(5) #define FD 0x3418 /* 32bit */ #define DISPBDF 0x3424 /* 16bit */ #define FD2 0x3428 /* 32bit */ #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) -#define PCH_DISABLE_P2P (1 << 1) -#define PCH_DISABLE_SATA1 (1 << 2) -#define PCH_DISABLE_SMBUS (1 << 3) -#define PCH_DISABLE_HD_AUDIO (1 << 4) -#define PCH_DISABLE_EHCI2 (1 << 13) -#define PCH_DISABLE_LPC (1 << 14) -#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_ALWAYS (BIT(0)|BIT(26)) +#define PCH_DISABLE_P2P BIT(1) +#define PCH_DISABLE_SATA1 BIT(2) +#define PCH_DISABLE_SMBUS BIT(3) +#define PCH_DISABLE_HD_AUDIO BIT(4) +#define PCH_DISABLE_EHCI2 BIT(13) +#define PCH_DISABLE_LPC BIT(14) +#define PCH_DISABLE_EHCI1 BIT(15) #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) -#define PCH_DISABLE_THERMAL (1 << 24) -#define PCH_DISABLE_SATA2 (1 << 25) -#define PCH_DISABLE_XHCI (1 << 27) +#define PCH_DISABLE_THERMAL BIT(24) +#define PCH_DISABLE_SATA2 BIT(25) +#define PCH_DISABLE_XHCI BIT(27) /* Function Disable 2 RCBA 0x3428 */ -#define PCH_DISABLE_KT (1 << 4) -#define PCH_DISABLE_IDER (1 << 3) -#define PCH_DISABLE_MEI2 (1 << 2) -#define PCH_DISABLE_MEI1 (1 << 1) -#define PCH_ENABLE_DBDF (1 << 0) +#define PCH_DISABLE_KT BIT(4) +#define PCH_DISABLE_IDER BIT(3) +#define PCH_DISABLE_MEI2 BIT(2) +#define PCH_DISABLE_MEI1 BIT(1) +#define PCH_ENABLE_DBDF BIT(0) /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 @@ -390,31 +390,31 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS BIT(15) +#define PCIEXPWAK_STS BIT(14) +#define PRBTNOR_STS BIT(11) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TMROF_STS BIT(0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS BIT(14) +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TMROF_EN BIT(0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) +#define SLP_EN BIT(13) #define SLP_TYP (7 << 10) #define SLP_TYP_S0 0 #define SLP_TYP_S1 1 #define SLP_TYP_S3 5 #define SLP_TYP_S4 6 #define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define GBL_RLS BIT(2) +#define BM_RLD BIT(1) +#define SCI_EN BIT(0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -422,25 +422,25 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define LV4 0x16 #define PM2_CNT 0x50 /* mobile only */ #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS BIT(13) +#define PME_STS BIT(11) +#define BATLOW_STS BIT(10) +#define PCI_EXP_STS BIT(9) +#define RI_STS BIT(8) +#define SMB_WAK_STS BIT(7) +#define TCOSCI_STS BIT(6) +#define SWGPE_STS BIT(2) +#define HOT_PLUG_STS BIT(1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN BIT(13) +#define PME_EN BIT(11) +#define TCOSCI_EN BIT(6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ -#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ -#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ -#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ -#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ +#define INTEL_USB2_EN BIT(18) /* Intel-Specific USB2 SMI logic */ +#define LEGACY_USB2_EN BIT(17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN BIT(14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN BIT(13) /* Enable TCO Logic (BIOSWE et al) */ +#define MCSMI_EN BIT(11) /* Trap microcontroller range access */ #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ @@ -457,7 +457,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS BIT(9) #define TCO2_STS 0x66 int lpc_init(struct pci_controller *hose, pci_dev_t dev); diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index c960525..01f5cad 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -55,12 +55,12 @@ #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ -#define DEVEN_PEG60 (1 << 13) -#define DEVEN_IGD (1 << 4) -#define DEVEN_PEG10 (1 << 3) -#define DEVEN_PEG11 (1 << 2) -#define DEVEN_PEG12 (1 << 1) -#define DEVEN_HOST (1 << 0) +#define DEVEN_PEG60 BIT(13) +#define DEVEN_IGD BIT(4) +#define DEVEN_PEG10 BIT(3) +#define DEVEN_PEG11 BIT(2) +#define DEVEN_PEG12 BIT(1) +#define DEVEN_HOST BIT(0) #define PAM0 0x80 #define PAM1 0x81 @@ -72,11 +72,11 @@ #define LAC 0x87 /* Legacy Access Control */ #define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN BIT(6) +#define D_CLS BIT(5) +#define D_LCK BIT(4) +#define G_SMRAME BIT(3) +#define C_BASE_SEG ((0 << 2) | BIT(1) | (0 << 0)) #define TOM 0xa0 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h index 699160f..1dc0bba 100644 --- a/arch/x86/include/asm/ioapic.h +++ b/arch/x86/include/asm/ioapic.h @@ -16,18 +16,18 @@ #define ALL (0xff << 24) #define NONE 0 -#define DISABLED (1 << 16) +#define DISABLED BIT(16) #define ENABLED (0 << 16) #define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) +#define TRIGGER_LEVEL BIT(15) #define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) +#define POLARITY_LOW BIT(13) #define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) +#define LOGICAL_DEST BIT(11) #define ExtINT (7 << 8) #define NMI (4 << 8) #define SMI (2 << 8) -#define INT (1 << 8) +#define INT BIT(8) u32 io_apic_read(u32 ioapic_base, u32 reg); void io_apic_write(u32 ioapic_base, u32 reg, u32 value); diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h index 0a7f443..5592343 100644 --- a/arch/x86/include/asm/lapic.h +++ b/arch/x86/include/asm/lapic.h @@ -55,7 +55,7 @@ static inline void disable_lapic(void) msr_t msr; msr = msr_read(LAPIC_BASE_MSR); - msr.lo &= ~(1 << 11); + msr.lo &= ~BIT(11); msr_write(LAPIC_BASE_MSR, msr); } diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h index 722cead..689bdee 100644 --- a/arch/x86/include/asm/lapic_def.h +++ b/arch/x86/include/asm/lapic_def.h @@ -10,8 +10,8 @@ #define _ASM_LAPIC_DEF_H #define LAPIC_BASE_MSR 0x1B -#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) -#define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR BIT(8) +#define LAPIC_BASE_MSR_ENABLE BIT(11) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 #define LOCAL_APIC_ADDR 0xfee00000 @@ -67,13 +67,13 @@ #define LAPIC_TIMER_BASE_CLKIN 0x0 #define LAPIC_TIMER_BASE_TMBASE 0x1 #define LAPIC_TIMER_BASE_DIV 0x2 -#define LAPIC_LVT_TIMER_PERIODIC (1 << 17) -#define LAPIC_LVT_MASKED (1 << 16) -#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15) -#define LAPIC_LVT_REMOTE_IRR (1 << 14) -#define LAPIC_INPUT_POLARITY (1 << 13) -#define LAPIC_SEND_PENDING (1 << 12) -#define LAPIC_LVT_RESERVED_1 (1 << 11) +#define LAPIC_LVT_TIMER_PERIODIC BIT(17) +#define LAPIC_LVT_MASKED BIT(16) +#define LAPIC_LVT_LEVEL_TRIGGER BIT(15) +#define LAPIC_LVT_REMOTE_IRR BIT(14) +#define LAPIC_INPUT_POLARITY BIT(13) +#define LAPIC_SEND_PENDING BIT(12) +#define LAPIC_LVT_RESERVED_1 BIT(11) #define LAPIC_DELIVERY_MODE_MASK (7 << 8) #define LAPIC_DELIVERY_MODE_FIXED (0 << 8) #define LAPIC_DELIVERY_MODE_NMI (4 << 8) @@ -88,7 +88,7 @@ #define LAPIC_TMICT 0x380 #define LAPIC_TMCCT 0x390 #define LAPIC_TDCR 0x3E0 -#define LAPIC_TDR_DIV_TMBASE (1 << 2) +#define LAPIC_TDR_DIV_TMBASE BIT(2) #define LAPIC_TDR_DIV_1 0xB #define LAPIC_TDR_DIV_2 0x0 #define LAPIC_TDR_DIV_4 0x1 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2cbb270..61578d3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -334,14 +334,14 @@ #define MSR_IA32_THERM_CONTROL 0x0000019a #define MSR_IA32_THERM_INTERRUPT 0x0000019b -#define THERM_INT_HIGH_ENABLE (1 << 0) -#define THERM_INT_LOW_ENABLE (1 << 1) -#define THERM_INT_PLN_ENABLE (1 << 24) +#define THERM_INT_HIGH_ENABLE BIT(0) +#define THERM_INT_LOW_ENABLE BIT(1) +#define THERM_INT_PLN_ENABLE BIT(24) #define MSR_IA32_THERM_STATUS 0x0000019c -#define THERM_STATUS_PROCHOT (1 << 0) -#define THERM_STATUS_POWER_LIMIT (1 << 10) +#define THERM_STATUS_PROCHOT BIT(0) +#define THERM_STATUS_POWER_LIMIT BIT(10) #define MSR_THERM2_CTL 0x0000019d @@ -358,26 +358,26 @@ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 -#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) -#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) +#define PACKAGE_THERM_STATUS_PROCHOT BIT(0) +#define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10) #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 -#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) -#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) -#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +#define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0) +#define PACKAGE_THERM_INT_LOW_ENABLE BIT(1) +#define PACKAGE_THERM_INT_PLN_ENABLE BIT(24) /* Thermal Thresholds Support */ -#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) +#define THERM_INT_THRESHOLD0_ENABLE BIT(15) #define THERM_SHIFT_THRESHOLD0 8 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) -#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) +#define THERM_INT_THRESHOLD1_ENABLE BIT(23) #define THERM_SHIFT_THRESHOLD1 16 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) -#define THERM_STATUS_THRESHOLD0 (1 << 6) -#define THERM_LOG_THRESHOLD0 (1 << 7) -#define THERM_STATUS_THRESHOLD1 (1 << 8) -#define THERM_LOG_THRESHOLD1 (1 << 9) +#define THERM_STATUS_THRESHOLD0 BIT(6) +#define THERM_LOG_THRESHOLD0 BIT(7) +#define THERM_STATUS_THRESHOLD1 BIT(8) +#define THERM_LOG_THRESHOLD1 BIT(9) /* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index fda4eae..e411d6a 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -21,13 +21,13 @@ #define MTRR_CAP_MSR 0x0fe #define MTRR_DEF_TYPE_MSR 0x2ff -#define MTRR_DEF_TYPE_EN (1 << 11) -#define MTRR_DEF_TYPE_FIX_EN (1 << 10) +#define MTRR_DEF_TYPE_EN BIT(11) +#define MTRR_DEF_TYPE_FIX_EN BIT(10) #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) -#define MTRR_PHYS_MASK_VALID (1 << 11) +#define MTRR_PHYS_MASK_VALID BIT(11) #define MTRR_BASE_TYPE_MASK 0x7 @@ -102,6 +102,6 @@ int mtrr_commit(bool do_caches); # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" #endif -#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) +#define CACHE_ROM_BASE ((BIT(20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) #endif diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h index bb0d4b4..10d05b5 100644 --- a/arch/x86/include/asm/turbo.h +++ b/arch/x86/include/asm/turbo.h @@ -10,10 +10,10 @@ #define _ASM_TURBO_H #define CPUID_LEAF_PM 6 -#define PM_CAP_TURBO_MODE (1 << 1) +#define PM_CAP_TURBO_MODE BIT(1) #define MSR_IA32_MISC_ENABLES 0x1a0 -#define H_MISC_DISABLE_TURBO (1 << 6) +#define H_MISC_DISABLE_TURBO BIT(6) enum { TURBO_UNKNOWN, diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 1d75cfc..b7984cd 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -211,9 +211,9 @@ static u8 vbe_set_mode(struct vbe_mode_info *mi) debug("VBE: Setting VESA mode %#04x\n", video_mode); /* request linear framebuffer mode */ - video_mode |= (1 << 14); + video_mode |= BIT(14); /* don't clear the framebuffer, we do that later */ - video_mode |= (1 << 15); + video_mode |= BIT(15); realmode_interrupt(0x10, VESA_SET_MODE, video_mode, 0x0000, 0x0000, 0x0000, 0x0000); @@ -224,7 +224,7 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) { unsigned char *framebuffer; - mode_info->video_mode = (1 << 14) | vesa_mode; + mode_info->video_mode = BIT(14) | vesa_mode; vbe_get_mode_info(mode_info); framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index 290990a..e4a0a40 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -97,8 +97,8 @@ break; return res; } -#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) -#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) +#define PCI_CONFIG_SPACE_TYPE1 BIT(0) +#define PCI_SPECIAL_CYCLE_TYPE1 BIT(4) int int1a_handler(void) { diff --git a/arch/x86/lib/cmd_mtrr.c b/arch/x86/lib/cmd_mtrr.c index 7e0506b..8d178d1 100644 --- a/arch/x86/lib/cmd_mtrr.c +++ b/arch/x86/lib/cmd_mtrr.c @@ -32,7 +32,7 @@ static int do_mtrr_list(void) base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); - size |= (1 << 12) - 1; + size |= BIT(12) - 1; size += 1; valid = mask & MTRR_PHYS_MASK_VALID; type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 4fd47fc..9281159 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -56,7 +56,7 @@ int calculate_relocation_address(void) #endif /* U-Boot is below the FDT */ dest_addr -= uboot_size; - dest_addr &= ~((1 << 12) - 1); + dest_addr &= ~(BIT(12) - 1); gd->relocaddr = dest_addr; gd->reloc_off = dest_addr - (uintptr_t)&__text_start; diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index c3c709e..800ccec 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Large pages are 2MB. */ -#define LARGE_PAGE_SIZE ((1 << 20) * 2) +#define LARGE_PAGE_SIZE (BIT(20) * 2) /* * Paging data structures. diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 23a98e4..f0d0076 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -564,7 +564,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 2164b52..ad24be9 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -163,21 +163,21 @@ int misc_init_r(void) void __led_toggle(led_id_t mask) { - MCFGPTA_GPTPORT ^= (1 << 3); + MCFGPTA_GPTPORT ^= BIT(3); } void __led_init(led_id_t mask, int state) { __led_set(mask, state); - MCFGPTA_GPTDDR |= (1 << 3); + MCFGPTA_GPTDDR |= BIT(3); } void __led_set(led_id_t mask, int state) { if (state == STATUS_LED_ON) - MCFGPTA_GPTPORT |= (1 << 3); + MCFGPTA_GPTPORT |= BIT(3); else - MCFGPTA_GPTPORT &= ~(1 << 3); + MCFGPTA_GPTPORT &= ~BIT(3); } #if defined(CONFIG_VIDEO) diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 3880a06..925581f 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -145,8 +145,8 @@ int board_eth_init(bd_t *bis) */ #if defined(CONFIG_CMD_NAND) -#define MASK_ALE (1 << 22) /* our ALE is AD22 */ -#define MASK_CLE (1 << 21) /* our CLE is AD21 */ +#define MASK_ALE BIT(22) /* our ALE is AD22 */ +#define MASK_CLE BIT(21) /* our CLE is AD21 */ void cpux9k2_nand_hw_init(void) { @@ -207,7 +207,7 @@ static void board_nand_hwcontrol(struct mtd_info *mtd, static int board_nand_dev_ready(struct mtd_info *mtd) { at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0); + return ((readl(&pio->pioc.pdsr) & BIT(2)) != 0); } int board_nand_init(struct nand_chip *nand) diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index e4e1a85..b35c6d3 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -195,7 +195,7 @@ int board_init(void) writel(pin, &pio->pioa.per); writel(pin, &pio->pioa.oer); writel(pin, &pio->pioa.sodr); - writel((1 << 25), &pio->pioa.codr); + writel(BIT(25), &pio->pioa.codr); pin = 0x1F000100; writel(pin, &pio->piob.idr); @@ -203,7 +203,7 @@ int board_init(void) writel(pin, &pio->piob.per); writel(pin, &pio->piob.oer); writel(pin, &pio->piob.codr); - writel((1 << 24), &pio->piob.sodr); + writel(BIT(24), &pio->piob.sodr); pin = 0x40000000; /* Pullup DRxD enbable */ writel(pin, &pio->pioc.puer); diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index d6ffefe..96df36c 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -15,8 +15,8 @@ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) void mv_phy_88e1116_init(const char *name, u16 phyaddr) { diff --git a/board/Marvell/dreamplug/dreamplug.h b/board/Marvell/dreamplug/dreamplug.h index 18ea41c..6db42b7 100644 --- a/board/Marvell/dreamplug/dreamplug.h +++ b/board/Marvell/dreamplug/dreamplug.h @@ -20,7 +20,7 @@ /* PHY related */ #define MV88E1116_MAC_CTRL2_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __DREAMPLUG_H */ diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h index 688d950..e06c606 100644 --- a/board/Marvell/guruplug/guruplug.h +++ b/board/Marvell/guruplug/guruplug.h @@ -17,7 +17,7 @@ /* PHY related */ #define MV88E1121_MAC_CTRL2_REG 21 #define MV88E1121_PGADR_REG 22 -#define MV88E1121_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1121_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1121_RGMII_TXTM_CTRL BIT(4) +#define MV88E1121_RGMII_RXTM_CTRL BIT(5) #endif /* __GURUPLUG_H */ diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index ef08ad8..2f67b51 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -110,7 +110,7 @@ void reset_phy(void) .led_init = MV88E61XX_LED_INIT_EN, .mdip = MV88E61XX_MDIP_REVERSE, .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = (1 << 5), + .cpuport = BIT(5), .ports_enabled = 0x3f }; diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h index 447e227..a3dd73e 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h @@ -9,12 +9,12 @@ #ifndef __MV88F6281GTW_GE_H #define __MV88F6281GTW_GE_H -#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \ - |(1 << 20) | (1 << 21))) /*enable GLED,RLED */ -#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \ - |(1 << 13)|(1 << 16)|(1 << 17))) -#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */ -#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17)) +#define MV88F6281GTW_GE_OE_LOW (~(BIT(7) | BIT(12) \ + |BIT(20) | BIT(21))) /*enable GLED,RLED */ +#define MV88F6281GTW_GE_OE_HIGH (~(BIT(4)|BIT(6)|BIT(7)|BIT(12) \ + |BIT(13)|BIT(16)|BIT(17))) +#define MV88F6281GTW_GE_OE_VAL_LOW BIT(20) /*make GLED on */ +#define MV88F6281GTW_GE_OE_VAL_HIGH (BIT(6)|BIT(13)|BIT(16)|BIT(17)) #endif /* __MV88F6281GTW_GE_H */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h index 56dfeea..ae50d66 100644 --- a/board/Marvell/openrd/openrd.h +++ b/board/Marvell/openrd/openrd.h @@ -17,14 +17,14 @@ #define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ #define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ #define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ +#define OPENRD_OE_VAL_HIGH BIT(2) /* Sel SD */ /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __OPENRD_BASE_H */ diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index b0020c9..56e76e9 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -146,7 +146,7 @@ void reset_phy(void) .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, .led_init = MV88E61XX_LED_INIT_EN, .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = (1 << 5), + .cpuport = BIT(5), .ports_enabled = 0x3f, }; diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h index 5e1f6a8..fc5b78c 100644 --- a/board/Marvell/rd6281a/rd6281a.h +++ b/board/Marvell/rd6281a/rd6281a.h @@ -9,17 +9,17 @@ #ifndef __RD6281A_H #define __RD6281A_H -#define RD6281A_OE_LOW (~(1 << 7)) +#define RD6281A_OE_LOW (~BIT(7)) #define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12)) #define RD6281A_OE_VAL_LOW (0) -#define RD6281A_OE_VAL_HIGH (1 << 12) +#define RD6281A_OE_VAL_HIGH BIT(12) /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __RD6281A_H */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h index 8517b99..ba20531 100644 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ b/board/Marvell/sheevaplug/sheevaplug.h @@ -11,15 +11,15 @@ #define SHEEVAPLUG_OE_LOW (~(0)) #define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */ +#define SHEEVAPLUG_OE_VAL_LOW BIT(29) /* USB_PWEN low */ +#define SHEEVAPLUG_OE_VAL_HIGH BIT(17) /* LED pin high */ /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __SHEEVAPLUG_H */ diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 83ab1bc..06bb0e1 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -136,8 +136,8 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ -#define GREEN_LED (1 << 14) -#define ORANGE_LED (1 << 15) +#define GREEN_LED BIT(14) +#define ORANGE_LED BIT(15) #define BOTH_LEDS (GREEN_LED | ORANGE_LED) #define NEITHER_LED 0 diff --git a/board/Seagate/dockstar/dockstar.h b/board/Seagate/dockstar/dockstar.h index ec6fa25..23b476e 100644 --- a/board/Seagate/dockstar/dockstar.h +++ b/board/Seagate/dockstar/dockstar.h @@ -14,15 +14,15 @@ #define DOCKSTAR_OE_LOW (~(0)) #define DOCKSTAR_OE_HIGH (~(0)) -#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */ +#define DOCKSTAR_OE_VAL_LOW BIT(29) /* USB_PWEN low */ +#define DOCKSTAR_OE_VAL_HIGH BIT(17) /* LED pin high */ /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __DOCKSTAR_H */ diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 1f4fb92..57b2be2 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -138,8 +138,8 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ -#define GREEN_LED (1 << 14) -#define ORANGE_LED (1 << 15) +#define GREEN_LED BIT(14) +#define ORANGE_LED BIT(15) #define BOTH_LEDS (GREEN_LED | ORANGE_LED) #define NEITHER_LED 0 diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index ee1681b..daec6f8 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -111,7 +111,7 @@ phys_size_t initdram(int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ @@ -165,8 +165,8 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, /* read digitalboard-version from TMR[2..4] */ val = 0; val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; + val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? BIT(1) : 0; + val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? BIT(2) : 0; *digiboardversion = val; /* @@ -186,8 +186,8 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, /* read fpga-version from TMR[5..7] */ val = 0; val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0; + val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? BIT(1) : 0; + val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? BIT(2) : 0; *fpgaversion = val; if (*fpgaversion == 1) @@ -210,7 +210,7 @@ void spl_board_init(void) #if defined(CONFIG_A4M2K) /* enable CS3 and CS5 (FPGA) */ - setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); + setbits_be32(&mm->ipbi_ws_ctrl, BIT(19) | BIT(21)); #else int digiboardversion; int failsavelevel; @@ -222,15 +222,15 @@ void spl_board_init(void) val = in_be32(&mm->ipbi_ws_ctrl); /* first clear bits 19..21 (CS3...5) */ - val &= ~((1 << 19) | (1 << 20) | (1 << 21)); + val &= ~(BIT(19) | BIT(20) | BIT(21)); if (failsavelevel == 2) { /* FPGA ok */ - val |= (1 << 19) | (1 << 21); + val |= BIT(19) | BIT(21); } if (failsavelevel >= 1) { /* at least digiboard-version ok */ - val |= (1 << 20); + val |= BIT(20); } /* And write new value back to register */ diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c index c5d161b..58be353 100644 --- a/board/a4m072/a4m072.c +++ b/board/a4m072/a4m072.c @@ -108,7 +108,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index ea9575d..e4a9942 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -126,7 +126,7 @@ int board_init(void) #ifdef CONFIG_CMD_NAND afeb9260_nand_hw_init(); #endif - at91_spi0_hw_init((1 << 0) | (1 << 1)); + at91_spi0_hw_init(BIT(0) | BIT(1)); #ifdef CONFIG_MACB afeb9260_macb_hw_init(); #endif diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c index e65befc..c93eca1 100644 --- a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c +++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c @@ -31,7 +31,7 @@ int checkboard(void) #define MSTPSR1 (0xFFC80044) #define MSTPCR1 (0xFFC80034) -#define MSTPSR1_GETHER (1 << 14) +#define MSTPSR1_GETHER BIT(14) /* IPSR3 */ #define ET0_ETXD0 (0x4 << 3) diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h index 7a94d67..266446a 100644 --- a/board/armltd/integrator/integrator-sc.h +++ b/board/armltd/integrator/integrator-sc.h @@ -20,22 +20,22 @@ #define SC_ID_OFFSET 0x00 #define SC_OSC_OFFSET 0x04 /* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ -#define SC_OSC_DIVXY (1 << 8) +#define SC_OSC_DIVXY BIT(8) #define SC_CTRLS_OFFSET 0x08 #define SC_CTRLC_OFFSET 0x0C /* Set bits by writing CTRLS, clear bits by writing CTRLC */ -#define SC_CTRL_SOFTRESET (1 << 0) -#define SC_CTRL_FLASHVPP (1 << 1) -#define SC_CTRL_FLASHWP (1 << 2) -#define SC_CTRL_UART1DTR (1 << 4) -#define SC_CTRL_UART1RTS (1 << 5) -#define SC_CTRL_UART0DTR (1 << 6) -#define SC_CTRL_UART0RTS (1 << 7) +#define SC_CTRL_SOFTRESET BIT(0) +#define SC_CTRL_FLASHVPP BIT(1) +#define SC_CTRL_FLASHWP BIT(2) +#define SC_CTRL_UART1DTR BIT(4) +#define SC_CTRL_UART1RTS BIT(5) +#define SC_CTRL_UART0DTR BIT(6) +#define SC_CTRL_UART0RTS BIT(7) #define SC_DEC_OFFSET 0x10 #define SC_ARB_OFFSET 0x14 #define SC_PCI_OFFSET 0x18 -#define SC_PCI_PCIEN (1 << 0) -#define SC_PCI_PCIBINT_CLR (1 << 1) +#define SC_PCI_PCIEN BIT(0) +#define SC_PCI_PCIBINT_CLR BIT(1) #define SC_LOCK_OFFSET 0x1C #define SC_LBFADDR_OFFSET 0x20 #define SC_LBFCODE_OFFSET 0x24 @@ -60,10 +60,10 @@ #define CP_IDFIELD_OFFSET 0x00 #define CP_FLASHPROG_OFFSET 0x04 -#define CP_FLASHPROG_FLVPPEN (1 << 0) -#define CP_FLASHPROG_FLWREN (1 << 1) -#define CP_FLASHPROG_FLASHSIZE (1 << 2) -#define CP_FLASHPROG_EXTRABANK (1 << 3) +#define CP_FLASHPROG_FLVPPEN BIT(0) +#define CP_FLASHPROG_FLWREN BIT(1) +#define CP_FLASHPROG_FLASHSIZE BIT(2) +#define CP_FLASHPROG_EXTRABANK BIT(3) #define CP_INTREG_OFFSET 0x08 #define CP_DECODE_OFFSET 0x0C diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h index 627b49a..72982ce 100644 --- a/board/armltd/integrator/pci_v3.h +++ b/board/armltd/integrator/pci_v3.h @@ -76,48 +76,48 @@ /* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) +#define V3_COMMAND_M_FBB_EN BIT(9) +#define V3_COMMAND_M_SERR_EN BIT(8) +#define V3_COMMAND_M_PAR_EN BIT(6) +#define V3_COMMAND_M_MASTER_EN BIT(2) +#define V3_COMMAND_M_MEM_EN BIT(1) +#define V3_COMMAND_M_IO_EN BIT(0) /* SYSTEM REGISTER bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) +#define V3_SYSTEM_M_RST_OUT BIT(15) +#define V3_SYSTEM_M_LOCK BIT(14) /* PCI_CFG bits */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) +#define V3_PCI_CFG_M_I2O_EN BIT(15) +#define V3_PCI_CFG_M_IO_REG_DIS BIT(14) +#define V3_PCI_CFG_M_IO_DIS BIT(13) +#define V3_PCI_CFG_M_EN3V BIT(12) +#define V3_PCI_CFG_M_RETRY_EN BIT(10) +#define V3_PCI_CFG_M_AD_LOW1 BIT(9) +#define V3_PCI_CFG_M_AD_LOW0 BIT(8) /* PCI_BASE register bits (PCI -> Local Bus) */ #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_PREFETCH BIT(3) #define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) +#define V3_PCI_BASE_M_IO BIT(0) /* PCI MAP register bits (PCI -> Local bus) */ #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_RD_POST_INH BIT(15) #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) #define V3_PCI_MAP_M_SWAP (3 << 8) #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) +#define V3_PCI_MAP_M_REG_EN BIT(1) +#define V3_PCI_MAP_M_ENABLE BIT(0) #define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_2MB BIT(4) #define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) #define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) #define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) @@ -135,11 +135,11 @@ #define V3_LB_BASE_ADR_BASE 0xfff00000 #define V3_LB_BASE_SWAP (3 << 8) #define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) +#define V3_LB_BASE_PREFETCH BIT(3) +#define V3_LB_BASE_ENABLE BIT(0) #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB BIT(4) #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) @@ -158,10 +158,10 @@ */ #define V3_LB_MAP_MAP_ADR 0xfff0 #define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) +#define V3_LB_MAP_AD_LOW_EN BIT(0) #define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_IO BIT(1) #define V3_LB_MAP_TYPE_MEM (3 << 1) #define V3_LB_MAP_TYPE_CONFIG (5 << 1) #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) @@ -174,7 +174,7 @@ */ #define V3_LB_BASE2_ADR_BASE 0xff00 #define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) +#define V3_LB_BASE2_ENABLE BIT(0) #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c index 0e9c222..87f6a1e 100644 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c @@ -223,25 +223,25 @@ void s_init(void) } #define GPIO_ICCR (0xE60581A0) -#define ICCR_15BIT (1 << 15) /* any time 1 */ -#define IIC0_CONTA (1 << 7) -#define IIC0_CONTB (1 << 6) -#define IIC1_CONTA (1 << 5) -#define IIC1_CONTB (1 << 4) -#define IIC0_PS33E (1 << 1) -#define IIC1_PS33E (1 << 0) +#define ICCR_15BIT BIT(15) /* any time 1 */ +#define IIC0_CONTA BIT(7) +#define IIC0_CONTB BIT(6) +#define IIC1_CONTA BIT(5) +#define IIC1_CONTB BIT(4) +#define IIC0_PS33E BIT(1) +#define IIC1_PS33E BIT(0) #define GPIO_ICCR_DATA \ (ICCR_15BIT | \ IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) #define MSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) -#define I2C0_MSTP116 (1 << 16) +#define TMU0_MSTP125 BIT(25) +#define I2C0_MSTP116 BIT(16) #define MSTPCR3 0xE615013C -#define I2C1_MSTP323 (1 << 23) -#define GETHER_MSTP309 (1 << 9) +#define I2C1_MSTP323 BIT(23) +#define GETHER_MSTP309 BIT(9) #define GPIO_SCIFA1_TXD (0xE60520C4) #define GPIO_SCIFA1_RXD (0xE60520C3) diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 7f14af1..60b656c 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -142,7 +142,7 @@ int board_init(void) at91sam9260ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init((1 << 0) | (1 << 1)); + at91_spi0_hw_init(BIT(0) | BIT(1)); #endif #ifdef CONFIG_MACB at91sam9260ek_macb_hw_init(); diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 5250474..1bbe73f 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -241,7 +241,7 @@ int board_init(void) at91sam9261ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_DRIVER_DM9000 at91sam9261ek_dm9000_hw_init(); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 927adb0..2d7131a 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -97,13 +97,13 @@ static void at91sam9263ek_macb_hw_init(void) * PHY has internal pull-down */ writel(1 << 25, &pio->pioc.pudr); - writel((1 << 25) | (1 <<26), &pio->pioe.pudr); + writel(BIT(25) | (1 <<26), &pio->pioe.pudr); at91_phy_reset(); /* Re-enable pull-up */ writel(1 << 25, &pio->pioc.puer); - writel((1 << 25) | (1 <<26), &pio->pioe.puer); + writel(BIT(25) | (1 <<26), &pio->pioe.puer); at91_macb_hw_init(); } @@ -249,7 +249,7 @@ int board_init(void) #endif #ifdef CONFIG_HAS_DATAFLASH at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */ - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB at91sam9263ek_macb_hw_init(); diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 4289179..9e8dbe0 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -332,10 +332,10 @@ int board_init(void) at91sam9m10g45ek_usb_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); + at91_spi0_hw_initBIT(4); #endif #ifdef CONFIG_MACB at91sam9m10g45ek_macb_hw_init(); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 4f46a03..7a3c96c 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -226,7 +226,7 @@ int board_init(void) #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_LCD @@ -269,7 +269,7 @@ void at91_spl_board_init(void) #elif CONFIG_SYS_USE_NANDFLASH at91sam9n12ek_nand_hw_init(); #elif CONFIG_SYS_USE_SPIFLASH - at91_spi0_hw_init(1 << 4); + at91_spi0_hw_initBIT(4); #endif } diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f995cef..a53ba7e 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -196,7 +196,7 @@ int board_init(void) at91sam9rlek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_LCD at91sam9rlek_lcd_hw_init(); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 114ac5c..ff46421 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -271,7 +271,7 @@ int board_init(void) #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); + at91_spi0_hw_initBIT(4); #endif #ifdef CONFIG_MACB @@ -305,7 +305,7 @@ void at91_spl_board_init(void) #elif CONFIG_SYS_USE_NANDFLASH at91sam9x5ek_nand_hw_init(); #elif CONFIG_SYS_USE_SPIFLASH - at91_spi0_hw_init(1 << 4); + at91_spi0_hw_initBIT(4); #endif } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index cf6ed8b..53ca354 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -249,7 +249,7 @@ int board_init(void) sama5d3xek_mci_hw_init(); #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB if (has_emac()) @@ -378,7 +378,7 @@ void spl_board_init(void) #elif CONFIG_SYS_USE_NANDFLASH sama5d3xek_nand_hw_init(); #elif CONFIG_SYS_USE_SERIALFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif } diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index c2bf145..6103d50 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -70,12 +70,12 @@ * LCD Modes */ #define LQ035_RL (0 << 8) /* Right -> Left Scan */ -#define LQ035_LR (1 << 8) /* Left -> Right Scan */ -#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ +#define LQ035_LR BIT(8) /* Left -> Right Scan */ +#define LQ035_TB BIT(9) /* Top -> Botton Scan */ #define LQ035_BT (0 << 9) /* Botton -> Top Scan */ -#define LQ035_BGR (1 << 11) /* Use BGR format */ +#define LQ035_BGR BIT(11) /* Use BGR format */ #define LQ035_RGB (0 << 11) /* Use RGB format */ -#define LQ035_NORM (1 << 13) /* Reversal */ +#define LQ035_NORM BIT(13) /* Reversal */ #define LQ035_REV (0 << 13) /* Reversal */ #define LQ035_INDEX 0x74 @@ -87,7 +87,7 @@ #define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV) #define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK) -#define LQ035_SHUT (1 << 0) /* Shutdown */ +#define LQ035_SHUT BIT(0) /* Shutdown */ #define LQ035_ON (0 << 0) /* Shutdown */ #ifndef CONFIG_LQ035Q1_LCD_MODE diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c index 32ff7a4..6a53d15 100644 --- a/board/birdland/bav335x/board.c +++ b/board/birdland/bav335x/board.c @@ -343,7 +343,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 95633b0..cbc9a12 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; /* IO Expander pins */ #define IO_EXP_ETH_RESET (0 << 1) -#define IO_EXP_ETH_POWER (1 << 1) +#define IO_EXP_ETH_POWER BIT(1) static void macb_hw_init(void) { diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index 337be43..6aba41f 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -72,7 +72,7 @@ int board_init(void) at91_seriald_hw_init(); tny_a9260_nand_hw_init(); - at91_spi0_hw_init(1 << 5); + at91_spi0_hw_initBIT(5); return 0; } diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index 266e950..5854ed1 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -119,7 +119,7 @@ int board_init(void) usb_a9263_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB usb_a9263_macb_hw_init(); diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index 15c934d..0ed34a4 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } @@ -131,7 +131,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { + if (dramsize2 < BIT(20)) { dramsize2 = 0; } diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h index 108d343..0d38735 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.h +++ b/board/cloudengines/pogo_e02/pogo_e02.h @@ -16,7 +16,7 @@ /* GPIO configuration */ #define POGO_E02_OE_LOW (~(0)) #define POGO_E02_OE_HIGH (~(0)) -#define POGO_E02_OE_VAL_LOW (1 << 29) +#define POGO_E02_OE_VAL_LOW BIT(29) #define POGO_E02_OE_VAL_HIGH 0 /* PHY related */ @@ -24,7 +24,7 @@ #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __POGO_E02_H */ diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index 1075cc4..8eb3341 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -16,16 +16,16 @@ #ifndef GPIO_PIN_1 #define GPIO_PIN_1 GPIO_PF4 #endif -#define GPIO_MASK_1 (1 << 21) +#define GPIO_MASK_1 BIT(21) #ifndef GPIO_PIN_2 #define GPIO_MASK_2 (0) #else -#define GPIO_MASK_2 (1 << 22) +#define GPIO_MASK_2 BIT(22) #endif #ifndef GPIO_PIN_3 #define GPIO_MASK_3 (0) #else -#define GPIO_MASK_3 (1 << 23) +#define GPIO_MASK_3 BIT(23) #endif #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3) diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 5276907..c891698 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -124,7 +124,7 @@ phys_size_t initdram(int board_type) dramsize = test2; /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 9c40ad7..7a9fe2a 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -176,7 +176,7 @@ static int do_rs232_test(char * const argv[]) /* check TXD <-> RXD loop */ /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 4); + gpio->simple_dvo |= BIT(4); /* wait some time before requesting status */ udelay(10); @@ -189,7 +189,7 @@ static int do_rs232_test(char * const argv[]) } /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 4); + gpio->simple_dvo &= ~BIT(4); /* wait some time before requesting status */ udelay(10); @@ -203,7 +203,7 @@ static int do_rs232_test(char * const argv[]) /* check RTS <-> CTS loop */ /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 6); + gpio->simple_dvo |= BIT(6); /* wait some time before requesting status */ udelay(10); @@ -216,7 +216,7 @@ static int do_rs232_test(char * const argv[]) } /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 6); + gpio->simple_dvo &= ~BIT(6); /* wait some time before requesting status */ udelay(10); @@ -242,7 +242,7 @@ static int do_rs232_test(char * const argv[]) /* check TXD <-> RXD loop */ /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); + gpio->simple_dvo |= BIT(8); /* wait some time before requesting status */ udelay(10); @@ -255,7 +255,7 @@ static int do_rs232_test(char * const argv[]) } /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); + gpio->simple_dvo &= ~BIT(8); /* wait some time before requesting status */ udelay(10); @@ -269,7 +269,7 @@ static int do_rs232_test(char * const argv[]) /* check RTS <-> CTS loop */ /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); + gpio->simple_dvo |= BIT(10); /* wait some time before requesting status */ udelay(10); @@ -282,7 +282,7 @@ static int do_rs232_test(char * const argv[]) } /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); + gpio->simple_dvo &= ~BIT(10); /* wait some time before requesting status */ udelay(10); @@ -311,7 +311,7 @@ static int do_rs232_test(char * const argv[]) /* check TXD <-> RXD loop */ /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 28); + gpio->simple_dvo |= BIT(28); /* wait some time before requesting status */ udelay(10); @@ -326,7 +326,7 @@ static int do_rs232_test(char * const argv[]) } /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 28); + gpio->simple_dvo &= ~BIT(28); /* wait some time before requesting status */ udelay(10); @@ -342,7 +342,7 @@ static int do_rs232_test(char * const argv[]) /* check RTS <-> CTS loop */ /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 29); + gpio->simple_dvo |= BIT(29); /* wait some time before requesting status */ udelay(10); @@ -357,7 +357,7 @@ static int do_rs232_test(char * const argv[]) } /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 29); + gpio->simple_dvo &= ~BIT(29); /* wait some time before requesting status */ udelay(10); diff --git a/board/cmi/flash.c b/board/cmi/flash.c index d9986f9..896263b 100644 --- a/board/cmi/flash.c +++ b/board/cmi/flash.c @@ -164,7 +164,7 @@ void flash_print_info (flash_info_t *info) break; } - if (info->size >= (1 << 20)) { + if (info->size >= BIT(20)) { i = 20; } else { i = 10; diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 9d4c41b..c4760db 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -53,7 +53,7 @@ static void setup_net_chip(void); RDACCESSTIME(6) | \ WRCYCLETIME(0x1D) | \ RDCYCLETIME(0x1D)) -#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \ +#define NET_LAN9220_GPMC_CONFIG6 (BIT(31) | \ WRACCESSTIME(0x1D) | \ WRDATAONADMUXBUS(3)) diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 7a1bbaf..52b3106 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -269,7 +269,7 @@ static int cm_fx6_setup_i2c(void) { return 0; } PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define MX6_USBNC_BASEADDR 0x2184800 -#define USBNC_USB_H1_PWR_POL (1 << 9) +#define USBNC_USB_H1_PWR_POL BIT(9) static int cm_fx6_setup_usb_host(void) { diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 428aee6..8285262 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -64,7 +64,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c index 61707f5..34e0819c 100644 --- a/board/compulab/common/omap3_display.c +++ b/board/compulab/common/omap3_display.c @@ -54,7 +54,7 @@ static const struct panel_config preset_dvi_640X480 = { .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 12 | (1 << 16), + .divisor = 12 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -66,7 +66,7 @@ static const struct panel_config preset_dvi_800X600 = { .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 8 | (1 << 16), + .divisor = 8 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -78,7 +78,7 @@ static const struct panel_config preset_dvi_1024X768 = { .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 5 | (1 << 16), + .divisor = 5 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -90,7 +90,7 @@ static const struct panel_config preset_dvi_1152X864 = { .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 4 | (1 << 16), + .divisor = 4 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -102,7 +102,7 @@ static const struct panel_config preset_dvi_1280X960 = { .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 3 | (1 << 16), + .divisor = 3 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -114,7 +114,7 @@ static const struct panel_config preset_dvi_1280X1024 = { .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, - .divisor = 3 | (1 << 16), + .divisor = 3 | BIT(16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -126,7 +126,7 @@ static const struct panel_config preset_dataimage_480X800 = { .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2), .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3), .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF, - .divisor = 10 | (1 << 10), + .divisor = 10 | BIT(10), .data_lines = LCD_INTERFACE_18_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -252,7 +252,7 @@ static int parse_pixclock(char *pixclock) if (divisor <= 1) divisor = 2; - panel_cfg.divisor = divisor | (1 << 16); + panel_cfg.divisor = divisor | BIT(16); if (pixclock[0] != '\0') { printf("LCD: invalid value for pixclock:%s\n", pixclk_start); return -1; diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h index 0167111..826684b 100644 --- a/board/d-link/dns325/dns325.h +++ b/board/d-link/dns325/dns325.h @@ -26,7 +26,7 @@ /* PHY related */ #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __DNS325_H */ diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S index 8887023..76ff1c4 100644 --- a/board/davedenx/qong/lowlevel_init.S +++ b/board/davedenx/qong/lowlevel_init.S @@ -60,36 +60,36 @@ /* SDCLK */ ldr r1, =IOMUXC_SW_PAD_CTL(0x2b) ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) + bic r0, r0, #BIT(12) str r0, [r1, #0x6C] /* CAS */ ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x70] /* RAS */ ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) + bic r0, r0, #BIT(2) str r0, [r1, #0x74] /* CS2 (CSD0) */ ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x7C] /* DQM3 */ ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x84] /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ pad_loop: ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) + bic r0, r0, #BIT(22) + bic r0, r0, #BIT(12) + bic r0, r0, #BIT(2) str r0, [r1, #0x88] add r1, r1, #4 subs r2, r2, #0x1 @@ -174,18 +174,18 @@ UPCTL_PARAM_240: .equ ESDCFG0_128MB, \ (0 << 21) + /* tXP */ \ - (1 << 20) + /* tWTR */ \ + BIT(20) + /* tWTR */ \ (2 << 18) + /* tRP */ \ - (1 << 16) + /* tMRD */ \ + BIT(16) + /* tMRD */ \ (0 << 15) + /* tWR */ \ (5 << 12) + /* tRAS */ \ - (1 << 10) + /* tRRD */ \ + BIT(10) + /* tRRD */ \ (3 << 8) + /* tCAS */ \ (2 << 4) + /* tRCD */ \ (0x0F << 0) /* tRC */ .equ ESDCTL0_128MB, \ - (1 << 31) + /* enable */ \ + BIT(31) + /* enable */ \ (0 << 28) + /* mode */ \ (0 << 27) + /* supervisor protect */ \ (2 << 24) + /* 13 rows */ \ @@ -194,23 +194,23 @@ UPCTL_PARAM_240: (3 << 13) + /* 7.81us (64ms/8192) */ \ (0 << 10) + /* power down timer */ \ (0 << 8) + /* full page */ \ - (1 << 7) + /* burst length */ \ + BIT(7) + /* burst length */ \ (0 << 0) /* precharge timer */ .equ ESDCFG0_256MB, \ (3 << 21) + /* tXP */ \ (0 << 20) + /* tWTR */ \ (2 << 18) + /* tRP */ \ - (1 << 16) + /* tMRD */ \ + BIT(16) + /* tMRD */ \ (0 << 15) + /* tWR */ \ (5 << 12) + /* tRAS */ \ - (1 << 10) + /* tRRD */ \ + BIT(10) + /* tRRD */ \ (3 << 8) + /* tCAS */ \ (2 << 4) + /* tRCD */ \ (7 << 0) /* tRC */ .equ ESDCTL0_256MB, \ - (1 << 31) + \ + BIT(31) + \ (0 << 28) + \ (0 << 27) + \ (3 << 24) + /* 14 rows */ \ @@ -219,5 +219,5 @@ UPCTL_PARAM_240: (4 << 13) + /* 3.91us (64ms/16384) */ \ (0 << 10) + \ (0 << 8) + \ - (1 << 7) + \ + BIT(7) + \ (0 << 0) diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h index 2a619f7..b73b1dd 100644 --- a/board/davedenx/qong/qong_fpga.h +++ b/board/davedenx/qong/qong_fpga.h @@ -10,7 +10,7 @@ #define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE #define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000) -#define QONG_FPGA_PERIPH_SIZE (1 << 24) +#define QONG_FPGA_PERIPH_SIZE BIT(24) #define QONG_FPGA_TCK_PIN 26 #define QONG_FPGA_TMS_PIN 25 diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b82385a..836b38d 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -454,7 +454,7 @@ int rmii_hw_init(void) } buf[0] &= 0x1f; - buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); + buf[0] |= (0 << 7) | BIT(6) | BIT(5); if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x write FAILED!!!\n", CONFIG_SYS_I2C_EXPANDER_ADDR); diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 53902f9..3d26152 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -35,35 +35,35 @@ int board_init(void) writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN); /* set GIO 9 input */ - writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir); + writel((readl(&gpio01_base->dir) | BIT(9)), &gpio01_base->dir); /* Both edge trigger GIO 9 */ - writel((readl(&gpio01_base->set_rising) | (1 << 9)), + writel((readl(&gpio01_base->set_rising) | BIT(9)), &gpio01_base->set_rising); - writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir); + writel((readl(&gpio01_base->dir) & ~BIT(5)), &gpio01_base->dir); /* output low */ - writel((readl(&gpio01_base->set_data) & ~(1 << 5)), + writel((readl(&gpio01_base->set_data) & ~BIT(5)), &gpio01_base->set_data); /* set GIO 10 output */ - writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir); + writel((readl(&gpio01_base->dir) & ~BIT(10)), &gpio01_base->dir); /* output high */ - writel((readl(&gpio01_base->set_data) | (1 << 10)), + writel((readl(&gpio01_base->set_data) | BIT(10)), &gpio01_base->set_data); /* set GIO 32 output */ - writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir); + writel((readl(&gpio23_base->dir) & ~BIT(0)), &gpio23_base->dir); /* output High */ - writel((readl(&gpio23_base->set_data) | (1 << 0)), + writel((readl(&gpio23_base->set_data) | BIT(0)), &gpio23_base->set_data); /* Enable UART1 MUX Lines */ writel((readl(PINMUX0) & ~3), PINMUX0); - writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir); - writel((readl(&gpio67_base->set_data) | (1 << 6)), + writel((readl(&gpio67_base->dir) & ~BIT(6)), &gpio67_base->dir); + writel((readl(&gpio67_base->set_data) | BIT(6)), &gpio67_base->set_data); return 0; diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 24bec56..dde4e46 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -39,18 +39,18 @@ int board_eth_init(bd_t *bis) writel((readl(PINMUX3) | 0x1affff), PINMUX3); /* Configure GPIO20 as output */ - writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir); + writel((readl(&gpio1_base->dir) & ~BIT(20)), &gpio1_base->dir); /* Toggle GPIO 20 */ for (i = 0; i < 20; i++) { /* GPIO 20 low */ - writel((readl(&gpio1_base->out_data) & ~(1 << 20)), + writel((readl(&gpio1_base->out_data) & ~BIT(20)), &gpio1_base->out_data); udelay(1000); /* GPIO 20 high */ - writel((readl(&gpio1_base->out_data) | (1 << 20)), + writel((readl(&gpio1_base->out_data) | BIT(20)), &gpio1_base->out_data); } diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index f5c3258..5c48391 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -67,7 +67,7 @@ static void nand_sonata_select_chip(struct mtd_info *mtd, int chip) { #define GPIO_SET_DATA01 0x01c67018 #define GPIO_CLR_DATA01 0x01c6701c -#define GPIO_NAND_WP (1 << 4) +#define GPIO_NAND_WP BIT(4) #ifdef SONATA_BOARD_GPIOWP if (chip < 0) { REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 67d3984..0e1f38c 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -166,7 +166,7 @@ int board_init(void) ethernut5_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif return 0; } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index 091652b..93f764b 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -70,7 +70,7 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - if (size_b1 < (1 << 20)) { + if (size_b1 < BIT(20)) { /* minimum CS size on PPC405GP is 1MB !!! */ size_b1 = 1 << 20; } @@ -87,7 +87,7 @@ unsigned long flash_init (void) } if (size_b0) { - if (size_b0 < (1 << 20)) { + if (size_b0 < BIT(20)) { /* minimum CS size on PPC405GP is 1MB !!! */ size_b0 = 1 << 20; } diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index c5994e0..d6344b7 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -256,7 +256,7 @@ int board_init(void) meesc_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB meesc_macb_hw_init(); diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 4751d0a..0037fe5 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -354,7 +354,7 @@ int board_init(void) otc570_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB otc570_macb_hw_init(); diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h index 84e0b1f..1fde75e 100644 --- a/board/esd/pmc440/pmc440.h +++ b/board/esd/pmc440/pmc440.h @@ -50,8 +50,8 @@ struct pmc440_fifo_s { }; /* fifo ctrl register */ -#define FIFO_IE (1 << 15) -#define FIFO_OVERFLOW (1 << 10) +#define FIFO_IE BIT(15) +#define FIFO_OVERFLOW BIT(10) #define FIFO_EMPTY (1 << 9) #define FIFO_FULL (1 << 8) #define FIFO_LEVEL_MASK 0x000000ff @@ -80,12 +80,12 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define CTRL_HOST_IE (1 << 8) /* outputs */ -#define RESET_EN (1 << 31) -#define CLOCK_EN (1 << 30) -#define RESET_OUT (1 << 19) -#define CLOCK_OUT (1 << 22) -#define RESET_OUT (1 << 19) -#define IRIGB_R_OUT (1 << 14) +#define RESET_EN BIT(31) +#define CLOCK_EN BIT(30) +#define RESET_OUT BIT(19) +#define CLOCK_OUT BIT(22) +#define RESET_OUT BIT(19) +#define IRIGB_R_OUT BIT(14) /* status register */ #define STATUS_VERSION_SHIFT 24 @@ -93,15 +93,15 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define STATUS_HWREV_SHIFT 20 #define STATUS_HWREV_MASK 0x00f00000 -#define STATUS_CAN_ISF (1 << 11) -#define STATUS_CSTM_ISF (1 << 10) +#define STATUS_CAN_ISF BIT(11) +#define STATUS_CSTM_ISF BIT(10) #define STATUS_FIFO_ISF (1 << 9) #define STATUS_HOST_ISF (1 << 8) /* inputs */ -#define RESET_IN (1 << 0) -#define CLOCK_IN (1 << 1) -#define IRIGB_R_IN (1 << 5) +#define RESET_IN BIT(0) +#define CLOCK_IN BIT(1) +#define IRIGB_R_IN BIT(5) /* hostctrl register */ #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c index df758ee..5d12003 100644 --- a/board/esg/ima3-mx53/ima3-mx53.c +++ b/board/esg/ima3-mx53/ima3-mx53.c @@ -193,7 +193,7 @@ void reset_phy(void) miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); - reg |= (1 << 5); + reg |= BIT(5); miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); } #endif diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c index 2da627e..a6e3ca0 100644 --- a/board/freescale/common/dcu_sii9022a.c +++ b/board/freescale/common/dcu_sii9022a.c @@ -31,9 +31,9 @@ #define TPI_RW_ACCESS_REG 0xBE #define TPI_TRANS_MODE_REG 0xC7 -#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6) -#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5) -#define TPI_INBUS_RISING_EDGE (1 << 4) +#define TPI_INBUS_CLOCK_RATIO_1 BIT(6) +#define TPI_INBUS_FULL_PIXEL_WIDE BIT(5) +#define TPI_INBUS_RISING_EDGE BIT(4) #define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6) #define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2) #define TPI_INPUT_CLR_RGB (0 << 0) @@ -42,20 +42,20 @@ #define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0) #define TPI_SYS_TMDS_OUTPUT (0 << 4) #define TPI_SYS_AV_NORAML (0 << 3) -#define TPI_SYS_AV_MUTE (1 << 3) +#define TPI_SYS_AV_MUTE BIT(3) #define TPI_SYS_DVI_MODE (0 << 0) -#define TPI_SYS_HDMI_MODE (1 << 0) +#define TPI_SYS_HDMI_MODE BIT(0) #define TPI_PWR_STAT_MASK (3 << 0) #define TPI_PWR_STAT_D0 (0 << 0) #define TPI_AUDIO_PASS_BASIC (0 << 0) #define TPI_AUDIO_INTF_I2S (2 << 6) #define TPI_AUDIO_INTF_NORMAL (0 << 4) -#define TPI_AUDIO_TYPE_PCM (1 << 0) -#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6) +#define TPI_AUDIO_TYPE_PCM BIT(0) +#define TPI_AUDIO_SAMP_SIZE_16BIT BIT(6) #define TPI_AUDIO_SAMP_FREQ_44K (2 << 3) #define TPI_SET_PAGE_SII9022A 0x01 #define TPI_SET_OFFSET_SII9022A 0x82 -#define TPI_RW_EN_SRC_TERMIN (1 << 0) +#define TPI_RW_EN_SRC_TERMIN BIT(0) #define TPI_TRANS_MODE_ENABLE (0 << 7) /* Programming of Silicon SIi9022a HDMI Transmitter */ diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h index c26c542..888c821 100644 --- a/board/freescale/common/sleep.h +++ b/board/freescale/common/sleep.h @@ -7,7 +7,7 @@ #ifndef __SLEEP_H #define __SLEEP_H -#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DCFG_CCSR_CRSTSR_WDRFR BIT(3) #define DDR_BUFF_LEN 128 /* determine if it is a wakeup from deep sleep */ diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S index fcb5549..b081536 100644 --- a/board/freescale/mx31ads/lowlevel_init.S +++ b/board/freescale/mx31ads/lowlevel_init.S @@ -106,7 +106,7 @@ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[6] = IPU1 on priority list BIT(6) = 0x00000040 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 * ------------ * 0x00000040 @@ -125,36 +125,36 @@ /* SDCLK */ ldr r1, =0x43FAC200 ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) + bic r0, r0, #BIT(12) str r0, [r1, #0x6C] /* CAS */ ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x70] /* RAS */ ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) + bic r0, r0, #BIT(2) str r0, [r1, #0x74] /* CS2 (CSD0) */ ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x7C] /* DQM3 */ ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) + bic r0, r0, #BIT(22) str r0, [r1, #0x84] /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ pad_loop: ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) + bic r0, r0, #BIT(22) + bic r0, r0, #BIT(12) + bic r0, r0, #BIT(2) str r0, [r1, #0x88] add r1, r1, #4 subs r2, r2, #0x1 diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 98ccdb7..bc667cd 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -216,7 +216,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_USB_EHCI_MX6 #define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) +#define UCTRL_PWR_POL BIT(9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index bb2dd96..3739712 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -540,7 +540,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_USB_EHCI_MX6 #define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) +#define UCTRL_PWR_POL BIT(9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7c18c90..d561174 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -285,7 +285,7 @@ static int setup_fec(void) #ifdef CONFIG_USB_EHCI_MX6 #define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) +#define UCTRL_PWR_POL BIT(9) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OTG1 */ diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 2ff960e..fcc2fdb 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -220,7 +220,7 @@ int power_init_board(void) #ifdef CONFIG_USB_EHCI_MX6 #define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) +#define UCTRL_PWR_POL BIT(9) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OGT1 */ diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 3a075c4..c90f087 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -217,7 +217,7 @@ int verify_gbit_phy(char *bus, unsigned char addr) /* verify SGMII link status */ if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) goto err_out; - if (!(value & (1 << 10))) + if (!(value & BIT(10))) return -2; return 0; @@ -288,7 +288,7 @@ int last_stage_init(void) for (k = 0; k < 32; ++k) { u16 status; FPGA_GET_REG(fpga, ch[k].status_int, &status); - if (!(status & (1 << 4))) { + if (!(status & BIT(4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 1d6eb7b..e2e9b62 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -23,7 +23,7 @@ static int ihs_mdio_idle(struct mii_dev *bus) udelay(100); if (ctr++ > 10) return -1; - } while (!(val & (1 << 12))); + } while (!(val & BIT(12))); return 0; } @@ -63,7 +63,7 @@ static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr, FPGA_SET_REG(info->fpga, mdio.address_data, value); FPGA_SET_REG(info->fpga, mdio.control, - ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); + ((addr & 0x1f) << 5) | (regnum & 0x1f) | BIT(10)); return 0; } diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c index 9f230c9..b0eb34b 100644 --- a/board/gdsys/common/mclink.c +++ b/board/gdsys/common/mclink.c @@ -33,13 +33,13 @@ int mclink_probe(void) FPGA_GET_REG(k, mc_status, &mc_status); - if (!(mc_status & (1 << 15))) + if (!(mc_status & BIT(15))) break; FPGA_SET_REG(k, mc_control, 0x8000); FPGA_GET_REG(k, mc_status, &mc_status); - while (!(mc_status & (1 << 14))) { + while (!(mc_status & BIT(14))) { udelay(100); if (ctr++ > 500) { timeout = 1; @@ -103,7 +103,7 @@ int mclink_receive(u8 slave, u16 addr, u16 *data) /* send read request */ FPGA_SET_REG(0, mc_tx_address, addr); FPGA_SET_REG(0, mc_tx_cmd, - ((slave & 0x03) << 14) | (1 << 12) | (1 << 0)); + ((slave & 0x03) << 14) | BIT(12) | BIT(0)); FPGA_SET_REG(0, mc_control, 0x8001); diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 55ecdf1..052479a 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -229,7 +229,7 @@ static void ics8n3qv01_set(unsigned int fout) i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18); reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f; - reg20 |= mint & (1 << 5); + reg20 |= mint & BIT(5); i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20); } #endif diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index beb2fac..1f4a0ae 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -142,7 +142,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 72932ca..deb111c 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -66,12 +66,12 @@ static void gpio_configure(void) #define GPIOKEY_COL2_BITMASK 0x08000000 /* the logical presentation of pressed keys */ -#define GPIOKEY_BIT_FNLEFT (1 << 5) -#define GPIOKEY_BIT_FNRIGHT (1 << 4) -#define GPIOKEY_BIT_DIRUP (1 << 3) -#define GPIOKEY_BIT_DIRLEFT (1 << 2) -#define GPIOKEY_BIT_DIRRIGHT (1 << 1) -#define GPIOKEY_BIT_DIRDOWN (1 << 0) +#define GPIOKEY_BIT_FNLEFT BIT(5) +#define GPIOKEY_BIT_FNRIGHT BIT(4) +#define GPIOKEY_BIT_DIRUP BIT(3) +#define GPIOKEY_BIT_DIRLEFT BIT(2) +#define GPIOKEY_BIT_DIRRIGHT BIT(1) +#define GPIOKEY_BIT_DIRDOWN BIT(0) /* the hotkey combination which starts recovery */ #define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c index ca09767..3e1a741 100644 --- a/board/ifm/o2dnt2/o2dnt2.c +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -104,7 +104,7 @@ phys_size_t initdram(int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ @@ -138,7 +138,7 @@ phys_size_t initdram(int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) + if (dramsize2 < BIT(20)) dramsize2 = 0; /* set SDRAM CS1 size according to the amount of RAM found */ @@ -239,9 +239,9 @@ int board_early_init_r(void) */ clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */ /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); + clrbits_be32((void *)MPC5XXX_ADDECR, BIT(25)); /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); + setbits_be32((void *)MPC5XXX_ADDECR, BIT(16)); return 0; } diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c index 91b4116..2562201 100644 --- a/board/in-circuit/grasshopper/grasshopper.c +++ b/board/in-circuit/grasshopper/grasshopper.c @@ -59,7 +59,7 @@ int board_early_init_f(void) portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) /* set PHY reset and pwrdown to low */ - portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30), + portmux_select_gpio(PORTMUX_PORT_B, BIT(29) | BIT(30), PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW); udelay(100); /* release PHYs reset */ diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 0a32f0e..267ccef 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -115,7 +115,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 4ab7160..ca8f1f9 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -108,7 +108,7 @@ phys_size_t initdram(int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ @@ -128,7 +128,7 @@ phys_size_t initdram(int board_type) dramsize2 = test1; /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) + if (dramsize2 < BIT(20)) dramsize2 = 0; /* set SDRAM CS1 size according to the amount of RAM found */ @@ -259,11 +259,11 @@ int board_early_init_r(void) * flash. */ /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); + clrbits_be32((void *)MPC5XXX_ADDECR, BIT(25)); /* enable CS1 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17)); + setbits_be32((void *)MPC5XXX_ADDECR, BIT(17)); /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); + setbits_be32((void *)MPC5XXX_ADDECR, BIT(16)); #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) /* Low level USB init, required for proper kernel operation */ @@ -341,13 +341,13 @@ void init_ide_reset(void) debug ("init_ide_reset\n"); /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, BIT(25)); /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, BIT(25)); /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, BIT(25)); /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, BIT(25)); } @@ -356,24 +356,24 @@ void ide_set_reset(int idereset) debug ("ide_reset(%d)\n", idereset); /* set gpio output value to 0 */ - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, BIT(25)); /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, BIT(25)); /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, BIT(25)); /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, BIT(25)); udelay(10000); /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, BIT(25)); /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, BIT(25)); /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, BIT(25)); /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, BIT(25)); } #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CMD_IDE */ diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h index 6107a99..1e00b91 100644 --- a/board/iomega/iconnect/iconnect.h +++ b/board/iomega/iconnect/iconnect.h @@ -9,17 +9,17 @@ #ifndef __ICONNECT_H #define __ICONNECT_H -#define ICONNECT_OE_LOW (~(1 << 7)) -#define ICONNECT_OE_HIGH (~(1 << 10)) +#define ICONNECT_OE_LOW (~BIT(7)) +#define ICONNECT_OE_HIGH (~BIT(10)) #define ICONNECT_OE_VAL_LOW (0) -#define ICONNECT_OE_VAL_HIGH (1 << 10) +#define ICONNECT_OE_VAL_HIGH BIT(10) /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) #endif /* __ICONNECT_H */ diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c index 2078f53..853de1c 100644 --- a/board/ipek01/ipek01.c +++ b/board/ipek01/ipek01.c @@ -114,7 +114,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 5fea7ff..71215ca 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -134,7 +134,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c index ff6dbf0..655fc632 100644 --- a/board/jornada/jornada.c +++ b/board/jornada/jornada.c @@ -27,8 +27,8 @@ int board_init(void) * that would have to be implemented in the * flash init function, which isnt possible yet. */ - PPSR |= (1 << 7); - PPDR |= (1 << 7); + PPSR |= BIT(7); + PPDR |= BIT(7); return 0; } diff --git a/board/jornada/setup.S b/board/jornada/setup.S index da9f006..3fc1ebd 100644 --- a/board/jornada/setup.S +++ b/board/jornada/setup.S @@ -42,16 +42,16 @@ #define MDREFR_TRASR(n_) (n_ & (0x0000000f)) #define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_K0DB2 BIT(18) +#define MDREFR_K1DB2 BIT(22) +#define MDREFR_K2DB2 BIT(26) -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K0RUN BIT(17) +#define MDREFR_K1RUN BIT(21) +#define MDREFR_K2RUN BIT(25) -#define MDREFR_SLFRSH (1 << 31) -#define MDREFR_E1PIN (1 << 20) +#define MDREFR_SLFRSH BIT(31) +#define MDREFR_E1PIN BIT(20) #define PSSR 0x04 #define PSSR_DH 0x00000008 diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 8856393..049b3fd 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -114,7 +114,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } @@ -144,7 +144,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { + if (dramsize2 < BIT(20)) { dramsize2 = 0; } @@ -228,8 +228,8 @@ void flash_afterinit(ulong size) *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ + *(vu_long *)MPC5XXX_ADDECR &= ~BIT(25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= BIT(16); /* enable CS0 */ } int update_flash_size (int flash_size) diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index 35546d2..d461f9e 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -106,8 +106,8 @@ int board_init(void) #define MV88E1116_MAC_CTRL2_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) static void mv_phy_88e1118_init(char *name) { diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 11b80b4..e8c298b 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -59,10 +59,10 @@ * reset SDRAM controller * then wait for initialization to complete */ - ldr r1, =(1 << 1) + ldr r1, =BIT(1) str r1, [r0, #0x10] 1: ldr r3, [r0, #0x10] - tst r3, #(1 << 31) + tst r3, #BIT(31) beq 1b ldr r1, =0x95728 diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index ea36fa4..4d9f2f2 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -19,15 +19,15 @@ DECLARE_GLOBAL_DATA_PTR; #define CS0WCR_D (0x55062C42) #define CS4WCR_D (0x1e071dc3) -#define CMNCR_BROMMD0 (1 << 21) -#define CMNCR_BROMMD1 (1 << 22) +#define CMNCR_BROMMD0 BIT(21) +#define CMNCR_BROMMD1 BIT(22) #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) #define VCLKCR1_D (0x27) -#define SMSTPCR1_CMT0 (1 << 24) -#define SMSTPCR1_I2C0 (1 << 16) -#define SMSTPCR3_USB (1 << 22) -#define SMSTPCR3_I2C1 (1 << 23) +#define SMSTPCR1_CMT0 BIT(24) +#define SMSTPCR1_I2C0 BIT(16) +#define SMSTPCR3_USB BIT(22) +#define SMSTPCR3_I2C1 BIT(23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -146,13 +146,13 @@ void s_init(void) writew(0xA507, &rwdt->rwtcsra0); /* Secure control register Init */ - #define LIFEC_SEC_SRC_BIT (1 << 15) + #define LIFEC_SEC_SRC_BIT BIT(15) writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); - clrbits_le32(&cpg->smstpcr3, (1 << 15)); - clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); - clrbits_le32(&cpg->smstpcr2, (1 << 18)); - clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); + clrbits_le32(&cpg->smstpcr3, BIT(15)); + clrbits_le32(&cpg_srcr->srcr3, BIT(15)); + clrbits_le32(&cpg->smstpcr2, BIT(18)); + clrbits_le32(&cpg_srcr->srcr2, BIT(18)); writel(0x0, &cpg->pllecr); cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); @@ -164,9 +164,9 @@ void s_init(void) cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); writel(0xB, &cpg->flckcr); - clrbits_le32(&cpg->smstpcr0, (1 << 1)); + clrbits_le32(&cpg->smstpcr0, BIT(1)); - clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); + clrbits_le32(&cpg_srcr->srcr0, BIT(1)); writel(0x0514, &hpb_bscr->smgpiotime); writel(0x0514, &hpb_bscr->smcmt2time); writel(0x0514, &hpb_bscr->smcpgtime); @@ -232,7 +232,7 @@ void s_init(void) writel(0x00000000, &cpg->smstpcr2); writel(0x00040000, &cpg_srcr->srcr2); - clrbits_le32(&cpg->pllecr, (1 << 3)); + clrbits_le32(&cpg->pllecr, BIT(3)); cmp_loop(&cpg->pllecr, 0x00000800, 0x0); writel(0x00000001, &hpb->hpbctrl6); @@ -242,7 +242,7 @@ void s_init(void) cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); writel(0x1d000000, &cpg->pll3cr); - setbits_le32(&cpg->pllecr, (1 << 3)); + setbits_le32(&cpg->pllecr, BIT(3)); cmp_loop(&cpg->pllecr, 0x800, 0x800); /* SBSC1 Init*/ @@ -370,5 +370,5 @@ int board_eth_init(bd_t *bis) void reset_cpu(ulong addr) { /* Soft Power On Reset */ - writel((1 << 31), RESCNT2); + writel(BIT(31), RESCNT2); } diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c index 3bb1b71..640d88a 100644 --- a/board/kosagi/novena/video.c +++ b/board/kosagi/novena/video.c @@ -38,20 +38,20 @@ #define IT6251_DEVICE_ID_LOW 0x02 #define IT6251_DEVICE_ID_HIGH 0x03 #define IT6251_SYSTEM_STATUS 0x0d -#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0) -#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1) -#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2) -#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3) -#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4) -#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5) -#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6) +#define IT6251_SYSTEM_STATUS_RINTSTATUS BIT(0) +#define IT6251_SYSTEM_STATUS_RHPDSTATUS BIT(1) +#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE BIT(2) +#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK BIT(3) +#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK BIT(4) +#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK BIT(5) +#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK BIT(6) #define IT6251_REF_STATE 0x0e -#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0) -#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1) -#define IT6251_REF_STATE_CR_PATTERN (1 << 2) -#define IT6251_REF_STATE_EQ_PATTERN (1 << 3) -#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4) -#define IT6251_REF_STATE_MUTED (1 << 5) +#define IT6251_REF_STATE_MAIN_LINK_DISABLED BIT(0) +#define IT6251_REF_STATE_AUX_CHANNEL_READ BIT(1) +#define IT6251_REF_STATE_CR_PATTERN BIT(2) +#define IT6251_REF_STATE_EQ_PATTERN BIT(3) +#define IT6251_REF_STATE_NORMAL_OPERATION BIT(4) +#define IT6251_REF_STATE_MUTED BIT(5) #define IT6251_REG_PCLK_CNT_LOW 0x57 #define IT6251_REG_PCLK_CNT_HIGH 0x58 diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 24be6ea..439b503 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AM3517_IP_SW_RESET 0x48002598 -#define CPGMACSS_SW_RST (1 << 1) +#define CPGMACSS_SW_RST BIT(1) /* * Routine: board_init diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 07b07a0..b042d3c 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -44,7 +44,7 @@ int board_init(void) * set in FMCR NF_FMS Bit(5) to 1 * (NAND Flash with 2 Kbyte page size) */ - writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr); + writel(readl(&sc_regs->fmcr) | BIT(5), &sc_regs->fmcr); #endif return 0; } diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h index efa36cf..2fc5559 100644 --- a/board/micronas/vct/ebi.h +++ b/board/micronas/vct/ebi.h @@ -15,10 +15,10 @@ #define EXT_DEVICE_CHANNEL_2 (0x20000000) #define EXT_DEVICE_CHANNEL_1 (0x10000000) #define EXT_CPU_ACCESS_ACTIVE (0x00000001) -#define EXT_DMA_ACCESS_ACTIVE (1 << 14) +#define EXT_DMA_ACCESS_ACTIVE BIT(14) #define EXT_CPU_IORDY_SL (0x00000001) -#define EBI_CPU_WRITE (1 << 31) +#define EBI_CPU_WRITE BIT(31) #define EBI_CPU_ID_SHIFT (28) #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) @@ -39,13 +39,13 @@ /* various bits in configuration register EBI_DEV[01]_CONFIG1 */ #define EBI_EXTERNAL_DATA_8 (1 << 8) -#define EBI_EXT_ADDR_SHIFT (1 << 22) +#define EBI_EXT_ADDR_SHIFT BIT(22) #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT #define EBI_CHIP_SELECT_1 0x2 #define EBI_CHIP_SELECT_2 0x4 -#define EBI_BUSY_EN_RD (1 << 12) -#define DIR_ACCESS_WRITE (1 << 20) -#define DIR_ACCESS_MASK (1 << 20) +#define EBI_BUSY_EN_RD BIT(12) +#define DIR_ACCESS_WRITE BIT(20) +#define DIR_ACCESS_MASK BIT(20) /* various bits in configuration register EBI_DEV[01]_CONFIG2 */ #define ADDRESS_INCREMENT_ON 0x0 @@ -67,7 +67,7 @@ #define WRITE_ENDIANNESS_CDAB 0x3 /* various bits in configuration register EBI_CTRL_SIG_ACTLV */ -#define IORDY_ACTIVELEVEL_HIGH (1 << 14) +#define IORDY_ACTIVELEVEL_HIGH BIT(14) #define ALE_ACTIVELEVEL_HIGH (1 << 8) /* bits in register EBI_SIG_LEVEL */ diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index f078295..af50e47 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -101,10 +101,10 @@ int board_early_init_f(void) /* init custom i/o */ /* cpu type inputs */ - portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23), + portmux_select_gpio(PORTMUX_PORT_E, BIT(19) | BIT(20) | BIT(23), PORTMUX_DIR_INPUT); /* main board type inputs */ - portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29), + portmux_select_gpio(PORTMUX_PORT_B, BIT(19) | BIT(29), PORTMUX_DIR_INPUT); /* DEBUG input (use weak pullup) */ portmux_select_gpio(PORTMUX_PORT_E, 1 << 21, diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 4d0ebaa..270dacf 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -54,8 +54,8 @@ static void kollmorgen_init(void) int board_early_init_r(void) { /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); + *(vu_long *)MPC5XXX_ADDECR &= ~BIT(25); + *(vu_long *)MPC5XXX_ADDECR |= BIT(16); /* Initialize Kollmorgen DPR */ kollmorgen_init(); @@ -148,7 +148,7 @@ phys_size_t initdram(int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 5590be1..cc43d9b 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -720,7 +720,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | - (1 << 8) | /* power on ** */ + BIT(8) | /* power on ** */ ((status & USBPORTSC_LSDA) << (-8 + 9)); *(unsigned short *) data = swap_16(status); diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h index 582015f..44459fd 100644 --- a/board/mpl/common/usb_uhci.h +++ b/board/mpl/common/usb_uhci.h @@ -67,18 +67,18 @@ #define UHCI_PTR_DEPTH 0x0004 /* for TD : */ -#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ +#define TD_CTRL_SPD BIT(29) /* Short Packet Detect */ #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ -#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ -#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ -#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ -#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ -#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ -#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ -#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ -#define TD_CTRL_NAK (1 << 19) /* NAK Received */ -#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ -#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ +#define TD_CTRL_LS BIT(26) /* Low Speed Device */ +#define TD_CTRL_IOS BIT(25) /* Isochronous Select */ +#define TD_CTRL_IOC BIT(24) /* Interrupt on Complete */ +#define TD_CTRL_ACTIVE BIT(23) /* TD Active */ +#define TD_CTRL_STALLED BIT(22) /* TD Stalled */ +#define TD_CTRL_DBUFERR BIT(21) /* Data Buffer Error */ +#define TD_CTRL_BABBLE BIT(20) /* Babble Detected */ +#define TD_CTRL_NAK BIT(19) /* NAK Received */ +#define TD_CTRL_CRCTIMEO BIT(18) /* CRC/Time Out Error */ +#define TD_CTRL_BITSTUFF BIT(17) /* Bit Stuff Error */ #define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c index fcae5e0..8e4502d 100644 --- a/board/mpl/pati/cmd_pati.c +++ b/board/mpl/pati/cmd_pati.c @@ -101,7 +101,7 @@ static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); udelay(1); /* wait some time */ /* Enable EEPROM Chip Select */ - reg |= (1 << 25); + reg |= BIT(25); PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); /* Send EEPROM command - one bit at a time */ for (i = (int)(len-1); i >= 0; i--) { @@ -132,9 +132,9 @@ static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) /* Clear all EEPROM bits */ reg &= ~(0xF << 24); /* Make sure EEDO Input is disabled for some PLX chips */ - reg &= ~(1 << 31); + reg &= ~BIT(31); /* Enable EEPROM Chip Select */ - reg |= (1 << 25); + reg |= BIT(25); /* Write 16-bit value to EEPROM - one bit at a time */ for (bitpos = 15; bitpos >= 0; bitpos--) { /* Get bit value and shift into result */ @@ -145,16 +145,16 @@ static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) clock_pci_eeprom(); } /* for */ /* Deselect Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~BIT(25)); /* Re-select Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | BIT(25)); /* A small delay is needed to let EEPROM complete */ timeout = 0; do { udelay(10); reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); timeout++; - } while (((reg & (1 << 27)) == 0) && timeout < 20000); + } while (((reg & BIT(27)) == 0) && timeout < 20000); /* Send Write_Disable command to EEPROM */ send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); /* Clear Chip Select and all other EEPROM bits */ @@ -177,21 +177,21 @@ static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) /* Set EEPROM write output bit */ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); /* Set EEDO Input enable */ - reg |= (1 << 31); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); + reg |= BIT(31); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | BIT(26)); /* Get 16-bit value from EEPROM - one bit at a time */ for (bitpos = 0; bitpos < 16; bitpos++) { clock_pci_eeprom(); udelay(10); reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); /* Get bit value and shift into result */ - if (reg & (1 << 27)) + if (reg & BIT(27)) *pvalue = (unsigned short)((*pvalue << 1) | 1); else *pvalue = (unsigned short)(*pvalue << 1); } /* Clear EEDO Input enable */ - reg &= ~(1 << 31); + reg &= ~BIT(31); /* Clear Chip Select and all other EEPROM bits */ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); } diff --git a/board/munices/munices.c b/board/munices/munices.c index 23d0f56..cecadf5 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -94,7 +94,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index 32f2b20..6fade3b 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -110,7 +110,7 @@ int board_init(void) #ifdef CONFIG_DRIVER_TI_EMAC /* select emac MII mode */ val = readl(&davinci_syscfg_regs->cfgchip3); - val &= ~(1 << 8); + val &= ~BIT(8); writel(val, &davinci_syscfg_regs->cfgchip3); #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 59b5a7e..5115a5d 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -26,13 +26,13 @@ DECLARE_GLOBAL_DATA_PTR; -#define TWL4030_BB_CFG_BBCHEN (1 << 4) +#define TWL4030_BB_CFG_BBCHEN BIT(4) #define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2) #define TWL4030_BB_CFG_BBISEL_500UA 2 #define CONTROL_WKUP_CTRL 0x48002a5c -#define GPIO_IO_PWRDNZ (1 << 6) -#define PBIASLITEVMODE1 (1 << 8) +#define GPIO_IO_PWRDNZ BIT(6) +#define PBIASLITEVMODE1 BIT(8) /* * Routine: board_init diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 81f3024..bed394c 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -419,8 +419,8 @@ int checkboard (void) /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */ setbits_be32(&im->io_ctrl.io_control_gp, - (1 << 0) | /* GP_MUX7->GPIO7 */ - (1 << 5)); /* GP_MUX2->GPIO2 */ + BIT(0) | /* GP_MUX7->GPIO7 */ + BIT(5)); /* GP_MUX2->GPIO2 */ /* configure GPIO24 (VIU_CE), output/high */ setbits_be32(&im->gpio.gpdir, 0x80); diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index ed41de1..20217ec 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -113,7 +113,7 @@ phys_size_t initdram(int board_type) dramsize = test2; /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 1bf9d73..ec1a699 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -200,7 +200,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h index 11278a8..3fab644 100644 --- a/board/raidsonic/ib62x0/ib62x0.h +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -20,11 +20,11 @@ #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) /* SATAHC related */ #define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C) -#define MVSATAHC_LED_POLARITY_CTRL (1 << 3) +#define MVSATAHC_LED_POLARITY_CTRL BIT(3) #endif /* __IB62x0_H */ diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index f0010db..d887a44 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -42,13 +42,13 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF2_MSTP719 (1 << 19) -#define ETHER_MSTP813 (1 << 13) -#define IIC1_MSTP323 (1 << 23) -#define MMC0_MSTP315 (1 << 15) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) +#define TMU0_MSTP125 BIT(25) +#define SCIF2_MSTP719 BIT(19) +#define ETHER_MSTP813 BIT(13) +#define IIC1_MSTP323 BIT(23) +#define MMC0_MSTP315 BIT(15) +#define SDHI0_MSTP314 BIT(14) +#define SDHI1_MSTP312 BIT(12) #define SD1CKCR 0xE6150078 #define SD1_97500KHZ 0x7 diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index d862d99..83d69f1 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -53,7 +53,7 @@ int board_late_init(void) outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); - debug_led(1 << 3); + debug_ledBIT(3); outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); @@ -79,20 +79,20 @@ int board_init(void) outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); outw((inw(HIZCRA) & ~0x02), HIZCRA); - debug_led(1 << 0); + debug_ledBIT(0); /* SCIF0 (PTF, PTM) */ outw(inw(PFCR) & ~0x30, PFCR); outw(inw(PMCR) & ~0x0C, PMCR); outw((inw(PSELA) & ~0x40) | 0x40, PSELA); - debug_led(1 << 1); + debug_ledBIT(1); /* RMII (PTA) */ outw((inw(PACR) & ~0x0C) | 0x04, PACR); outb((inb(PADR) & ~0x02) | 0x02, PADR); - debug_led(1 << 2); + debug_ledBIT(2); /* USB host */ outw((inw(PBCR) & ~0x300) | 0x100, PBCR); @@ -100,7 +100,7 @@ int board_init(void) outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); outw(0x0600, UPONCR0); - debug_led(1 << 3); + debug_ledBIT(3); /* debug switch */ outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index bace439..6911288 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -45,13 +45,13 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define ETHER_MSTP813 BIT(13) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) -#define SDHI2_MSTP311 (1 << 11) +#define SDHI0_MSTP314 BIT(14) +#define SDHI1_MSTP312 BIT(12) +#define SDHI2_MSTP311 BIT(11) #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026C @@ -79,7 +79,7 @@ int board_early_init_f(void) #define PUPR5 0xE6060114 #define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define PUPR5_ETH_MAGIC BIT(27) int board_init(void) { diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 51e70e2..f5d5075 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -47,13 +47,13 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define ETHER_MSTP813 BIT(13) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) -#define SDHI2_MSTP311 (1 << 11) +#define SDHI0_MSTP314 BIT(14) +#define SDHI1_MSTP312 BIT(12) +#define SDHI2_MSTP311 BIT(11) #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026C @@ -86,7 +86,7 @@ int board_early_init_f(void) /* LSI pin pull-up control */ #define PUPR5 0xe6060114 #define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define PUPR5_ETH_MAGIC BIT(27) int board_init(void) { /* adress of boot parameters */ diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 83260a1..96d7b72 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -56,16 +56,16 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) -#define MMC1_MSTP305 (1 << 5) +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define ETHER_MSTP813 BIT(13) +#define MMC1_MSTP305 BIT(5) #define MSTPSR3 0xE6150048 #define SMSTPCR3 0xE615013C -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP313 (1 << 13) -#define SDHI2_MSTP312 (1 << 12) +#define SDHI0_MSTP314 BIT(14) +#define SDHI1_MSTP313 BIT(13) +#define SDHI2_MSTP312 BIT(12) #define SD2CKCR 0xE6150078 #define SD2_97500KHZ 0x7 diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index b5378de..eda86e6 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -47,11 +47,11 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI2_MSTP311 (1 << 11) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) +#define TMU0_MSTP125 BIT(25) +#define SDHI0_MSTP314 BIT(14) +#define SDHI2_MSTP311 BIT(11) +#define SCIF0_MSTP721 BIT(21) +#define ETHER_MSTP813 BIT(13) #define SD2CKCR 0xE615026C #define SD_97500KHZ 0x7 @@ -81,7 +81,7 @@ int board_early_init_f(void) /* LSI pin pull-up control */ #define PUPR5 0xe6060114 #define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define PUPR5_ETH_MAGIC BIT(27) int board_init(void) { /* adress of boot parameters */ diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c index 2e31ba6..a0c0410 100644 --- a/board/renesas/r0p7734/r0p7734.c +++ b/board/renesas/r0p7734/r0p7734.c @@ -31,7 +31,7 @@ int checkboard(void) #define MSTPSR1 (0xFFC80044) #define MSTPCR1 (0xFFC80034) -#define MSTPSR1_GETHER (1 << 14) +#define MSTPSR1_GETHER BIT(14) int board_init(void) { diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 021baab..4d22e12 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -43,12 +43,12 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF2_MSTP719 (1 << 19) -#define ETHER_MSTP813 (1 << 13) -#define IIC1_MSTP323 (1 << 23) -#define MMC0_MSTP315 (1 << 15) -#define SDHI1_MSTP312 (1 << 12) +#define TMU0_MSTP125 BIT(25) +#define SCIF2_MSTP719 BIT(19) +#define ETHER_MSTP813 BIT(13) +#define IIC1_MSTP323 BIT(23) +#define MMC0_MSTP315 BIT(15) +#define SDHI1_MSTP312 BIT(12) #define SD1CKCR 0xE6150078 #define SD1_97500KHZ 0x7 @@ -88,7 +88,7 @@ int board_early_init_f(void) #define PUPR3 0xe606010C #define PUPR3_ETH 0x006FF800 #define PUPR1 0xe6060104 -#define PUPR1_DREQ0_N (1 << 20) +#define PUPR1_DREQ0_N BIT(20) int board_init(void) { /* adress of boot parameters */ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index b96f745..df48f7f 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -248,7 +248,7 @@ int board_init(void) pm9261_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_DRIVER_DM9000 pm9261_dm9000_hw_init(); diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 1b00f08..bebc2af 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -347,7 +347,7 @@ int board_init(void) pm9263_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB pm9263_macb_hw_init(); diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index fdb83e4..b05ff78 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -59,7 +59,7 @@ skip_check_didle: str r1, [r0, #0x0] @ GPIO_CON_OFFSET ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET - bic r1, r1, #(1 << 1) + bic r1, r1, #BIT(1) str r1, [r0, #0x4] @ GPIO_DAT_OFFSET /* Don't setup at s5pc100 */ @@ -152,8 +152,8 @@ skip_check_didle: ldreq r0, =S5PC100_OTHERS @ 0xE0108200 ldrne r0, =S5PC110_OTHERS @ 0xE010E000 ldr r1, [r0] - ldreq r2, =(1 << 31) @ IO_RET_REL - ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + ldreq r2, =BIT(31) @ IO_RET_REL + ldrne r2, =(BIT(31) | BIT(30) | BIT(29) | BIT(28)) orr r1, r1, r2 /* Do not release retention here for S5PC110 */ streq r1, [r0] @@ -207,8 +207,8 @@ skip_check_didle: ldreq r0, =S5PC100_OTHERS @ 0xE0108200 ldrne r0, =S5PC110_OTHERS @ 0xE010E000 ldr r1, [r0] - ldreq r2, =(1 << 31) @ IO_RET_REL - ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + ldreq r2, =BIT(31) @ IO_RET_REL + ldrne r2, =(BIT(31) | BIT(30) | BIT(29) | BIT(28)) orr r1, r1, r2 str r1, [r0] @@ -219,8 +219,8 @@ didle_wakeup: ldr r0, =0xE0100100 @ S5PC110_APLL_CON lockloop: ldr r1, [r0] - and r1, r1, #(1 << 29) - cmp r1, #(1 << 29) + and r1, r1, #BIT(29) + cmp r1, #BIT(29) bne lockloop ldr r0, =S5PC110_INFORM0 @@ -417,7 +417,7 @@ uart_asm_init: str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET - orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit + orr r1, r1, #BIT(5) @ 5 = 5 * 1-bit str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET b 200f @@ -439,7 +439,7 @@ uart_asm_init: str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET - orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + orr r1, r1, #BIT(7) @ 7 = 7 * 1-bit str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 200: mov pc, lr diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 577c1a5..a574399 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -29,18 +29,18 @@ void onenand_board_init(struct mtd_info *mtd) /* D0 Domain memory clock gating */ value = readl(&clk->gate_d01); - value &= ~(1 << 2); /* CLK_ONENANDC */ - value |= (1 << 2); + value &= ~BIT(2); /* CLK_ONENANDC */ + value |= BIT(2); writel(value, &clk->gate_d01); value = readl(&clk->src0); - value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ - value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ + value &= ~BIT(24); /* MUX_1nand: 0 from HCLKD0 */ + value &= ~BIT(20); /* MUX_HREF: 0 from FIN_27M */ writel(value, &clk->src0); value = readl(&clk->div1); value &= ~(3 << 16); /* PCLKD1_RATIO */ - value |= (1 << 16); + value |= BIT(16); writel(value, &clk->div1); writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset); diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index df46713..3cc6e30 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -65,17 +65,17 @@ static unsigned short get_adc_value(int channel) unsigned int loop = 0; writel(channel & 0xF, &adc->adcmux); - writel((1 << 14) | (49 << 6), &adc->adccon); + writel(BIT(14) | (49 << 6), &adc->adccon); writel(1000 & 0xffff, &adc->adcdly); - writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ + writel(readl(&adc->adccon) | BIT(16), &adc->adccon); /* 12 bit */ udelay(10); - writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ + writel(readl(&adc->adccon) | BIT(0), &adc->adccon); /* Enable */ udelay(10); do { udelay(1); reg = readl(&adc->adccon); - } while (!(reg & (1 << 15)) && (loop++ < 1000)); + } while (!(reg & BIT(15)) && (loop++ < 1000)); ret = readl(&adc->adcdat0) & 0xFFF; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 6bdf1a2..be1ed8f 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -254,7 +254,7 @@ void board_reset(void) * rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("li 4, BIT(6)" ::: "r4"); __asm__ __volatile__ ("mtspr 27, 4"); __asm__ __volatile__ ("rfi"); #endif diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index f3f6dae..4ff3e1e 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -219,10 +219,10 @@ int board_init(void) corvus_nand_hw_init(); #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); + at91_spi0_hw_initBIT(4); #endif #ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); + at91_spi0_hw_initBIT(0); #endif #ifdef CONFIG_MACB corvus_macb_hw_init(); diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index ede73ba..48b44bd 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -232,7 +232,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 4d8ba3c..cd6dabb 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -205,7 +205,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index fb840f7..b6e7e1e 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -167,7 +167,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c index 815c9a7..b892de0 100644 --- a/board/silica/pengwyn/board.c +++ b/board/silica/pengwyn/board.c @@ -165,7 +165,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 953a43f..502374c 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -256,7 +256,7 @@ int ft_board_setup(void *blob, bd_t *bd) #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ #define DEFAULT_BRIGHTNESS 25 -#define BACKLIGHT_ENABLE (1 << 31) +#define BACKLIGHT_ENABLE BIT(31) static const gdc_regs init_regs [] = { diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2c4830f..9b9f29e 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -125,7 +125,7 @@ out: /* * STM32 RCC FMC specific definitions */ -#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ +#define STM32_RCC_ENR_FMC BIT(0) /* FMC module clock */ static inline u32 _ns2clk(u32 ns, u32 freq) { diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c index 8c16410..ab3cdc2 100644 --- a/board/synopsys/axs101/axs101.c +++ b/board/synopsys/axs101/axs101.c @@ -49,7 +49,7 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { - if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28)) + if (readl((void __iomem *)AXS_MB_CREG + 0x234) & BIT(28)) gd->board_type = AXS_MB_V3; else gd->board_type = AXS_MB_V2; diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c index 4be52e2..a044062 100644 --- a/board/synopsys/axs101/nand.c +++ b/board/synopsys/axs101/nand.c @@ -16,17 +16,17 @@ DECLARE_GLOBAL_DATA_PTR; #define BUS_WIDTH 8 /* AXI data bus width in bytes */ /* DMA buffer descriptor bits & masks */ -#define BD_STAT_OWN (1 << 31) -#define BD_STAT_BD_FIRST (1 << 3) -#define BD_STAT_BD_LAST (1 << 2) +#define BD_STAT_OWN BIT(31) +#define BD_STAT_BD_FIRST BIT(3) +#define BD_STAT_BD_LAST BIT(2) #define BD_SIZES_BUFFER1_MASK 0xfff #define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) /* Controller command flags */ -#define B_WFR (1 << 19) /* 1b - Wait for ready */ -#define B_LC (1 << 18) /* 1b - Last cycle */ -#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ +#define B_WFR BIT(19) /* 1b - Wait for ready */ +#define B_LC BIT(18) /* 1b - Last cycle */ +#define B_IWC BIT(13) /* 1b - Interrupt when complete */ /* NAND cycle types */ #define B_CT_ADDRESS (0x0 << 16) /* Address operation */ diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S index 5eccf09..ca3cf4b 100644 --- a/board/syteco/zmx25/lowlevel_init.S +++ b/board/syteco/zmx25/lowlevel_init.S @@ -48,12 +48,12 @@ * reset SDRAM controller * then wait for initialization to complete */ - ldr r1, =(1 << 1) | (1 << 2) + ldr r1, =BIT(1) | BIT(2) str r1, [r0, #ESDRAMC_ESDMISC] 1: ldr r3, [r0, #ESDRAMC_ESDMISC] - tst r3, #(1 << 31) + tst r3, #BIT(31) beq 1b - ldr r1, =(1 << 2) + ldr r1, =BIT(2) str r1, [r0, #ESDRAMC_ESDMISC] ldr r1, =0x002a7420 diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 96245a3..1dc1a19 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -548,7 +548,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 680f656..1725f45 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -284,14 +284,14 @@ void enable_i2c0_pin_mux(void) * valid and need pinmux to be configured. */ #define PROFILE_NONE 0x0 -#define PROFILE_0 (1 << 0) -#define PROFILE_1 (1 << 1) -#define PROFILE_2 (1 << 2) -#define PROFILE_3 (1 << 3) -#define PROFILE_4 (1 << 4) -#define PROFILE_5 (1 << 5) -#define PROFILE_6 (1 << 6) -#define PROFILE_7 (1 << 7) +#define PROFILE_0 BIT(0) +#define PROFILE_1 BIT(1) +#define PROFILE_2 BIT(2) +#define PROFILE_3 BIT(3) +#define PROFILE_4 BIT(4) +#define PROFILE_5 BIT(5) +#define PROFILE_6 BIT(6) +#define PROFILE_7 BIT(7) #define PROFILE_MASK 0x7 #define PROFILE_ALL 0xFF diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4aae230..d90bb88 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -778,7 +778,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index ffcd531..9ae7703 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -330,7 +330,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d464855..2dec661 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -305,7 +305,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index ab44676..923c3d4 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -19,14 +19,14 @@ DECLARE_GLOBAL_DATA_PTR; struct ddr3_phy_config ddr3phy_1600_8g = { .pllcr = 0x0001C000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .pgcr1_val = (BIT(2) | BIT(7) | BIT(23)), .ptr0 = 0x42C21590ul, .ptr1 = 0xD05612C0ul, .ptr2 = 0, /* not set in gel */ .ptr3 = 0x0D861A80ul, .ptr4 = 0x0C827100ul, .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), + .dcr_val = (BIT(10)), .dtpr0 = 0xA19DBB66ul, .dtpr1 = 0x32868300ul, .dtpr2 = 0x50035200ul, @@ -58,14 +58,14 @@ struct ddr3_emif_config ddr3_1600_8g = { struct ddr3_phy_config ddr3phy_1333_2g = { .pllcr = 0x0005C000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .pgcr1_val = (BIT(2) | BIT(7) | BIT(23)), .ptr0 = 0x42C21590ul, .ptr1 = 0xD05612C0ul, .ptr2 = 0, /* not set in gel */ .ptr3 = 0x0B4515C2ul, .ptr4 = 0x0A6E08B4ul, .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), + .dcr_val = (BIT(10)), .dtpr0 = 0x8558AA55ul, .dtpr1 = 0x32857280ul, .dtpr2 = 0x5002C200ul, @@ -98,14 +98,14 @@ struct ddr3_emif_config ddr3_1333_2g = { struct ddr3_phy_config ddr3phy_1600_4g = { .pllcr = 0x0001C000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .pgcr1_val = (BIT(2) | BIT(7) | BIT(23)), .ptr0 = 0x42C21590ul, .ptr1 = 0xD05612C0ul, .ptr2 = 0, /* not set in gel */ .ptr3 = 0x08861A80ul, .ptr4 = 0x0C827100ul, .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), + .dcr_val = (BIT(10)), .dtpr0 = 0x9D9CBB66ul, .dtpr1 = 0x12840300ul, .dtpr2 = 0x5002D200ul, @@ -136,14 +136,14 @@ struct ddr3_emif_config ddr3_1600_4g = { struct ddr3_phy_config ddr3phy_1600_2g = { .pllcr = 0x0001C000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .pgcr1_val = (BIT(2) | BIT(7) | BIT(23)), .ptr0 = 0x42C21590ul, .ptr1 = 0xD05612C0ul, .ptr2 = 0, /* not set in gel */ .ptr3 = 0x0D861A80ul, .ptr4 = 0x0C827100ul, .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), + .dcr_val = (BIT(10)), .dtpr0 = 0x9D5CBB66ul, .dtpr1 = 0x12868300ul, .dtpr2 = 0x5002D200ul, diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index e406dab..d769b91 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -154,7 +154,7 @@ static struct cpsw_platform_data cpsw_data = { .host_port_reg_ofs = 0x28, .hw_stats_reg_ofs = 0x400, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), + .mac_control = BIT(5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_1, diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 5f905d5..6b35ad2 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -569,65 +569,65 @@ int do_led(char * const argv[]) case 0: if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 8); + gpio->simple_dvo |= BIT(8); } else { - gpio->simple_dvo &= ~(1 << 8); + gpio->simple_dvo &= ~BIT(8); } break; case 1: if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 9); + gpio->simple_dvo |= BIT(9); } else { - gpio->simple_dvo &= ~(1 << 9); + gpio->simple_dvo &= ~BIT(9); } break; case 2: if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 10); + gpio->simple_dvo |= BIT(10); } else { - gpio->simple_dvo &= ~(1 << 10); + gpio->simple_dvo &= ~BIT(10); } break; case 3: if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 11); + gpio->simple_dvo |= BIT(11); } else { - gpio->simple_dvo &= ~(1 << 11); + gpio->simple_dvo &= ~BIT(11); } break; case 4: if (strcmp (argv[3], "on") == 0) { - gpt->gpt4.emsr |= (1 << 4); + gpt->gpt4.emsr |= BIT(4); } else { - gpt->gpt4.emsr &= ~(1 << 4); + gpt->gpt4.emsr &= ~BIT(4); } break; case 5: if (strcmp (argv[3], "on") == 0) { - gpt->gpt5.emsr |= (1 << 4); + gpt->gpt5.emsr |= BIT(4); } else { - gpt->gpt5.emsr &= ~(1 << 4); + gpt->gpt5.emsr &= ~BIT(4); } break; case 6: if (strcmp (argv[3], "on") == 0) { - gpt->gpt6.emsr |= (1 << 4); + gpt->gpt6.emsr |= BIT(4); } else { - gpt->gpt6.emsr &= ~(1 << 4); + gpt->gpt6.emsr &= ~BIT(4); } break; case 7: if (strcmp (argv[3], "on") == 0) { - gpt->gpt7.emsr |= (1 << 4); + gpt->gpt7.emsr |= BIT(4); } else { - gpt->gpt7.emsr &= ~(1 << 4); + gpt->gpt7.emsr &= ~BIT(4); } break; #ifndef CONFIG_TQM5200S @@ -1020,7 +1020,7 @@ int do_rs232(char * const argv[]) /* check TXD <-> RXD loop */ /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); + gpio->simple_dvo |= BIT(8); /* wait some time before requesting status */ udelay(10); @@ -1034,7 +1034,7 @@ int do_rs232(char * const argv[]) } /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); + gpio->simple_dvo &= ~BIT(8); /* wait some time before requesting status */ udelay(10); @@ -1049,7 +1049,7 @@ int do_rs232(char * const argv[]) /* check RTS <-> CTS loop */ /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); + gpio->simple_dvo |= BIT(10); /* wait some time before requesting status */ udelay(10); @@ -1063,7 +1063,7 @@ int do_rs232(char * const argv[]) } /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); + gpio->simple_dvo &= ~BIT(10); /* wait some time before requesting status */ udelay(10); @@ -1095,10 +1095,10 @@ static void sm501_backlight (unsigned int state) { if (state == BL_ON) { *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= - (1 << 26) | (1 << 27); + BIT(26) | BIT(27); } else if (state == BL_OFF) *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= - ~((1 << 26) | (1 << 27)); + ~(BIT(26) | BIT(27)); } #endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index 4d4f29d..669eb55 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -169,7 +169,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { + if (dramsize < BIT(20)) { dramsize = 0; } @@ -200,7 +200,7 @@ phys_size_t initdram (int board_type) } /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { + if (dramsize2 < BIT(20)) { dramsize2 = 0; } @@ -585,7 +585,7 @@ int last_stage_init (void) if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { /* no SRAM at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_ADDECR &= ~BIT(18); *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; restore = 0; @@ -634,7 +634,7 @@ int last_stage_init (void) if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_ADDECR &= ~BIT(17); *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; restore = 0; diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 1ddf05d..284d7e4 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -25,8 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index a337729..d1f4459 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -93,7 +93,7 @@ phys_size_t initdram(int board_type) dramsize = test2; /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) + if (dramsize < BIT(20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ @@ -120,7 +120,7 @@ phys_size_t initdram(int board_type) dramsize2 = test2; /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) + if (dramsize2 < BIT(20)) dramsize2 = 0; /* set SDRAM CS1 size according to the amount of RAM found */ diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c index 3da61a4..91a3a1b 100644 --- a/board/woodburn/woodburn.c +++ b/board/woodburn/woodburn.c @@ -182,7 +182,7 @@ int board_init(void) val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); /* Set SWILIMB */ - val |= (1 << 22); + val |= BIT(22); pmic_reg_write(p, REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 90bba6a..62fdca5 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -118,24 +118,24 @@ void zipitz2_spi_sda(int set) { /* GPIO 13 */ if (set) - writel((1 << 13), GPSR0); + writel(BIT(13), GPSR0); else - writel((1 << 13), GPCR0); + writel(BIT(13), GPCR0); } void zipitz2_spi_scl(int set) { /* GPIO 22 */ if (set) - writel((1 << 22), GPCR0); + writel(BIT(22), GPCR0); else - writel((1 << 22), GPSR0); + writel(BIT(22), GPSR0); } unsigned char zipitz2_spi_read(void) { /* GPIO 40 */ - return !!(readl(GPLR1) & (1 << 8)); + return !!(readl(GPLR1) & BIT(8)); } int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -147,13 +147,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { /* GPIO 88 low */ - writel((1 << 24), GPCR2); + writel(BIT(24), GPCR2); } void spi_cs_deactivate(struct spi_slave *slave) { /* GPIO 88 high */ - writel((1 << 24), GPSR2); + writel(BIT(24), GPSR2); } @@ -174,11 +174,11 @@ void lcd_start(void) writel(792, PWM_PERVAL2); /* Toggle the reset pin to reset the LCD */ - writel((1 << 19), GPSR0); + writel(BIT(19), GPSR0); udelay(100000); - writel((1 << 19), GPCR0); + writel(BIT(19), GPCR0); udelay(20000); - writel((1 << 19), GPSR0); + writel(BIT(19), GPSR0); udelay(20000); /* Program the LCD init sequence */ @@ -197,6 +197,6 @@ void lcd_start(void) udelay(lcd_data[i].mdelay * 1000); } - writel((1 << 11), GPSR0); + writel(BIT(11), GPSR0); } #endif diff --git a/common/bedbug.c b/common/bedbug.c index 42ecf61..c389429 100644 --- a/common/bedbug.c +++ b/common/bedbug.c @@ -1103,8 +1103,8 @@ int find_next_address (unsigned char *nextaddr, int step_over, !get_operand_value (op, instr, O_LK, &lk)) return false; - if ((addr & (1 << 13)) != 0) - addr = addr - (1 << 14); + if ((addr & BIT(13)) != 0) + addr = addr - BIT(14); addr <<= 2; conditional = 1; branch = 1; @@ -1119,8 +1119,8 @@ int find_next_address (unsigned char *nextaddr, int step_over, !get_operand_value (op, instr, O_LK, &lk)) return false; - if ((addr & (1 << 23)) != 0) - addr = addr - (1 << 24); + if ((addr & BIT(23)) != 0) + addr = addr - BIT(24); addr <<= 2; conditional = 0; branch = 1; diff --git a/common/bootm.c b/common/bootm.c index 6842029..3553a99 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -906,7 +906,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type) } /* Allow the image to expand by a factor of 4, should be safe */ - load_buf = malloc((1 << 20) + len * 4); + load_buf = malloc(BIT(20) + len * 4); ret = bootm_decomp_image(imape_comp, 0, data, image_type, load_buf, (void *)data, len, CONFIG_SYS_BOOTM_LEN, &load_end); diff --git a/common/cli_hush.c b/common/cli_hush.c index 296542f..423b813 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -121,8 +121,8 @@ #define SUBSTED_VAR_SYMBOL 04 #ifndef __U_BOOT__ #define FLAG_EXIT_FROM_LOOP 1 -#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ -#define FLAG_REPARSING (1 << 2) /* >= 2nd pass */ +#define FLAG_PARSE_SEMICOLON BIT(1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING BIT(2) /* >= 2nd pass */ #endif diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index be792ae..a510aa2 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -58,7 +58,7 @@ SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE /* * Maximum expected input data size for import command */ -#define MAX_ENV_SIZE (1 << 20) /* 1 MiB */ +#define MAX_ENV_SIZE BIT(20) /* 1 MiB */ /* * This variable is incremented on each do_env_set(), so it can diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 24a1a56..57414d0 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -39,14 +39,14 @@ int overwrite_console(void) #define SCROLL_LOCK 0x47 /* Modifier bits */ -#define LEFT_CNTR (1 << 0) -#define LEFT_SHIFT (1 << 1) -#define LEFT_ALT (1 << 2) -#define LEFT_GUI (1 << 3) -#define RIGHT_CNTR (1 << 4) -#define RIGHT_SHIFT (1 << 5) -#define RIGHT_ALT (1 << 6) -#define RIGHT_GUI (1 << 7) +#define LEFT_CNTR BIT(0) +#define LEFT_SHIFT BIT(1) +#define LEFT_ALT BIT(2) +#define LEFT_GUI BIT(3) +#define RIGHT_CNTR BIT(4) +#define RIGHT_SHIFT BIT(5) +#define RIGHT_ALT BIT(6) +#define RIGHT_GUI BIT(7) /* Size of the keyboard buffer */ #define USB_KBD_BUFFER_LEN 0x20 @@ -85,10 +85,10 @@ static const unsigned char usb_kbd_arrow[] = { * NOTE: It's important for the NUM, CAPS, SCROLL-lock bits to be in this * order. See usb_kbd_setled() function! */ -#define USB_KBD_NUMLOCK (1 << 0) -#define USB_KBD_CAPSLOCK (1 << 1) -#define USB_KBD_SCROLLLOCK (1 << 2) -#define USB_KBD_CTRL (1 << 3) +#define USB_KBD_NUMLOCK BIT(0) +#define USB_KBD_CAPSLOCK BIT(1) +#define USB_KBD_SCROLLLOCK BIT(2) +#define USB_KBD_CTRL BIT(3) #define USB_KBD_LEDMASK \ (USB_KBD_NUMLOCK | USB_KBD_CAPSLOCK | USB_KBD_SCROLLLOCK) diff --git a/common/usb_storage.c b/common/usb_storage.c index cc9b3e3..6918e22 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -77,7 +77,7 @@ struct us_data { struct usb_device *pusb_dev; /* this usb_device */ unsigned int flags; /* from filter initially */ -# define USB_READY (1 << 0) +# define USB_READY BIT(0) unsigned char ifnum; /* interface number */ unsigned char ep_in; /* in endpoint */ unsigned char ep_out; /* out ....... */ diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 7ea5fa6..1a1a3e1 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -182,7 +182,7 @@ static int atibios_set_vesa_mode(RMREGS *regs, int vesa_mode, regs->e.eax = VESA_SET_MODE; regs->e.ebx = vesa_mode; /* request linear framebuffer mode and don't clear display */ - regs->e.ebx |= (1 << 14) | (1 << 15); + regs->e.ebx |= BIT(14) | BIT(15); BE_int86(0x10, regs, regs); if (regs->e.eax != 0x4f) { debug("VESA_SET_MODE: error %x\n", regs->e.eax); diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 6508648..b9ff97e 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -180,8 +180,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) debug("ahci_host_init: start\n"); cap_save = readl(mmio + HOST_CAP); - cap_save &= ((1 << 28) | (1 << 17)); - cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ + cap_save &= (BIT(28) | BIT(17)); + cap_save |= BIT(27); /* Staggered Spin-up. Not needed. */ ret = ahci_reset(probe_ent->mmio_base); if (ret) @@ -374,26 +374,26 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) "%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s" "%s%s%s%s%s%s\n", - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 16) ? "fbss " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : "", - cap & (1 << 7) ? "ccc " : "", - cap & (1 << 6) ? "ems " : "", - cap & (1 << 5) ? "sxs " : "", - cap2 & (1 << 2) ? "apst " : "", - cap2 & (1 << 1) ? "nvmp " : "", - cap2 & (1 << 0) ? "boh " : ""); + cap & BIT(31) ? "64bit " : "", + cap & BIT(30) ? "ncq " : "", + cap & BIT(28) ? "ilck " : "", + cap & BIT(27) ? "stag " : "", + cap & BIT(26) ? "pm " : "", + cap & BIT(25) ? "led " : "", + cap & BIT(24) ? "clo " : "", + cap & BIT(19) ? "nz " : "", + cap & BIT(18) ? "only " : "", + cap & BIT(17) ? "pmp " : "", + cap & BIT(16) ? "fbss " : "", + cap & BIT(15) ? "pio " : "", + cap & BIT(14) ? "slum " : "", + cap & BIT(13) ? "part " : "", + cap & BIT(7) ? "ccc " : "", + cap & BIT(6) ? "ems " : "", + cap & BIT(5) ? "sxs " : "", + cap2 & BIT(2) ? "apst " : "", + cap2 & BIT(1) ? "nvmp " : "", + cap2 & BIT(0) ? "boh " : ""); } #ifndef CONFIG_SCSI_AHCI_PLAT diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index cf3ef6b..c40833b 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -313,19 +313,19 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) printf("flags: " "%s%s%s%s%s%s" "%s%s%s%s%s%s%s\n", - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : ""); + cap & BIT(31) ? "64bit " : "", + cap & BIT(30) ? "ncq " : "", + cap & BIT(28) ? "ilck " : "", + cap & BIT(27) ? "stag " : "", + cap & BIT(26) ? "pm " : "", + cap & BIT(25) ? "led " : "", + cap & BIT(24) ? "clo " : "", + cap & BIT(19) ? "nz " : "", + cap & BIT(18) ? "only " : "", + cap & BIT(17) ? "pmp " : "", + cap & BIT(15) ? "pio " : "", + cap & BIT(14) ? "slum " : "", + cap & BIT(13) ? "part " : ""); } static int ahci_init_one(int pdev) diff --git a/drivers/block/ftide020.h b/drivers/block/ftide020.h index 2d88c7c..5a6fc5f 100644 --- a/drivers/block/ftide020.h +++ b/drivers/block/ftide020.h @@ -40,24 +40,24 @@ struct ftide020_s { #define CONFIG_CTRD1_PROBE_T2 0x5 /* status register - 0x04 */ -#define STATUS_CSEL (1 << 0) /* CSEL */ +#define STATUS_CSEL BIT(0) /* CSEL */ #define STATUS_CS(x) (((x) >> 1) & 0x3) /* CS#[1:0] */ -#define STATUS_DMACK (1 << 3) /* DMACK# */ -#define STATUS_DMARQ (1 << 4) /* DMA req */ -#define STATUS_INTRQ (1 << 5) /* INT req */ -#define STATUS_DIOR (1 << 6) /* DIOR */ -#define STATUS_IORDY (1 << 7) /* I/O ready */ -#define STATUS_DIOW (1 << 8) /* DIOW# */ -#define STATUS_PDIAG (1 << 9) /* PDIAG */ -#define STATUS_DASP (1 << 10) /* DASP# */ -#define STATUS_DEV (1 << 11) /* selected device */ -#define STATUS_PIO (1 << 12) /* PIO in progress */ -#define STATUS_DMA (1 << 13) /* DMA in progress */ -#define STATUS_WFE (1 << 14) /* write fifo full */ -#define STATUS_RFE (1 << 15) /* read fifo empty */ +#define STATUS_DMACK BIT(3) /* DMACK# */ +#define STATUS_DMARQ BIT(4) /* DMA req */ +#define STATUS_INTRQ BIT(5) /* INT req */ +#define STATUS_DIOR BIT(6) /* DIOR */ +#define STATUS_IORDY BIT(7) /* I/O ready */ +#define STATUS_DIOW BIT(8) /* DIOW# */ +#define STATUS_PDIAG BIT(9) /* PDIAG */ +#define STATUS_DASP BIT(10) /* DASP# */ +#define STATUS_DEV BIT(11) /* selected device */ +#define STATUS_PIO BIT(12) /* PIO in progress */ +#define STATUS_DMA BIT(13) /* DMA in progress */ +#define STATUS_WFE BIT(14) /* write fifo full */ +#define STATUS_RFE BIT(15) /* read fifo empty */ #define STATUS_COUNTER(x) (((x) >> 16) & 0x3fff) /* data tx counter */ -#define STATUS_ERR (1 << 30) /* trasfer terminated */ -#define STATUS_AER (1 << 31) /* AHB timeout indicate */ +#define STATUS_ERR BIT(30) /* trasfer terminated */ +#define STATUS_AER BIT(31) /* AHB timeout indicate */ /* Control register - 0x08 */ #define CONTROL_TYPE_PIO 0x0 @@ -65,49 +65,49 @@ struct ftide020_s { /* Device 0 */ #define CONTROL_TYP0(x) (((x) & 0x7) << 0) -#define CONTROL_IRE0 (1 << 3) /* enable IORDY for PIO */ -#define CONTROL_RESVD_DW0 (1 << 4) /* Reserved - DW0 ? */ -#define CONTROL_E0 (1 << 5) /* E0: 1: Big Endian */ -#define CONTROL_RESVD_WP0 (1 << 6) /* Reserved - WP0 ? */ -#define CONTROL_RESVD_SE0 (1 << 7) /* Reserved - SE0 ? */ -#define CONTROL_RESVD_ECC0 (1 << 8) /* Reserved - ECC0 ? */ +#define CONTROL_IRE0 BIT(3) /* enable IORDY for PIO */ +#define CONTROL_RESVD_DW0 BIT(4) /* Reserved - DW0 ? */ +#define CONTROL_E0 BIT(5) /* E0: 1: Big Endian */ +#define CONTROL_RESVD_WP0 BIT(6) /* Reserved - WP0 ? */ +#define CONTROL_RESVD_SE0 BIT(7) /* Reserved - SE0 ? */ +#define CONTROL_RESVD_ECC0 BIT(8) /* Reserved - ECC0 ? */ -#define CONTROL_RAEIE (1 << 9) /* IRQ - read fifo almost full */ -#define CONTROL_RNEIE (1 << 10) /* IRQ - read fifo not empty */ -#define CONTROL_WAFIE (1 << 11) /* IRQ - write fifo almost empty */ -#define CONTROL_WNFIE (1 << 12) /* IRQ - write fifo not full */ -#define CONTROL_RESVD_FIRQ (1 << 13) /* RESERVED - FIRQ ? */ -#define CONTROL_AERIE (1 << 14) /* IRQ - AHB timeout error */ -#define CONTROL_IIE (1 << 15) /* IDE IRQ enable */ +#define CONTROL_RAEIE BIT(9) /* IRQ - read fifo almost full */ +#define CONTROL_RNEIE BIT(10) /* IRQ - read fifo not empty */ +#define CONTROL_WAFIE BIT(11) /* IRQ - write fifo almost empty */ +#define CONTROL_WNFIE BIT(12) /* IRQ - write fifo not full */ +#define CONTROL_RESVD_FIRQ BIT(13) /* RESERVED - FIRQ ? */ +#define CONTROL_AERIE BIT(14) /* IRQ - AHB timeout error */ +#define CONTROL_IIE BIT(15) /* IDE IRQ enable */ /* Device 1 */ #define CONTROL_TYP1(x) (((x) & 0x7) << 16) -#define CONTROL_IRE1 (1 << 19) /* enable IORDY for PIO */ -#define CONTROL_RESVD_DW1 (1 << 20) /* Reserved - DW1 ? */ -#define CONTROL_E1 (1 << 21) /* E1: 1: Big Endian */ -#define CONTROL_RESVD_WP1 (1 << 22) /* Reserved - WP1 ? */ -#define CONTROL_RESVD_SE1 (1 << 23) /* Reserved - SE1 ? */ -#define CONTROL_RESVD_ECC1 (1 << 24) /* Reserved - ECC1 ? */ +#define CONTROL_IRE1 BIT(19) /* enable IORDY for PIO */ +#define CONTROL_RESVD_DW1 BIT(20) /* Reserved - DW1 ? */ +#define CONTROL_E1 BIT(21) /* E1: 1: Big Endian */ +#define CONTROL_RESVD_WP1 BIT(22) /* Reserved - WP1 ? */ +#define CONTROL_RESVD_SE1 BIT(23) /* Reserved - SE1 ? */ +#define CONTROL_RESVD_ECC1 BIT(24) /* Reserved - ECC1 ? */ -#define CONTROL_DRE (1 << 25) /* DMA receive enable */ -#define CONTROL_DTE (1 << 26) /* DMA transmit enable */ -#define CONTRIL_RESVD (1 << 27) -#define CONTROL_TERIE (1 << 28) /* transfer terminate error IRQ */ -#define CONTROL_T (1 << 29) /* terminate current operation */ -#define CONTROL_SRST (1 << 30) /* IDE soft reset */ -#define CONTROL_RST (1 << 31) /* IDE hardware reset */ +#define CONTROL_DRE BIT(25) /* DMA receive enable */ +#define CONTROL_DTE BIT(26) /* DMA transmit enable */ +#define CONTRIL_RESVD BIT(27) +#define CONTROL_TERIE BIT(28) /* transfer terminate error IRQ */ +#define CONTROL_T BIT(29) /* terminate current operation */ +#define CONTROL_SRST BIT(30) /* IDE soft reset */ +#define CONTROL_RST BIT(31) /* IDE hardware reset */ /* IRQ register - 0x0c */ #define IRQ_RXTHRESH(x) (((x) & 0x3ff) << 0) /* Read FIFO threshold */ -#define IRQ_RFAEIRQ (1 << 10) /* Read FIFO almost full intr req */ -#define IRQ_RFNEIRQ (1 << 11) /* Read FIFO not empty intr req */ -#define IRQ_WFAFIRQ (1 << 12) /* Write FIFO almost empty int req */ -#define IRQ_WFNFIRQ (1 << 13) /* Write FIFO not full intr req */ -#define IRQ_RESVD_FIRQ (1 << 14) /* Reserved - FIRQ ? */ -#define IRQ_IIRQ (1 << 15) /* IDE device interrupt request */ +#define IRQ_RFAEIRQ BIT(10) /* Read FIFO almost full intr req */ +#define IRQ_RFNEIRQ BIT(11) /* Read FIFO not empty intr req */ +#define IRQ_WFAFIRQ BIT(12) /* Write FIFO almost empty int req */ +#define IRQ_WFNFIRQ BIT(13) /* Write FIFO not full intr req */ +#define IRQ_RESVD_FIRQ BIT(14) /* Reserved - FIRQ ? */ +#define IRQ_IIRQ BIT(15) /* IDE device interrupt request */ #define IRQ_TXTHRESH(x) (((x) & 0x3ff) << 16) /* Write FIFO thershold */ -#define IRQ_TERMERR (1 << 28) /* Transfer termination indication */ -#define IRQ_AHBERR (1 << 29) /* AHB Timeout indication */ +#define IRQ_TERMERR BIT(28) /* Transfer termination indication */ +#define IRQ_AHBERR BIT(29) /* AHB Timeout indication */ /* Command Timing Register 0-1: ctrd (0x10, 0x18) */ #define CT_REG_T1(x) (((x) & 0xff) << 0) /* setup time of addressed */ @@ -146,7 +146,7 @@ struct ftide020_s { /* ftide020_s command formats */ /* read: IDE Register (CF1) */ -#define IDE_REG_OPCODE_READ (1 << 13) /* 0x2000 */ +#define IDE_REG_OPCODE_READ BIT(13) /* 0x2000 */ #define IDE_REG_CS_READ(x) (((x) & 0x3) << 11) #define IDE_REG_DA_READ(x) (((x) & 0x7) << 8) #define IDE_REG_CMD_READ(x) 0x0 /* fixed value */ @@ -159,7 +159,7 @@ struct ftide020_s { #define IDE_REG_CMD_WRITE(x) (((x) & 0xff) << 0) /* read/write data: PIO/UDMA (CF3) */ -#define IDE_DATA_WRITE (1 << 15) /* read: 0, write: 1 */ +#define IDE_DATA_WRITE BIT(15) /* read: 0, write: 1 */ #define IDE_DATA_OPCODE (0x2 << 13) /* device data access opcode */ /* b(0:12) IDE_DATA_COUNTER(x): Number of transfers minus 1 */ #define IDE_DATA_COUNTER(x) (((x) & 0x1fff) << 0) diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index c2673bd..2adfbf6 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -575,8 +575,8 @@ static unsigned int bfin_devchk(struct ata_port *ap, static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; - unsigned int dev0 = devmask & (1 << 0); - unsigned int dev1 = devmask & (1 << 1); + unsigned int dev0 = devmask & BIT(0); + unsigned int dev1 = devmask & BIT(1); long deadline; /* if device 0 was found in ata_devchk, wait for its @@ -674,9 +674,9 @@ static int bfin_softreset(struct ata_port *ap) * only one device is supported on one port by now. */ if (bfin_devchk(ap, 0)) - ap->dev_mask |= (1 << 0); + ap->dev_mask |= BIT(0); else if (bfin_devchk(ap, 1)) - ap->dev_mask |= (1 << 1); + ap->dev_mask |= BIT(1); else return -ENODEV; diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 9e8b067..b6f84c4 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -511,7 +511,7 @@ static int ata_id_has_hipm(const u16 *id) if (val == 0 || val == 0xffff) return -1; - return val & (1 << 9); + return val & BIT(9); } static int ata_id_has_dipm(const u16 *id) @@ -521,7 +521,7 @@ static int ata_id_has_dipm(const u16 *id) if (val == 0 || val == 0xffff) return -1; - return val & (1 << 3); + return val & BIT(3); } int scan_sata(int dev) @@ -588,7 +588,7 @@ int scan_sata(int dev) ata_dev->heads = 0; ata_dev->sectors = 0; - if (id[ATA_ID_FIELD_VALID] & (1 << 1)) { + if (id[ATA_ID_FIELD_VALID] & BIT(1)) { pio_mask = id[ATA_ID_PIO_MODES] & 0x03; pio_mask <<= 3; pio_mask |= 0x7; @@ -612,13 +612,13 @@ int scan_sata(int dev) int dma = (id[163] >> 3) & 7; if (pio) - pio_mask |= (1 << 5); + pio_mask |= BIT(5); if (pio > 1) - pio_mask |= (1 << 6); + pio_mask |= BIT(6); if (dma) - mwdma_mask |= (1 << 3); + mwdma_mask |= BIT(3); if (dma > 1) - mwdma_mask |= (1 << 4); + mwdma_mask |= BIT(4); } if (ata_dev->class == ATA_DEV_ATA) { @@ -698,7 +698,7 @@ int scan_sata(int dev) sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors; #ifdef CONFIG_LBA48 - if (ata_dev->id[83] & (1 << 10)) { + if (ata_dev->id[83] & BIT(10)) { sata_dev_desc[dev].lba48 = 1; } else { sata_dev_desc[dev].lba48 = 0; diff --git a/drivers/block/sata_dwc.h b/drivers/block/sata_dwc.h index e2d9e0c..825398d 100644 --- a/drivers/block/sata_dwc.h +++ b/drivers/block/sata_dwc.h @@ -33,7 +33,7 @@ #define WRITE 1 enum { - ATA_READID_POSTRESET = (1 << 0), + ATA_READID_POSTRESET = BIT(0), ATA_DNXFER_PIO = 0, ATA_DNXFER_DMA = 1, @@ -41,7 +41,7 @@ enum { ATA_DNXFER_FORCE_PIO = 3, ATA_DNXFER_FORCE_PIO0 = 4, - ATA_DNXFER_QUIET = (1 << 31), + ATA_DNXFER_QUIET = BIT(31), }; enum hsm_task_states { @@ -102,84 +102,84 @@ enum { ATA_SHT_THIS_ID = -1, ATA_SHT_USE_CLUSTERING = 1, - ATA_DFLAG_LBA = (1 << 0), - ATA_DFLAG_LBA48 = (1 << 1), - ATA_DFLAG_CDB_INTR = (1 << 2), - ATA_DFLAG_NCQ = (1 << 3), - ATA_DFLAG_FLUSH_EXT = (1 << 4), - ATA_DFLAG_ACPI_PENDING = (1 << 5), - ATA_DFLAG_ACPI_FAILED = (1 << 6), - ATA_DFLAG_AN = (1 << 7), - ATA_DFLAG_HIPM = (1 << 8), - ATA_DFLAG_DIPM = (1 << 9), - ATA_DFLAG_DMADIR = (1 << 10), - ATA_DFLAG_CFG_MASK = (1 << 12) - 1, - - ATA_DFLAG_PIO = (1 << 12), - ATA_DFLAG_NCQ_OFF = (1 << 13), - ATA_DFLAG_SPUNDOWN = (1 << 14), - ATA_DFLAG_SLEEPING = (1 << 15), - ATA_DFLAG_DUBIOUS_XFER = (1 << 16), - ATA_DFLAG_INIT_MASK = (1 << 24) - 1, - - ATA_DFLAG_DETACH = (1 << 24), - ATA_DFLAG_DETACHED = (1 << 25), - - ATA_LFLAG_HRST_TO_RESUME = (1 << 0), - ATA_LFLAG_SKIP_D2H_BSY = (1 << 1), - ATA_LFLAG_NO_SRST = (1 << 2), - ATA_LFLAG_ASSUME_ATA = (1 << 3), - ATA_LFLAG_ASSUME_SEMB = (1 << 4), + ATA_DFLAG_LBA = BIT(0), + ATA_DFLAG_LBA48 = BIT(1), + ATA_DFLAG_CDB_INTR = BIT(2), + ATA_DFLAG_NCQ = BIT(3), + ATA_DFLAG_FLUSH_EXT = BIT(4), + ATA_DFLAG_ACPI_PENDING = BIT(5), + ATA_DFLAG_ACPI_FAILED = BIT(6), + ATA_DFLAG_AN = BIT(7), + ATA_DFLAG_HIPM = BIT(8), + ATA_DFLAG_DIPM = BIT(9), + ATA_DFLAG_DMADIR = BIT(10), + ATA_DFLAG_CFG_MASK = BIT(12) - 1, + + ATA_DFLAG_PIO = BIT(12), + ATA_DFLAG_NCQ_OFF = BIT(13), + ATA_DFLAG_SPUNDOWN = BIT(14), + ATA_DFLAG_SLEEPING = BIT(15), + ATA_DFLAG_DUBIOUS_XFER = BIT(16), + ATA_DFLAG_INIT_MASK = BIT(24) - 1, + + ATA_DFLAG_DETACH = BIT(24), + ATA_DFLAG_DETACHED = BIT(25), + + ATA_LFLAG_HRST_TO_RESUME = BIT(0), + ATA_LFLAG_SKIP_D2H_BSY = BIT(1), + ATA_LFLAG_NO_SRST = BIT(2), + ATA_LFLAG_ASSUME_ATA = BIT(3), + ATA_LFLAG_ASSUME_SEMB = BIT(4), ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB, - ATA_LFLAG_NO_RETRY = (1 << 5), - ATA_LFLAG_DISABLED = (1 << 6), - - ATA_FLAG_SLAVE_POSS = (1 << 0), - ATA_FLAG_SATA = (1 << 1), - ATA_FLAG_NO_LEGACY = (1 << 2), - ATA_FLAG_MMIO = (1 << 3), - ATA_FLAG_SRST = (1 << 4), - ATA_FLAG_SATA_RESET = (1 << 5), - ATA_FLAG_NO_ATAPI = (1 << 6), - ATA_FLAG_PIO_DMA = (1 << 7), - ATA_FLAG_PIO_LBA48 = (1 << 8), - ATA_FLAG_PIO_POLLING = (1 << 9), - ATA_FLAG_NCQ = (1 << 10), - ATA_FLAG_DEBUGMSG = (1 << 13), - ATA_FLAG_IGN_SIMPLEX = (1 << 15), - ATA_FLAG_NO_IORDY = (1 << 16), - ATA_FLAG_ACPI_SATA = (1 << 17), - ATA_FLAG_AN = (1 << 18), - ATA_FLAG_PMP = (1 << 19), - ATA_FLAG_IPM = (1 << 20), - - ATA_FLAG_DISABLED = (1 << 23), - - ATA_PFLAG_EH_PENDING = (1 << 0), - ATA_PFLAG_EH_IN_PROGRESS = (1 << 1), - ATA_PFLAG_FROZEN = (1 << 2), - ATA_PFLAG_RECOVERED = (1 << 3), - ATA_PFLAG_LOADING = (1 << 4), - ATA_PFLAG_UNLOADING = (1 << 5), - ATA_PFLAG_SCSI_HOTPLUG = (1 << 6), - ATA_PFLAG_INITIALIZING = (1 << 7), - ATA_PFLAG_RESETTING = (1 << 8), - ATA_PFLAG_SUSPENDED = (1 << 17), - ATA_PFLAG_PM_PENDING = (1 << 18), - - ATA_QCFLAG_ACTIVE = (1 << 0), - ATA_QCFLAG_DMAMAP = (1 << 1), - ATA_QCFLAG_IO = (1 << 3), - ATA_QCFLAG_RESULT_TF = (1 << 4), - ATA_QCFLAG_CLEAR_EXCL = (1 << 5), - ATA_QCFLAG_QUIET = (1 << 6), - - ATA_QCFLAG_FAILED = (1 << 16), - ATA_QCFLAG_SENSE_VALID = (1 << 17), - ATA_QCFLAG_EH_SCHEDULED = (1 << 18), - - ATA_HOST_SIMPLEX = (1 << 0), - ATA_HOST_STARTED = (1 << 1), + ATA_LFLAG_NO_RETRY = BIT(5), + ATA_LFLAG_DISABLED = BIT(6), + + ATA_FLAG_SLAVE_POSS = BIT(0), + ATA_FLAG_SATA = BIT(1), + ATA_FLAG_NO_LEGACY = BIT(2), + ATA_FLAG_MMIO = BIT(3), + ATA_FLAG_SRST = BIT(4), + ATA_FLAG_SATA_RESET = BIT(5), + ATA_FLAG_NO_ATAPI = BIT(6), + ATA_FLAG_PIO_DMA = BIT(7), + ATA_FLAG_PIO_LBA48 = BIT(8), + ATA_FLAG_PIO_POLLING = BIT(9), + ATA_FLAG_NCQ = BIT(10), + ATA_FLAG_DEBUGMSG = BIT(13), + ATA_FLAG_IGN_SIMPLEX = BIT(15), + ATA_FLAG_NO_IORDY = BIT(16), + ATA_FLAG_ACPI_SATA = BIT(17), + ATA_FLAG_AN = BIT(18), + ATA_FLAG_PMP = BIT(19), + ATA_FLAG_IPM = BIT(20), + + ATA_FLAG_DISABLED = BIT(23), + + ATA_PFLAG_EH_PENDING = BIT(0), + ATA_PFLAG_EH_IN_PROGRESS = BIT(1), + ATA_PFLAG_FROZEN = BIT(2), + ATA_PFLAG_RECOVERED = BIT(3), + ATA_PFLAG_LOADING = BIT(4), + ATA_PFLAG_UNLOADING = BIT(5), + ATA_PFLAG_SCSI_HOTPLUG = BIT(6), + ATA_PFLAG_INITIALIZING = BIT(7), + ATA_PFLAG_RESETTING = BIT(8), + ATA_PFLAG_SUSPENDED = BIT(17), + ATA_PFLAG_PM_PENDING = BIT(18), + + ATA_QCFLAG_ACTIVE = BIT(0), + ATA_QCFLAG_DMAMAP = BIT(1), + ATA_QCFLAG_IO = BIT(3), + ATA_QCFLAG_RESULT_TF = BIT(4), + ATA_QCFLAG_CLEAR_EXCL = BIT(5), + ATA_QCFLAG_QUIET = BIT(6), + + ATA_QCFLAG_FAILED = BIT(16), + ATA_QCFLAG_SENSE_VALID = BIT(17), + ATA_QCFLAG_EH_SCHEDULED = BIT(18), + + ATA_HOST_SIMPLEX = BIT(0), + ATA_HOST_STARTED = BIT(1), ATA_TMOUT_BOOT = 30 * 100, ATA_TMOUT_BOOT_QUICK = 7 * 100, @@ -228,25 +228,25 @@ enum { ATA_EH_DESC_LEN = 80, - ATA_EH_REVALIDATE = (1 << 0), - ATA_EH_SOFTRESET = (1 << 1), - ATA_EH_HARDRESET = (1 << 2), - ATA_EH_ENABLE_LINK = (1 << 3), - ATA_EH_LPM = (1 << 4), + ATA_EH_REVALIDATE = BIT(0), + ATA_EH_SOFTRESET = BIT(1), + ATA_EH_HARDRESET = BIT(2), + ATA_EH_ENABLE_LINK = BIT(3), + ATA_EH_LPM = BIT(4), ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET, ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE, - ATA_EHI_HOTPLUGGED = (1 << 0), - ATA_EHI_RESUME_LINK = (1 << 1), - ATA_EHI_NO_AUTOPSY = (1 << 2), - ATA_EHI_QUIET = (1 << 3), + ATA_EHI_HOTPLUGGED = BIT(0), + ATA_EHI_RESUME_LINK = BIT(1), + ATA_EHI_NO_AUTOPSY = BIT(2), + ATA_EHI_QUIET = BIT(3), - ATA_EHI_DID_SOFTRESET = (1 << 16), - ATA_EHI_DID_HARDRESET = (1 << 17), - ATA_EHI_PRINTINFO = (1 << 18), - ATA_EHI_SETMODE = (1 << 19), - ATA_EHI_POST_SETMODE = (1 << 20), + ATA_EHI_DID_SOFTRESET = BIT(16), + ATA_EHI_DID_HARDRESET = BIT(17), + ATA_EHI_PRINTINFO = BIT(18), + ATA_EHI_SETMODE = BIT(19), + ATA_EHI_POST_SETMODE = BIT(20), ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET, ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK, @@ -263,20 +263,20 @@ enum { /* Horkage types. May be set by libata or controller on drives (some horkage may be drive/controller pair dependant */ - ATA_HORKAGE_DIAGNOSTIC = (1 << 0), - ATA_HORKAGE_NODMA = (1 << 1), - ATA_HORKAGE_NONCQ = (1 << 2), - ATA_HORKAGE_MAX_SEC_128 = (1 << 3), - ATA_HORKAGE_BROKEN_HPA = (1 << 4), - ATA_HORKAGE_SKIP_PM = (1 << 5), - ATA_HORKAGE_HPA_SIZE = (1 << 6), - ATA_HORKAGE_IPM = (1 << 7), - ATA_HORKAGE_IVB = (1 << 8), - ATA_HORKAGE_STUCK_ERR = (1 << 9), - - ATA_DMA_MASK_ATA = (1 << 0), - ATA_DMA_MASK_ATAPI = (1 << 1), - ATA_DMA_MASK_CFA = (1 << 2), + ATA_HORKAGE_DIAGNOSTIC = BIT(0), + ATA_HORKAGE_NODMA = BIT(1), + ATA_HORKAGE_NONCQ = BIT(2), + ATA_HORKAGE_MAX_SEC_128 = BIT(3), + ATA_HORKAGE_BROKEN_HPA = BIT(4), + ATA_HORKAGE_SKIP_PM = BIT(5), + ATA_HORKAGE_HPA_SIZE = BIT(6), + ATA_HORKAGE_IPM = BIT(7), + ATA_HORKAGE_IVB = BIT(8), + ATA_HORKAGE_STUCK_ERR = BIT(9), + + ATA_DMA_MASK_ATA = BIT(0), + ATA_DMA_MASK_ATAPI = BIT(1), + ATA_DMA_MASK_CFA = BIT(2), ATAPI_READ = 0, ATAPI_WRITE = 1, @@ -286,17 +286,17 @@ enum { }; enum ata_completion_errors { - AC_ERR_DEV = (1 << 0), - AC_ERR_HSM = (1 << 1), - AC_ERR_TIMEOUT = (1 << 2), - AC_ERR_MEDIA = (1 << 3), - AC_ERR_ATA_BUS = (1 << 4), - AC_ERR_HOST_BUS = (1 << 5), - AC_ERR_SYSTEM = (1 << 6), - AC_ERR_INVALID = (1 << 7), - AC_ERR_OTHER = (1 << 8), - AC_ERR_NODEV_HINT = (1 << 9), - AC_ERR_NCQ = (1 << 10), + AC_ERR_DEV = BIT(0), + AC_ERR_HSM = BIT(1), + AC_ERR_TIMEOUT = BIT(2), + AC_ERR_MEDIA = BIT(3), + AC_ERR_ATA_BUS = BIT(4), + AC_ERR_HOST_BUS = BIT(5), + AC_ERR_SYSTEM = BIT(6), + AC_ERR_INVALID = BIT(7), + AC_ERR_OTHER = BIT(8), + AC_ERR_NODEV_HINT = BIT(9), + AC_ERR_NCQ = BIT(10), }; enum ata_xfer_mask { diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index daff7d4..31f6aa5 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -175,7 +175,7 @@ static int sil_cmd_set_feature(int dev) memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block)); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); pcmd->prb.fis.command = ATA_CMD_SET_FEATURES; pcmd->prb.fis.features = SETFEATURES_XFER; @@ -215,7 +215,7 @@ static int sil_cmd_identify_device(int dev, u16 *id) pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL); pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); pcmd->prb.fis.command = ATA_CMD_ID_ATA; pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id)); pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS); @@ -277,7 +277,7 @@ static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt, memset(pcmd, 0, sizeof(struct sil_cmd_block)); pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); if (is_write) { pcmd->prb.fis.command = ATA_CMD_WRITE; pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE); @@ -322,7 +322,7 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt, memset(pcmd, 0, sizeof(struct sil_cmd_block)); pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); if (is_write) { pcmd->prb.fis.command = ATA_CMD_WRITE_EXT; pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE); @@ -421,7 +421,7 @@ static void sil_sata_cmd_flush_cache(int dev) memset((void *)pcmd, 0, sizeof(struct sil_cmd_block)); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); pcmd->prb.fis.command = ATA_CMD_FLUSH; sil_exec_cmd(dev, pcmd, 0); @@ -433,7 +433,7 @@ static void sil_sata_cmd_flush_cache_ext(int dev) memset((void *)pcmd, 0, sizeof(struct sil_cmd_block)); pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; - pcmd->prb.fis.pm_port_c = (1 << 7); + pcmd->prb.fis.pm_port_c = BIT(7); pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT; sil_exec_cmd(dev, pcmd, 0); diff --git a/drivers/block/sata_sil.h b/drivers/block/sata_sil.h index 55954ef..0333cd0 100644 --- a/drivers/block/sata_sil.h +++ b/drivers/block/sata_sil.h @@ -79,15 +79,15 @@ enum { HOST_I2C_CTRL = 0x7f, /* HOST_SLOT_STAT bits */ - HOST_SSTAT_ATTN = (1 << 31), + HOST_SSTAT_ATTN = BIT(31), /* HOST_CTRL bits */ - HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ - HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ - HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ - HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ - HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ - HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ + HOST_CTRL_M66EN = BIT(16), /* M66EN PCI bus signal */ + HOST_CTRL_TRDY = BIT(17), /* latched PCI TRDY */ + HOST_CTRL_STOP = BIT(18), /* latched PCI STOP */ + HOST_CTRL_DEVSEL = BIT(19), /* latched PCI DEVSEL */ + HOST_CTRL_REQ64 = BIT(20), /* latched PCI REQ64 */ + HOST_CTRL_GLOBAL_RST = BIT(31), /* global reset */ /* * Port registers @@ -136,30 +136,30 @@ enum { PORT_SACTIVE = 0x1f0c, /* PORT_CTRL_STAT bits */ - PORT_CS_PORT_RST = (1 << 0), /* port reset */ - PORT_CS_DEV_RST = (1 << 1), /* device reset */ - PORT_CS_INIT = (1 << 2), /* port initialize */ - PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ - PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ - PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ - PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ - PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ - PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ + PORT_CS_PORT_RST = BIT(0), /* port reset */ + PORT_CS_DEV_RST = BIT(1), /* device reset */ + PORT_CS_INIT = BIT(2), /* port initialize */ + PORT_CS_IRQ_WOC = BIT(3), /* interrupt write one to clear */ + PORT_CS_CDB16 = BIT(5), /* 0=12b cdb, 1=16b cdb */ + PORT_CS_PMP_RESUME = BIT(6), /* PMP resume */ + PORT_CS_32BIT_ACTV = BIT(10), /* 32-bit activation */ + PORT_CS_PMP_EN = BIT(13), /* port multiplier enable */ + PORT_CS_RDY = BIT(31), /* port ready to accept commands */ /* PORT_IRQ_STAT/ENABLE_SET/CLR */ /* bits[11:0] are masked */ - PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ - PORT_IRQ_ERROR = (1 << 1), /* command execution error */ - PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ - PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ - PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ - PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ - PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ - PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ - PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ - PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ - PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ - PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ + PORT_IRQ_COMPLETE = BIT(0), /* command(s) completed */ + PORT_IRQ_ERROR = BIT(1), /* command execution error */ + PORT_IRQ_PORTRDY_CHG = BIT(2), /* port ready change */ + PORT_IRQ_PWR_CHG = BIT(3), /* power management change */ + PORT_IRQ_PHYRDY_CHG = BIT(4), /* PHY ready change */ + PORT_IRQ_COMWAKE = BIT(5), /* COMWAKE received */ + PORT_IRQ_UNK_FIS = BIT(6), /* unknown FIS received */ + PORT_IRQ_DEV_XCHG = BIT(7), /* device exchanged */ + PORT_IRQ_8B10B = BIT(8), /* 8b/10b decode error threshold */ + PORT_IRQ_CRC = BIT(9), /* CRC error threshold */ + PORT_IRQ_HANDSHAKE = BIT(10), /* handshake error threshold */ + PORT_IRQ_SDB_NOTIFY = BIT(11), /* SDB notify received */ DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | @@ -185,27 +185,27 @@ enum { PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ /* bits of PRB control field */ - PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ - PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ - PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ - PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ - PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ + PRB_CTRL_PROTOCOL = BIT(0), /* override def. ATA protocol */ + PRB_CTRL_PACKET_READ = BIT(4), /* PACKET cmd read */ + PRB_CTRL_PACKET_WRITE = BIT(5), /* PACKET cmd write */ + PRB_CTRL_NIEN = BIT(6), /* Mask completion irq */ + PRB_CTRL_SRST = BIT(7), /* Soft reset request (ign BSY?) */ /* PRB protocol field */ - PRB_PROT_PACKET = (1 << 0), - PRB_PROT_TCQ = (1 << 1), - PRB_PROT_NCQ = (1 << 2), - PRB_PROT_READ = (1 << 3), - PRB_PROT_WRITE = (1 << 4), - PRB_PROT_TRANSPARENT = (1 << 5), + PRB_PROT_PACKET = BIT(0), + PRB_PROT_TCQ = BIT(1), + PRB_PROT_NCQ = BIT(2), + PRB_PROT_READ = BIT(3), + PRB_PROT_WRITE = BIT(4), + PRB_PROT_TRANSPARENT = BIT(5), /* * Other constants */ - SGE_TRM = (1 << 31), /* Last SGE in chain */ - SGE_LNK = (1 << 30), /* linked list + SGE_TRM = BIT(31), /* Last SGE in chain */ + SGE_LNK = BIT(30), /* linked list Points to SGT, not SGE */ - SGE_DRD = (1 << 29), /* discard data read (/dev/null) + SGE_DRD = BIT(29), /* discard data read (/dev/null) data address ignored */ CMD_ERR = 0x21, diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c index 61ffb66..78d12a3 100644 --- a/drivers/block/sata_sil3114.c +++ b/drivers/block/sata_sil3114.c @@ -161,7 +161,7 @@ static void sata_identify (int num, int dev) debug("lba=0x%lx\n", sata_dev_desc[devno].lba); #ifdef CONFIG_LBA48 - if (iobuf[83] & (1 << 10)) { + if (iobuf[83] & BIT(10)) { sata_dev_desc[devno].lba48 = 1; } else { sata_dev_desc[devno].lba48 = 0; diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index f1097f7..8f4bc8f 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -81,49 +81,49 @@ struct exynos_ace_sfr { }; /* ACE_FC_INT */ -#define ACE_FC_PKDMA (1 << 0) -#define ACE_FC_HRDMA (1 << 1) -#define ACE_FC_BTDMA (1 << 2) -#define ACE_FC_BRDMA (1 << 3) -#define ACE_FC_PRNG_ERROR (1 << 4) -#define ACE_FC_MSG_DONE (1 << 5) -#define ACE_FC_PRNG_DONE (1 << 6) -#define ACE_FC_PARTIAL_DONE (1 << 7) +#define ACE_FC_PKDMA BIT(0) +#define ACE_FC_HRDMA BIT(1) +#define ACE_FC_BTDMA BIT(2) +#define ACE_FC_BRDMA BIT(3) +#define ACE_FC_PRNG_ERROR BIT(4) +#define ACE_FC_MSG_DONE BIT(5) +#define ACE_FC_PRNG_DONE BIT(6) +#define ACE_FC_PARTIAL_DONE BIT(7) /* ACE_FC_FIFOSTAT */ -#define ACE_FC_PKFIFO_EMPTY (1 << 0) -#define ACE_FC_PKFIFO_FULL (1 << 1) -#define ACE_FC_HRFIFO_EMPTY (1 << 2) -#define ACE_FC_HRFIFO_FULL (1 << 3) -#define ACE_FC_BTFIFO_EMPTY (1 << 4) -#define ACE_FC_BTFIFO_FULL (1 << 5) -#define ACE_FC_BRFIFO_EMPTY (1 << 6) -#define ACE_FC_BRFIFO_FULL (1 << 7) +#define ACE_FC_PKFIFO_EMPTY BIT(0) +#define ACE_FC_PKFIFO_FULL BIT(1) +#define ACE_FC_HRFIFO_EMPTY BIT(2) +#define ACE_FC_HRFIFO_FULL BIT(3) +#define ACE_FC_BTFIFO_EMPTY BIT(4) +#define ACE_FC_BTFIFO_FULL BIT(5) +#define ACE_FC_BRFIFO_EMPTY BIT(6) +#define ACE_FC_BRFIFO_FULL BIT(7) /* ACE_FC_FIFOCTRL */ #define ACE_FC_SELHASH_MASK (3 << 0) #define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */ -#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */ +#define ACE_FC_SELHASH_BCIN BIT(0) /* blk cipher input */ #define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */ -#define ACE_FC_SELBC_MASK (1 << 2) +#define ACE_FC_SELBC_MASK BIT(2) #define ACE_FC_SELBC_AES (0 << 2) -#define ACE_FC_SELBC_DES (1 << 2) +#define ACE_FC_SELBC_DES BIT(2) /* ACE_FC_GLOBAL */ -#define ACE_FC_SSS_RESET (1 << 0) -#define ACE_FC_DMA_RESET (1 << 1) -#define ACE_FC_AES_RESET (1 << 2) -#define ACE_FC_DES_RESET (1 << 3) -#define ACE_FC_HASH_RESET (1 << 4) +#define ACE_FC_SSS_RESET BIT(0) +#define ACE_FC_DMA_RESET BIT(1) +#define ACE_FC_AES_RESET BIT(2) +#define ACE_FC_DES_RESET BIT(3) +#define ACE_FC_HASH_RESET BIT(4) #define ACE_FC_AXI_ENDIAN_MASK (3 << 6) #define ACE_FC_AXI_ENDIAN_LE (0 << 6) -#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6) +#define ACE_FC_AXI_ENDIAN_BIBE BIT(6) #define ACE_FC_AXI_ENDIAN_WIBE (2 << 6) /* Feed control - BRDMA control */ #define ACE_FC_BRDMACFLUSH_OFF (0 << 0) -#define ACE_FC_BRDMACFLUSH_ON (1 << 0) -#define ACE_FC_BRDMACSWAP_ON (1 << 1) +#define ACE_FC_BRDMACFLUSH_ON BIT(0) +#define ACE_FC_BRDMACSWAP_ON BIT(1) #define ACE_FC_BRDMACARPROT_MASK (0x7 << 2) #define ACE_FC_BRDMACARPROT_OFS 2 #define ACE_FC_BRDMACARCACHE_MASK (0xf << 5) @@ -131,8 +131,8 @@ struct exynos_ace_sfr { /* Feed control - BTDMA control */ #define ACE_FC_BTDMACFLUSH_OFF (0 << 0) -#define ACE_FC_BTDMACFLUSH_ON (1 << 0) -#define ACE_FC_BTDMACSWAP_ON (1 << 1) +#define ACE_FC_BTDMACFLUSH_ON BIT(0) +#define ACE_FC_BTDMACSWAP_ON BIT(1) #define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2) #define ACE_FC_BTDMACAWPROT_OFS 2 #define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5) @@ -140,102 +140,102 @@ struct exynos_ace_sfr { /* Feed control - HRDMA control */ #define ACE_FC_HRDMACFLUSH_OFF (0 << 0) -#define ACE_FC_HRDMACFLUSH_ON (1 << 0) -#define ACE_FC_HRDMACSWAP_ON (1 << 1) +#define ACE_FC_HRDMACFLUSH_ON BIT(0) +#define ACE_FC_HRDMACSWAP_ON BIT(1) #define ACE_FC_HRDMACARPROT_MASK (0x7 << 2) #define ACE_FC_HRDMACARPROT_OFS 2 #define ACE_FC_HRDMACARCACHE_MASK (0xf << 5) #define ACE_FC_HRDMACARCACHE_OFS 5 /* Feed control - PKDMA control */ -#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3) -#define ACE_FC_PKDMACDESEND_ON (1 << 2) -#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1) -#define ACE_FC_PKDMACFLUSH_ON (1 << 0) +#define ACE_FC_PKDMACBYTESWAP_ON BIT(3) +#define ACE_FC_PKDMACDESEND_ON BIT(2) +#define ACE_FC_PKDMACTRANSMIT_ON BIT(1) +#define ACE_FC_PKDMACFLUSH_ON BIT(0) /* Feed control - PKDMA offset */ #define ACE_FC_SRAMOFFSET_MASK 0xfff /* AES control */ -#define ACE_AES_MODE_MASK (1 << 0) +#define ACE_AES_MODE_MASK BIT(0) #define ACE_AES_MODE_ENC (0 << 0) -#define ACE_AES_MODE_DEC (1 << 0) +#define ACE_AES_MODE_DEC BIT(0) #define ACE_AES_OPERMODE_MASK (3 << 1) #define ACE_AES_OPERMODE_ECB (0 << 1) -#define ACE_AES_OPERMODE_CBC (1 << 1) +#define ACE_AES_OPERMODE_CBC BIT(1) #define ACE_AES_OPERMODE_CTR (2 << 1) -#define ACE_AES_FIFO_MASK (1 << 3) +#define ACE_AES_FIFO_MASK BIT(3) #define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */ -#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */ +#define ACE_AES_FIFO_ON BIT(3) /* FIFO mode */ #define ACE_AES_KEYSIZE_MASK (3 << 4) #define ACE_AES_KEYSIZE_128 (0 << 4) -#define ACE_AES_KEYSIZE_192 (1 << 4) +#define ACE_AES_KEYSIZE_192 BIT(4) #define ACE_AES_KEYSIZE_256 (2 << 4) -#define ACE_AES_KEYCNGMODE_MASK (1 << 6) +#define ACE_AES_KEYCNGMODE_MASK BIT(6) #define ACE_AES_KEYCNGMODE_OFF (0 << 6) -#define ACE_AES_KEYCNGMODE_ON (1 << 6) +#define ACE_AES_KEYCNGMODE_ON BIT(6) #define ACE_AES_SWAP_MASK (0x1f << 7) #define ACE_AES_SWAPKEY_OFF (0 << 7) -#define ACE_AES_SWAPKEY_ON (1 << 7) +#define ACE_AES_SWAPKEY_ON BIT(7) #define ACE_AES_SWAPCNT_OFF (0 << 8) -#define ACE_AES_SWAPCNT_ON (1 << 8) +#define ACE_AES_SWAPCNT_ON BIT(8) #define ACE_AES_SWAPIV_OFF (0 << 9) -#define ACE_AES_SWAPIV_ON (1 << 9) +#define ACE_AES_SWAPIV_ON BIT(9) #define ACE_AES_SWAPDO_OFF (0 << 10) -#define ACE_AES_SWAPDO_ON (1 << 10) +#define ACE_AES_SWAPDO_ON BIT(10) #define ACE_AES_SWAPDI_OFF (0 << 11) -#define ACE_AES_SWAPDI_ON (1 << 11) +#define ACE_AES_SWAPDI_ON BIT(11) #define ACE_AES_COUNTERSIZE_MASK (3 << 12) #define ACE_AES_COUNTERSIZE_128 (0 << 12) -#define ACE_AES_COUNTERSIZE_64 (1 << 12) +#define ACE_AES_COUNTERSIZE_64 BIT(12) #define ACE_AES_COUNTERSIZE_32 (2 << 12) #define ACE_AES_COUNTERSIZE_16 (3 << 12) /* AES status */ -#define ACE_AES_OUTRDY_MASK (1 << 0) +#define ACE_AES_OUTRDY_MASK BIT(0) #define ACE_AES_OUTRDY_OFF (0 << 0) -#define ACE_AES_OUTRDY_ON (1 << 0) -#define ACE_AES_INRDY_MASK (1 << 1) +#define ACE_AES_OUTRDY_ON BIT(0) +#define ACE_AES_INRDY_MASK BIT(1) #define ACE_AES_INRDY_OFF (0 << 1) -#define ACE_AES_INRDY_ON (1 << 1) -#define ACE_AES_BUSY_MASK (1 << 2) +#define ACE_AES_INRDY_ON BIT(1) +#define ACE_AES_BUSY_MASK BIT(2) #define ACE_AES_BUSY_OFF (0 << 2) -#define ACE_AES_BUSY_ON (1 << 2) +#define ACE_AES_BUSY_ON BIT(2) /* TDES control */ -#define ACE_TDES_MODE_MASK (1 << 0) +#define ACE_TDES_MODE_MASK BIT(0) #define ACE_TDES_MODE_ENC (0 << 0) -#define ACE_TDES_MODE_DEC (1 << 0) -#define ACE_TDES_OPERMODE_MASK (1 << 1) +#define ACE_TDES_MODE_DEC BIT(0) +#define ACE_TDES_OPERMODE_MASK BIT(1) #define ACE_TDES_OPERMODE_ECB (0 << 1) -#define ACE_TDES_OPERMODE_CBC (1 << 1) +#define ACE_TDES_OPERMODE_CBC BIT(1) #define ACE_TDES_SEL_MASK (3 << 3) #define ACE_TDES_SEL_DES (0 << 3) -#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */ +#define ACE_TDES_SEL_TDESEDE BIT(3) /* TDES EDE mode */ #define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */ -#define ACE_TDES_FIFO_MASK (1 << 5) +#define ACE_TDES_FIFO_MASK BIT(5) #define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */ -#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */ +#define ACE_TDES_FIFO_ON BIT(5) /* FIFO mode */ #define ACE_TDES_SWAP_MASK (0xf << 6) #define ACE_TDES_SWAPKEY_OFF (0 << 6) -#define ACE_TDES_SWAPKEY_ON (1 << 6) +#define ACE_TDES_SWAPKEY_ON BIT(6) #define ACE_TDES_SWAPIV_OFF (0 << 7) -#define ACE_TDES_SWAPIV_ON (1 << 7) +#define ACE_TDES_SWAPIV_ON BIT(7) #define ACE_TDES_SWAPDO_OFF (0 << 8) -#define ACE_TDES_SWAPDO_ON (1 << 8) +#define ACE_TDES_SWAPDO_ON BIT(8) #define ACE_TDES_SWAPDI_OFF (0 << 9) -#define ACE_TDES_SWAPDI_ON (1 << 9) +#define ACE_TDES_SWAPDI_ON BIT(9) /* TDES status */ -#define ACE_TDES_OUTRDY_MASK (1 << 0) +#define ACE_TDES_OUTRDY_MASK BIT(0) #define ACE_TDES_OUTRDY_OFF (0 << 0) -#define ACE_TDES_OUTRDY_ON (1 << 0) -#define ACE_TDES_INRDY_MASK (1 << 1) +#define ACE_TDES_OUTRDY_ON BIT(0) +#define ACE_TDES_INRDY_MASK BIT(1) #define ACE_TDES_INRDY_OFF (0 << 1) -#define ACE_TDES_INRDY_ON (1 << 1) -#define ACE_TDES_BUSY_MASK (1 << 2) +#define ACE_TDES_INRDY_ON BIT(1) +#define ACE_TDES_BUSY_MASK BIT(2) #define ACE_TDES_BUSY_OFF (0 << 2) -#define ACE_TDES_BUSY_ON (1 << 2) +#define ACE_TDES_BUSY_ON BIT(2) /* Hash control */ #define ACE_HASH_ENGSEL_MASK (0xf << 0) @@ -250,48 +250,48 @@ struct exynos_ace_sfr { #define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0) #define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0) #define ACE_HASH_ENGSEL_PRNG (0x8 << 0) -#define ACE_HASH_STARTBIT_ON (1 << 4) -#define ACE_HASH_USERIV_EN (1 << 5) -#define ACE_HASH_PAUSE_ON (1 << 0) +#define ACE_HASH_STARTBIT_ON BIT(4) +#define ACE_HASH_USERIV_EN BIT(5) +#define ACE_HASH_PAUSE_ON BIT(0) /* Hash control - FIFO mode */ -#define ACE_HASH_FIFO_MASK (1 << 0) +#define ACE_HASH_FIFO_MASK BIT(0) #define ACE_HASH_FIFO_OFF (0 << 0) -#define ACE_HASH_FIFO_ON (1 << 0) +#define ACE_HASH_FIFO_ON BIT(0) /* Hash control - byte swap */ #define ACE_HASH_SWAP_MASK (0xf << 0) #define ACE_HASH_SWAPKEY_OFF (0 << 0) -#define ACE_HASH_SWAPKEY_ON (1 << 0) +#define ACE_HASH_SWAPKEY_ON BIT(0) #define ACE_HASH_SWAPIV_OFF (0 << 1) -#define ACE_HASH_SWAPIV_ON (1 << 1) +#define ACE_HASH_SWAPIV_ON BIT(1) #define ACE_HASH_SWAPDO_OFF (0 << 2) -#define ACE_HASH_SWAPDO_ON (1 << 2) +#define ACE_HASH_SWAPDO_ON BIT(2) #define ACE_HASH_SWAPDI_OFF (0 << 3) -#define ACE_HASH_SWAPDI_ON (1 << 3) +#define ACE_HASH_SWAPDI_ON BIT(3) /* Hash status */ -#define ACE_HASH_BUFRDY_MASK (1 << 0) +#define ACE_HASH_BUFRDY_MASK BIT(0) #define ACE_HASH_BUFRDY_OFF (0 << 0) -#define ACE_HASH_BUFRDY_ON (1 << 0) -#define ACE_HASH_SEEDSETTING_MASK (1 << 1) +#define ACE_HASH_BUFRDY_ON BIT(0) +#define ACE_HASH_SEEDSETTING_MASK BIT(1) #define ACE_HASH_SEEDSETTING_OFF (0 << 1) -#define ACE_HASH_SEEDSETTING_ON (1 << 1) -#define ACE_HASH_PRNGBUSY_MASK (1 << 2) +#define ACE_HASH_SEEDSETTING_ON BIT(1) +#define ACE_HASH_PRNGBUSY_MASK BIT(2) #define ACE_HASH_PRNGBUSY_OFF (0 << 2) -#define ACE_HASH_PRNGBUSY_ON (1 << 2) -#define ACE_HASH_PARTIALDONE_MASK (1 << 4) +#define ACE_HASH_PRNGBUSY_ON BIT(2) +#define ACE_HASH_PARTIALDONE_MASK BIT(4) #define ACE_HASH_PARTIALDONE_OFF (0 << 4) -#define ACE_HASH_PARTIALDONE_ON (1 << 4) -#define ACE_HASH_PRNGDONE_MASK (1 << 5) +#define ACE_HASH_PARTIALDONE_ON BIT(4) +#define ACE_HASH_PRNGDONE_MASK BIT(5) #define ACE_HASH_PRNGDONE_OFF (0 << 5) -#define ACE_HASH_PRNGDONE_ON (1 << 5) -#define ACE_HASH_MSGDONE_MASK (1 << 6) +#define ACE_HASH_PRNGDONE_ON BIT(5) +#define ACE_HASH_MSGDONE_MASK BIT(6) #define ACE_HASH_MSGDONE_OFF (0 << 6) -#define ACE_HASH_MSGDONE_ON (1 << 6) -#define ACE_HASH_PRNGERROR_MASK (1 << 7) +#define ACE_HASH_MSGDONE_ON BIT(6) +#define ACE_HASH_PRNGERROR_MASK BIT(7) #define ACE_HASH_PRNGERROR_OFF (0 << 7) -#define ACE_HASH_PRNGERROR_ON (1 << 7) +#define ACE_HASH_PRNGERROR_ON BIT(7) #define ACE_HASH_PRNG_REG_NUM 5 #define ACE_SHA_TYPE_SHA1 1 diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 18e2ec8..28cc5a4 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -251,8 +251,8 @@ #define LDOFF_CHG_SHARE_OK_PROP (0x2 << LDOFF_CHG_SHARE_SHIFT) #define LDOFF_CHG_SHARE_OK_NO_PROP (0x3 << LDOFF_CHG_SHARE_SHIFT) -#define LDOFF_ENABLE_AUTO_NFIFO (1 << 2) -#define LDOFF_DISABLE_AUTO_NFIFO (1 << 3) +#define LDOFF_ENABLE_AUTO_NFIFO BIT(2) +#define LDOFF_DISABLE_AUTO_NFIFO BIT(3) #define LDOFF_CHG_NONSEQLIODN_SHIFT 4 #define LDOFF_CHG_NONSEQLIODN_MASK (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) @@ -271,11 +271,11 @@ #define LDST_LEN_MASK (0xff << LDST_LEN_SHIFT) /* Special Length definitions when dst=deco-ctrl */ -#define LDLEN_ENABLE_OSL_COUNT (1 << 7) -#define LDLEN_RST_CHA_OFIFO_PTR (1 << 6) -#define LDLEN_RST_OFIFO (1 << 5) -#define LDLEN_SET_OFIFO_OFF_VALID (1 << 4) -#define LDLEN_SET_OFIFO_OFF_RSVD (1 << 3) +#define LDLEN_ENABLE_OSL_COUNT BIT(7) +#define LDLEN_RST_CHA_OFIFO_PTR BIT(6) +#define LDLEN_RST_OFIFO BIT(5) +#define LDLEN_SET_OFIFO_OFF_VALID BIT(4) +#define LDLEN_SET_OFIFO_OFF_RSVD BIT(3) #define LDLEN_SET_OFIFO_OFFSET_SHIFT 0 #define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index f9cae91..6af458d 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -11,7 +11,7 @@ #include #include "desc.h" -#define IMMEDIATE (1 << 23) +#define IMMEDIATE BIT(23) #define CAAM_CMD_SZ sizeof(u32) #define CAAM_PTR_SZ sizeof(dma_addr_t) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) diff --git a/drivers/ddr/mvebu/ddr3_dfs.c b/drivers/ddr/mvebu/ddr3_dfs.c index 9347773..6a43435 100644 --- a/drivers/ddr/mvebu/ddr3_dfs.c +++ b/drivers/ddr/mvebu/ddr3_dfs.c @@ -527,7 +527,7 @@ int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ - reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); /* [0] - disable */ + reg = reg_read(REG_METAL_MASK_ADDR) & ~BIT(0); /* [0] - disable */ /* 0x14B0 - Dunit MMask Register */ dfs_reg_write(REG_METAL_MASK_ADDR, reg); @@ -681,7 +681,7 @@ int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) /* Config CL and CWL with MR0 and MR2 registers */ reg = reg_read(REG_DDR3_MR0_ADDR); reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ - reg |= (1 << 5); /* CL = 4, CAS is 6 */ + reg |= BIT(5); /* CL = 4, CAS is 6 */ dfs_reg_write(REG_DDR3_MR0_ADDR, reg); reg = REG_SDRAM_OPERATION_CMD_MR0 & ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); @@ -693,7 +693,7 @@ int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) reg = reg_read(REG_DDR3_MR2_ADDR); reg &= ~0x38; /* CWL [5:3] */ - reg |= (1 << 3); /* CWL = 1, CWL is 6 */ + reg |= BIT(3); /* CWL = 1, CWL is 6 */ dfs_reg_write(REG_DDR3_MR2_ADDR, reg); reg = REG_SDRAM_OPERATION_CMD_MR2 & @@ -737,7 +737,7 @@ int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); } while (reg); /* Wait for '1' */ - reg = (reg_read(REG_METAL_MASK_ADDR) | (1 << 0)); + reg = (reg_read(REG_METAL_MASK_ADDR) | BIT(0)); /* [0] - Enable Dunit to crossbar retry */ /* 0x14B0 - Dunit MMask Register */ dfs_reg_write(REG_METAL_MASK_ADDR, reg); @@ -1228,7 +1228,7 @@ int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) /* Disable DRAM Controller to crossbar retry */ /* [0] - disable */ - reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); + reg = reg_read(REG_METAL_MASK_ADDR) & ~BIT(0); /* 0x14B0 - Dunit MMask Register */ dfs_reg_write(REG_METAL_MASK_ADDR, reg); @@ -1352,9 +1352,9 @@ int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) if (ratio_2to1) { /* Pup Reset Divider B - Set Reset */ /* [28] = 0 - Pup Reset Divider B */ - reg = reg_read(REG_SDRAM_CONFIG_ADDR) & ~(1 << 28); + reg = reg_read(REG_SDRAM_CONFIG_ADDR) & ~BIT(28); /* [28] = 1 - Pup Reset Divider B */ - tmp = reg_read(REG_SDRAM_CONFIG_ADDR) | (1 << 28); + tmp = reg_read(REG_SDRAM_CONFIG_ADDR) | BIT(28); /* 0x1400 - SDRAM Configuration register */ dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); @@ -1406,7 +1406,7 @@ int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); /* Disable DFS Reconfig */ - reg = reg_read(REG_DFS_ADDR) & ~(1 << 4); + reg = reg_read(REG_DFS_ADDR) & ~BIT(4); dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ /* [2] - DFS Self refresh disable */ @@ -1541,7 +1541,7 @@ int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); - reg = reg_read(REG_METAL_MASK_ADDR) | (1 << 0); /* [0] - disable */ + reg = reg_read(REG_METAL_MASK_ADDR) | BIT(0); /* [0] - disable */ /* 0x14B0 - Dunit MMask Register */ dfs_reg_write(REG_METAL_MASK_ADDR, reg); diff --git a/drivers/ddr/mvebu/ddr3_init.c b/drivers/ddr/mvebu/ddr3_init.c index 11b8591..b496489 100644 --- a/drivers/ddr/mvebu/ddr3_init.c +++ b/drivers/ddr/mvebu/ddr3_init.c @@ -245,7 +245,7 @@ static void ddr3_save_and_set_training_windows(u32 *win_backup) reg = 0x0700; break; } - reg |= (1 << 0); + reg |= BIT(0); reg |= (SDRAM_CS_SIZE & 0xFFFF0000); reg_write(win_ctrl_reg + win_jump_index * tmp_count, @@ -392,7 +392,7 @@ static u32 ddr3_init_main(void) /* Power down deskew PLL */ #if !defined(MV88F672X) /* 0x18780 [25] */ - reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25)); + reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~BIT(25)); reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg); #endif @@ -661,7 +661,7 @@ static u32 ddr3_init_main(void) if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) { reg = reg_read(REG_SDRAM_CONFIG_ADDR); if (ecc == 0) - reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19)); + reg_write(REG_SDRAM_CONFIG_ADDR, reg | BIT(19)); } #endif /* end defined(MV88F78X60) */ diff --git a/drivers/ddr/mvebu/ddr3_sdram.c b/drivers/ddr/mvebu/ddr3_sdram.c index 50c1bf8..8737777 100644 --- a/drivers/ddr/mvebu/ddr3_sdram.c +++ b/drivers/ddr/mvebu/ddr3_sdram.c @@ -510,14 +510,14 @@ int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len) /* src is DRAM CS, dst is SRAM */ cs_num = (src / (1 + SDRAM_CS_SIZE)); reg_write(XOR_ADDR_OVRD_REG(0, 0), - ((cs_num << 1) | (1 << 0))); + ((cs_num << 1) | BIT(0))); channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE)); channel.desc->dst_addr = dst; } else { /* src is SRAM, dst is DRAM CS */ cs_num = (dst / (1 + SDRAM_CS_SIZE)); reg_write(XOR_ADDR_OVRD_REG(0, 0), - ((cs_num << 25) | (1 << 24))); + ((cs_num << 25) | BIT(24))); channel.desc->src_addr0 = (src); channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE)); channel.desc->src_addr0 = src; diff --git a/drivers/ddr/mvebu/ddr3_spd.c b/drivers/ddr/mvebu/ddr3_spd.c index f4f94c5..f6a9f1c 100644 --- a/drivers/ddr/mvebu/ddr3_spd.c +++ b/drivers/ddr/mvebu/ddr3_spd.c @@ -769,10 +769,10 @@ int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) reg |= tmp; if (cl != 3) - reg |= (1 << 16); /* If 2:1 need to set P2DWr */ + reg |= BIT(16); /* If 2:1 need to set P2DWr */ #if defined(MV88F672X) - reg |= (1 << 27); /* PhyRfRST = Disable */ + reg |= BIT(27); /* PhyRfRST = Disable */ #endif reg_write(REG_SDRAM_CONFIG_ADDR, reg); @@ -996,7 +996,7 @@ int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) #if (defined(MV88F78X60) || defined(MV88F672X)) /*{0x000014CC} - DRAM Main Pads Calibration Machine Control Register */ reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR); - reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg | (1 << 0)); + reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg | BIT(0)); #endif #if defined(MV88F672X) @@ -1004,7 +1004,7 @@ int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) /* 0x14CC[4:3] - CalUpdateControl = IntOnly */ reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR); reg &= 0xFFFFFFE7; - reg |= (1 << 3); + reg |= BIT(3); reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg); #endif diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index da0199b..77e9767 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -38,8 +38,8 @@ #define GPIO_INT_LOW_LEV 0x1 #define GPIO_INT_RISE_EDGE 0x2 #define GPIO_INT_HIGH_LEV 0x3 -#define GPIO_INT_LEV_MASK (1 << 0) -#define GPIO_INT_POL_MASK (1 << 1) +#define GPIO_INT_LEV_MASK BIT(0) +#define GPIO_INT_POL_MASK BIT(1) void mxs_gpio_init(void) { diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index a9b1efc..04a4fa4 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -13,8 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Flags for each GPIO */ -#define GPIOF_OUTPUT (1 << 0) /* Currently set as an output */ -#define GPIOF_HIGH (1 << 1) /* Currently set high */ +#define GPIOF_OUTPUT BIT(0) /* Currently set as an output */ +#define GPIOF_HIGH BIT(1) /* Currently set high */ struct gpio_state { const char *label; /* label given by requester */ diff --git a/drivers/i2c/davinci_i2c.h b/drivers/i2c/davinci_i2c.h index 20d4342..75417a1 100644 --- a/drivers/i2c/davinci_i2c.h +++ b/drivers/i2c/davinci_i2c.h @@ -31,25 +31,25 @@ struct i2c_regs { /* I2C masks */ /* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_IE_SCD_IE BIT(5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE BIT(4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE BIT(3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE BIT(2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE BIT(1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE BIT(0) /* Arbitration lost interrupt enable */ /* I2C Status Register (I2C_STAT): */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_STAT_BB BIT(12) /* Bus busy */ +#define I2C_STAT_ROVR BIT(11) /* Receive overrun */ +#define I2C_STAT_XUDF BIT(10) /* Transmit underflow */ +#define I2C_STAT_AAS BIT(9) /* Address as slave */ +#define I2C_STAT_SCD BIT(5) /* Stop condition detect */ +#define I2C_STAT_XRDY BIT(4) /* Transmit data ready */ +#define I2C_STAT_RRDY BIT(3) /* Receive data ready */ +#define I2C_STAT_ARDY BIT(2) /* Register access ready */ +#define I2C_STAT_NACK BIT(1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL BIT(0) /* Arbitration lost interrupt enable */ /* I2C Interrupt Code Register (I2C_INTCODE): */ @@ -64,14 +64,14 @@ struct i2c_regs { /* I2C Configuration Register (I2C_CON): */ -#define I2C_CON_EN (1 << 5) /* I2C module enable */ -#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ -#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ +#define I2C_CON_EN BIT(5) /* I2C module enable */ +#define I2C_CON_STB BIT(4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST BIT(10) /* Master/slave mode */ +#define I2C_CON_TRX BIT(9) /* Tx/Rx mode (master mode only) */ +#define I2C_CON_XA BIT(8) /* Expand address */ +#define I2C_CON_STP BIT(11) /* Stop condition (master mode only) */ +#define I2C_CON_STT BIT(13) /* Start condition (master mode only) */ +#define I2C_CON_FREE BIT(14) /* Free run on emulation */ #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c index d29dd45..c67bd09 100644 --- a/drivers/i2c/i2c-uniphier-f.c +++ b/drivers/i2c/i2c-uniphier-f.c @@ -20,14 +20,14 @@ DECLARE_GLOBAL_DATA_PTR; struct uniphier_fi2c_regs { u32 cr; /* control register */ -#define I2C_CR_MST (1 << 3) /* master mode */ -#define I2C_CR_STA (1 << 2) /* start condition */ -#define I2C_CR_STO (1 << 1) /* stop condition */ -#define I2C_CR_NACK (1 << 0) /* not ACK */ +#define I2C_CR_MST BIT(3) /* master mode */ +#define I2C_CR_STA BIT(2) /* start condition */ +#define I2C_CR_STO BIT(1) /* stop condition */ +#define I2C_CR_NACK BIT(0) /* not ACK */ u32 dttx; /* send FIFO (write-only) */ #define dtrx dttx /* receive FIFO (read-only) */ -#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */ -#define I2C_DTTX_RD (1 << 0) /* read */ +#define I2C_DTTX_CMD BIT(8) /* send command (slave addr) */ +#define I2C_DTTX_RD BIT(0) /* read */ u32 __reserved; /* no register at offset 0x08 */ u32 slad; /* slave address */ u32 cyc; /* clock cycle control */ @@ -37,22 +37,22 @@ struct uniphier_fi2c_regs { u32 intr; /* interrupt status */ u32 ie; /* interrupt enable */ u32 ic; /* interrupt clear */ -#define I2C_INT_TE (1 << 9) /* TX FIFO empty */ -#define I2C_INT_RB (1 << 4) /* received specified bytes */ -#define I2C_INT_NA (1 << 2) /* no answer */ -#define I2C_INT_AL (1 << 1) /* arbitration lost */ +#define I2C_INT_TE BIT(9) /* TX FIFO empty */ +#define I2C_INT_RB BIT(4) /* received specified bytes */ +#define I2C_INT_NA BIT(2) /* no answer */ +#define I2C_INT_AL BIT(1) /* arbitration lost */ u32 sr; /* status register */ -#define I2C_SR_DB (1 << 12) /* device busy */ -#define I2C_SR_BB (1 << 8) /* bus busy */ -#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */ -#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */ -#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */ -#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */ +#define I2C_SR_DB BIT(12) /* device busy */ +#define I2C_SR_BB BIT(8) /* bus busy */ +#define I2C_SR_RFF BIT(3) /* Rx FIFO full */ +#define I2C_SR_RNE BIT(2) /* Rx FIFO not empty */ +#define I2C_SR_TNF BIT(1) /* Tx FIFO not full */ +#define I2C_SR_TFE BIT(0) /* Tx FIFO empty */ u32 __reserved2; /* no register at offset 0x30 */ u32 rst; /* reset control */ -#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */ -#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */ -#define I2C_RST_RST (1 << 0) /* forcible bus reset */ +#define I2C_RST_TBRST BIT(2) /* clear Tx FIFO */ +#define I2C_RST_RBRST BIT(1) /* clear Rx FIFO */ +#define I2C_RST_RST BIT(0) /* forcible bus reset */ u32 bm; /* bus monitor */ u32 noise; /* noise filter control */ u32 tbc; /* Tx byte count setting */ @@ -60,8 +60,8 @@ struct uniphier_fi2c_regs { u32 tbcm; /* Tx byte count monitor */ u32 rbcm; /* Rx byte count monitor */ u32 brst; /* bus reset */ -#define I2C_BRST_FOEN (1 << 1) /* normal operation */ -#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */ +#define I2C_BRST_FOEN BIT(1) /* normal operation */ +#define I2C_BRST_RSCLO BIT(0) /* release SCL low fixing */ }; #define FIOCLK 50000000 diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index c4972ff..72d07e2 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -20,19 +20,19 @@ DECLARE_GLOBAL_DATA_PTR; struct uniphier_i2c_regs { u32 dtrm; /* data transmission */ -#define I2C_DTRM_STA (1 << 10) -#define I2C_DTRM_STO (1 << 9) -#define I2C_DTRM_NACK (1 << 8) -#define I2C_DTRM_RD (1 << 0) +#define I2C_DTRM_STA BIT(10) +#define I2C_DTRM_STO BIT(9) +#define I2C_DTRM_NACK BIT(8) +#define I2C_DTRM_RD BIT(0) u32 drec; /* data reception */ -#define I2C_DREC_STS (1 << 12) -#define I2C_DREC_LRB (1 << 11) -#define I2C_DREC_LAB (1 << 9) +#define I2C_DREC_STS BIT(12) +#define I2C_DREC_LRB BIT(11) +#define I2C_DREC_LAB BIT(9) u32 myad; /* slave address */ u32 clk; /* clock frequency control */ u32 brst; /* bus reset */ -#define I2C_BRST_FOEN (1 << 1) -#define I2C_BRST_BRST (1 << 0) +#define I2C_BRST_FOEN BIT(1) +#define I2C_BRST_BRST BIT(0) u32 hold; /* hold time control */ u32 bsts; /* bus status monitor */ u32 noise; /* noise filter control */ diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 41cc3b8..e088e6b 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -120,17 +120,17 @@ static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip, case I2C_MUX_PCA9542_ID: if (channel > 1) return -1; - buf = (uint8_t)((channel & 0x01) | (1 << 2)); + buf = (uint8_t)((channel & 0x01) | BIT(2)); break; case I2C_MUX_PCA9544_ID: if (channel > 3) return -1; - buf = (uint8_t)((channel & 0x03) | (1 << 2)); + buf = (uint8_t)((channel & 0x03) | BIT(2)); break; case I2C_MUX_PCA9547_ID: if (channel > 7) return -1; - buf = (uint8_t)((channel & 0x07) | (1 << 3)); + buf = (uint8_t)((channel & 0x07) | BIT(3)); break; case I2C_MUX_PCA9548_ID: if (channel > 7) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 42782cb..c522c74 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -42,24 +42,24 @@ struct mxc_i2c_regs { }; #endif -#define I2CR_IIEN (1 << 6) -#define I2CR_MSTA (1 << 5) -#define I2CR_MTX (1 << 4) -#define I2CR_TX_NO_AK (1 << 3) -#define I2CR_RSTA (1 << 2) - -#define I2SR_ICF (1 << 7) -#define I2SR_IBB (1 << 5) -#define I2SR_IAL (1 << 4) -#define I2SR_IIF (1 << 1) -#define I2SR_RX_NO_AK (1 << 0) +#define I2CR_IIEN BIT(6) +#define I2CR_MSTA BIT(5) +#define I2CR_MTX BIT(4) +#define I2CR_TX_NO_AK BIT(3) +#define I2CR_RSTA BIT(2) + +#define I2SR_ICF BIT(7) +#define I2SR_IBB BIT(5) +#define I2SR_IAL BIT(4) +#define I2SR_IIF BIT(1) +#define I2SR_RX_NO_AK BIT(0) #ifdef I2C_QUIRK_REG #define I2CR_IEN (0 << 7) -#define I2CR_IDIS (1 << 7) -#define I2SR_IIF_CLEAR (1 << 1) +#define I2CR_IDIS BIT(7) +#define I2SR_IIF_CLEAR BIT(1) #else -#define I2CR_IEN (1 << 7) +#define I2CR_IEN BIT(7) #define I2CR_IDIS (0 << 7) #define I2SR_IIF_CLEAR (0 << 1) #endif diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 0f1e35c..5ecb1d0 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -366,7 +366,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, return 1; } - if (addr + len > (1 << 16)) { + if (addr + len > BIT(16)) { puts("I2C read: address out of range\n"); return 1; } @@ -495,7 +495,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, return 1; } - if (addr + len > (1 << 16)) { + if (addr + len > BIT(16)) { printf("I2C write: address 0x%x + 0x%x out of range\n", addr, len); return 1; diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h index 3dae295..9c112b6 100644 --- a/drivers/i2c/omap24xx_i2c.h +++ b/drivers/i2c/omap24xx_i2c.h @@ -10,26 +10,26 @@ /* I2C masks */ /* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_IE_GC_IE BIT(5) +#define I2C_IE_XRDY_IE BIT(4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE BIT(3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE BIT(2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE BIT(1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE BIT(0) /* Arbitration lost interrupt enable */ /* I2C Status Register (I2C_STAT): */ -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_STAT_SBD BIT(15) /* Single byte data */ +#define I2C_STAT_BB BIT(12) /* Bus busy */ +#define I2C_STAT_ROVR BIT(11) /* Receive overrun */ +#define I2C_STAT_XUDF BIT(10) /* Transmit underflow */ +#define I2C_STAT_AAS BIT(9) /* Address as slave */ +#define I2C_STAT_GC BIT(5) +#define I2C_STAT_XRDY BIT(4) /* Transmit data ready */ +#define I2C_STAT_RRDY BIT(3) /* Receive data ready */ +#define I2C_STAT_ARDY BIT(2) /* Register access ready */ +#define I2C_STAT_NACK BIT(1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL BIT(0) /* Arbitration lost interrupt enable */ /* I2C Interrupt Code Register (I2C_INTCODE): */ @@ -43,35 +43,35 @@ /* I2C Buffer Configuration Register (I2C_BUF): */ -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ +#define I2C_BUF_RDMA_EN BIT(15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN BIT(7) /* Transmit DMA channel enable */ /* I2C Configuration Register (I2C_CON): */ -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ +#define I2C_CON_EN BIT(15) /* I2C module enable */ +#define I2C_CON_BE BIT(14) /* Big endian mode */ +#define I2C_CON_STB BIT(11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST BIT(10) /* Master/slave mode */ +#define I2C_CON_TRX BIT(9) /* Transmitter/receiver mode */ /* (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ +#define I2C_CON_XA BIT(8) /* Expand address */ +#define I2C_CON_STP BIT(1) /* Stop condition (master mode only) */ +#define I2C_CON_STT BIT(0) /* Start condition (master mode only) */ /* I2C System Test Register (I2C_SYSTEST): */ -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_ST_EN BIT(15) /* System test enable */ +#define I2C_SYSTEST_FREE BIT(14) /* Free running mode, on brkpoint) */ #define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ #define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ +#define I2C_SYSTEST_SCL_I BIT(3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O BIT(2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I BIT(1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O BIT(0) /* SDA line drive output value */ /* I2C System Status Register (I2C_SYSS): */ -#define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ +#define I2C_SYSS_RDONE BIT(0) /* Internel reset monitoring */ #define I2C_SCLL_SCLL 0 #define I2C_SCLL_SCLL_M 0xFF diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c index 313288d..b352695 100644 --- a/drivers/i2c/pca9564_i2c.c +++ b/drivers/i2c/pca9564_i2c.c @@ -21,7 +21,7 @@ #define PCA_STA (CONFIG_PCA9564_BASE + 0) #define PCA_TO (CONFIG_PCA9564_BASE + 0) -#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2)) +#define PCA_DAT (CONFIG_PCA9564_BASE + BIT(2)) #define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2)) #define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2)) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index e7e9692..6e24833 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -24,22 +24,22 @@ struct sh_i2c { #undef ureg /* ICCR */ -#define SH_I2C_ICCR_ICE (1 << 7) -#define SH_I2C_ICCR_RACK (1 << 6) -#define SH_I2C_ICCR_RTS (1 << 4) -#define SH_I2C_ICCR_BUSY (1 << 2) -#define SH_I2C_ICCR_SCP (1 << 0) +#define SH_I2C_ICCR_ICE BIT(7) +#define SH_I2C_ICCR_RACK BIT(6) +#define SH_I2C_ICCR_RTS BIT(4) +#define SH_I2C_ICCR_BUSY BIT(2) +#define SH_I2C_ICCR_SCP BIT(0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 << 4) -#define SH_IC_TACK (1 << 2) -#define SH_IC_WAIT (1 << 1) -#define SH_IC_DTE (1 << 0) +#define SH_IC_BUSY BIT(4) +#define SH_IC_TACK BIT(2) +#define SH_IC_WAIT BIT(1) +#define SH_IC_DTE BIT(0) #ifdef CONFIG_SH_I2C_8BIT /* store 8th bit of iccl and icch in ICIC register */ -#define SH_I2C_ICIC_ICCLB8 (1 << 7) -#define SH_I2C_ICIC_ICCHB8 (1 << 6) +#define SH_I2C_ICIC_ICCLB8 BIT(7) +#define SH_I2C_ICIC_ICCHB8 BIT(6) #endif static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c index 6c2f221..896d2f7 100644 --- a/drivers/i2c/sh_sh7734_i2c.c +++ b/drivers/i2c/sh_sh7734_i2c.c @@ -27,38 +27,38 @@ static struct sh_i2c *base; static u8 iccr1_cks, nf2cyc; /* ICCR1 */ -#define SH_I2C_ICCR1_ICE (1 << 7) -#define SH_I2C_ICCR1_RCVD (1 << 6) -#define SH_I2C_ICCR1_MST (1 << 5) -#define SH_I2C_ICCR1_TRS (1 << 4) +#define SH_I2C_ICCR1_ICE BIT(7) +#define SH_I2C_ICCR1_RCVD BIT(6) +#define SH_I2C_ICCR1_MST BIT(5) +#define SH_I2C_ICCR1_TRS BIT(4) #define SH_I2C_ICCR1_MTRS \ (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS) /* ICCR1 */ -#define SH_I2C_ICCR2_BBSY (1 << 7) -#define SH_I2C_ICCR2_SCP (1 << 6) -#define SH_I2C_ICCR2_SDAO (1 << 5) -#define SH_I2C_ICCR2_SDAOP (1 << 4) -#define SH_I2C_ICCR2_SCLO (1 << 3) -#define SH_I2C_ICCR2_IICRST (1 << 1) - -#define SH_I2C_ICIER_TIE (1 << 7) -#define SH_I2C_ICIER_TEIE (1 << 6) -#define SH_I2C_ICIER_RIE (1 << 5) -#define SH_I2C_ICIER_NAKIE (1 << 4) -#define SH_I2C_ICIER_STIE (1 << 3) -#define SH_I2C_ICIER_ACKE (1 << 2) -#define SH_I2C_ICIER_ACKBR (1 << 1) -#define SH_I2C_ICIER_ACKBT (1 << 0) - -#define SH_I2C_ICSR_TDRE (1 << 7) -#define SH_I2C_ICSR_TEND (1 << 6) -#define SH_I2C_ICSR_RDRF (1 << 5) -#define SH_I2C_ICSR_NACKF (1 << 4) -#define SH_I2C_ICSR_STOP (1 << 3) -#define SH_I2C_ICSR_ALOVE (1 << 2) -#define SH_I2C_ICSR_AAS (1 << 1) -#define SH_I2C_ICSR_ADZ (1 << 0) +#define SH_I2C_ICCR2_BBSY BIT(7) +#define SH_I2C_ICCR2_SCP BIT(6) +#define SH_I2C_ICCR2_SDAO BIT(5) +#define SH_I2C_ICCR2_SDAOP BIT(4) +#define SH_I2C_ICCR2_SCLO BIT(3) +#define SH_I2C_ICCR2_IICRST BIT(1) + +#define SH_I2C_ICIER_TIE BIT(7) +#define SH_I2C_ICIER_TEIE BIT(6) +#define SH_I2C_ICIER_RIE BIT(5) +#define SH_I2C_ICIER_NAKIE BIT(4) +#define SH_I2C_ICIER_STIE BIT(3) +#define SH_I2C_ICIER_ACKE BIT(2) +#define SH_I2C_ICIER_ACKBR BIT(1) +#define SH_I2C_ICIER_ACKBT BIT(0) + +#define SH_I2C_ICSR_TDRE BIT(7) +#define SH_I2C_ICSR_TEND BIT(6) +#define SH_I2C_ICSR_RDRF BIT(5) +#define SH_I2C_ICSR_NACKF BIT(4) +#define SH_I2C_ICSR_STOP BIT(3) +#define SH_I2C_ICSR_ALOVE BIT(2) +#define SH_I2C_ICSR_AAS BIT(1) +#define SH_I2C_ICSR_ADZ BIT(0) #define IRQ_WAIT 1000 diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index 0ef94f7..a2007f5 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -26,11 +26,11 @@ enum { #define KBC_FIFO_TH_CNT_SHIFT 14 #define KBC_DEBOUNCE_CNT_SHIFT 4 -#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) -#define KBC_CONTROL_KBC_EN (1 << 0) -#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) -#define KBC_KPENT_VALID (1 << 7) -#define KBC_ST_STATUS (1 << 3) +#define KBC_CONTROL_FIFO_CNT_INT_EN BIT(3) +#define KBC_CONTROL_KBC_EN BIT(0) +#define KBC_INT_FIFO_CNT_INT_STATUS BIT(2) +#define KBC_KPENT_VALID BIT(7) +#define KBC_ST_STATUS BIT(3) enum { KBC_DEBOUNCE_COUNT = 2, diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 5b5b33a..1fcbd5d 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -14,15 +14,15 @@ #include /* MMC/SD in SPI mode reports R1 status always */ -#define R1_SPI_IDLE (1 << 0) -#define R1_SPI_ERASE_RESET (1 << 1) -#define R1_SPI_ILLEGAL_COMMAND (1 << 2) -#define R1_SPI_COM_CRC (1 << 3) -#define R1_SPI_ERASE_SEQ (1 << 4) -#define R1_SPI_ADDRESS (1 << 5) -#define R1_SPI_PARAMETER (1 << 6) +#define R1_SPI_IDLE BIT(0) +#define R1_SPI_ERASE_RESET BIT(1) +#define R1_SPI_ILLEGAL_COMMAND BIT(2) +#define R1_SPI_COM_CRC BIT(3) +#define R1_SPI_ERASE_SEQ BIT(4) +#define R1_SPI_ADDRESS BIT(5) +#define R1_SPI_PARAMETER BIT(6) /* R1 bit 7 is always zero, reuse this bit for error */ -#define R1_SPI_ERROR (1 << 7) +#define R1_SPI_ERROR BIT(7) /* Response tokens used to ack each block written: */ #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 561b204..5abbacd 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -47,57 +47,57 @@ struct mxcmci_regs { u32 buffer_access; }; -#define STR_STP_CLK_RESET (1 << 3) -#define STR_STP_CLK_START_CLK (1 << 1) -#define STR_STP_CLK_STOP_CLK (1 << 0) - -#define STATUS_CARD_INSERTION (1 << 31) -#define STATUS_CARD_REMOVAL (1 << 30) -#define STATUS_YBUF_EMPTY (1 << 29) -#define STATUS_XBUF_EMPTY (1 << 28) -#define STATUS_YBUF_FULL (1 << 27) -#define STATUS_XBUF_FULL (1 << 26) -#define STATUS_BUF_UND_RUN (1 << 25) -#define STATUS_BUF_OVFL (1 << 24) -#define STATUS_SDIO_INT_ACTIVE (1 << 14) -#define STATUS_END_CMD_RESP (1 << 13) -#define STATUS_WRITE_OP_DONE (1 << 12) -#define STATUS_DATA_TRANS_DONE (1 << 11) -#define STATUS_READ_OP_DONE (1 << 11) +#define STR_STP_CLK_RESET BIT(3) +#define STR_STP_CLK_START_CLK BIT(1) +#define STR_STP_CLK_STOP_CLK BIT(0) + +#define STATUS_CARD_INSERTION BIT(31) +#define STATUS_CARD_REMOVAL BIT(30) +#define STATUS_YBUF_EMPTY BIT(29) +#define STATUS_XBUF_EMPTY BIT(28) +#define STATUS_YBUF_FULL BIT(27) +#define STATUS_XBUF_FULL BIT(26) +#define STATUS_BUF_UND_RUN BIT(25) +#define STATUS_BUF_OVFL BIT(24) +#define STATUS_SDIO_INT_ACTIVE BIT(14) +#define STATUS_END_CMD_RESP BIT(13) +#define STATUS_WRITE_OP_DONE BIT(12) +#define STATUS_DATA_TRANS_DONE BIT(11) +#define STATUS_READ_OP_DONE BIT(11) #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) -#define STATUS_CARD_BUS_CLK_RUN (1 << 8) -#define STATUS_BUF_READ_RDY (1 << 7) -#define STATUS_BUF_WRITE_RDY (1 << 6) -#define STATUS_RESP_CRC_ERR (1 << 5) -#define STATUS_CRC_READ_ERR (1 << 3) -#define STATUS_CRC_WRITE_ERR (1 << 2) -#define STATUS_TIME_OUT_RESP (1 << 1) -#define STATUS_TIME_OUT_READ (1 << 0) +#define STATUS_CARD_BUS_CLK_RUN BIT(8) +#define STATUS_BUF_READ_RDY BIT(7) +#define STATUS_BUF_WRITE_RDY BIT(6) +#define STATUS_RESP_CRC_ERR BIT(5) +#define STATUS_CRC_READ_ERR BIT(3) +#define STATUS_CRC_WRITE_ERR BIT(2) +#define STATUS_TIME_OUT_RESP BIT(1) +#define STATUS_TIME_OUT_READ BIT(0) #define STATUS_ERR_MASK 0x2f -#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) -#define CMD_DAT_CONT_STOP_READWAIT (1 << 11) -#define CMD_DAT_CONT_START_READWAIT (1 << 10) +#define CMD_DAT_CONT_CMD_RESP_LONG_OFF BIT(12) +#define CMD_DAT_CONT_STOP_READWAIT BIT(11) +#define CMD_DAT_CONT_START_READWAIT BIT(10) #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) -#define CMD_DAT_CONT_INIT (1 << 7) -#define CMD_DAT_CONT_WRITE (1 << 4) -#define CMD_DAT_CONT_DATA_ENABLE (1 << 3) -#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) +#define CMD_DAT_CONT_INIT BIT(7) +#define CMD_DAT_CONT_WRITE BIT(4) +#define CMD_DAT_CONT_DATA_ENABLE BIT(3) +#define CMD_DAT_CONT_RESPONSE_48BIT_CRC BIT(0) #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) -#define INT_SDIO_INT_WKP_EN (1 << 18) -#define INT_CARD_INSERTION_WKP_EN (1 << 17) -#define INT_CARD_REMOVAL_WKP_EN (1 << 16) -#define INT_CARD_INSERTION_EN (1 << 15) -#define INT_CARD_REMOVAL_EN (1 << 14) -#define INT_SDIO_IRQ_EN (1 << 13) -#define INT_DAT0_EN (1 << 12) -#define INT_BUF_READ_EN (1 << 4) -#define INT_BUF_WRITE_EN (1 << 3) -#define INT_END_CMD_RES_EN (1 << 2) -#define INT_WRITE_OP_DONE_EN (1 << 1) -#define INT_READ_OP_EN (1 << 0) +#define INT_SDIO_INT_WKP_EN BIT(18) +#define INT_CARD_INSERTION_WKP_EN BIT(17) +#define INT_CARD_REMOVAL_WKP_EN BIT(16) +#define INT_CARD_INSERTION_EN BIT(15) +#define INT_CARD_REMOVAL_EN BIT(14) +#define INT_SDIO_IRQ_EN BIT(13) +#define INT_DAT0_EN BIT(12) +#define INT_BUF_READ_EN BIT(4) +#define INT_BUF_WRITE_EN BIT(3) +#define INT_END_CMD_RES_EN BIT(2) +#define INT_WRITE_OP_DONE_EN BIT(1) +#define INT_READ_OP_EN BIT(0) struct mxcmci_host { struct mmc *mmc; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index dc725cb..51bef8c 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -45,8 +45,8 @@ #endif /* common definitions for all OMAPs */ -#define SYSCTL_SRC (1 << 25) -#define SYSCTL_SRD (1 << 26) +#define SYSCTL_SRC BIT(25) +#define SYSCTL_SRD BIT(26) struct omap_hsmmc_data { struct hsmmc *base_addr; diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 25ab0b1..3b69488 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -172,7 +172,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) && cmd->resp_type & MMC_RSP_CRC) { #ifdef PXAMMC_CRC_SKIP if (cmd->resp_type & MMC_RSP_136 - && cmd->response[0] & (1 << 31)) + && cmd->response[0] & BIT(31)) printf("Ignoring CRC, this may be dangerous!\n"); else #endif diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c index 1b5b705..f54c972 100644 --- a/drivers/mmc/s3c_sdi.c +++ b/drivers/mmc/s3c_sdi.c @@ -16,38 +16,38 @@ #include #include -#define S3C2440_SDICON_SDRESET (1 << 8) -#define S3C2410_SDICON_FIFORESET (1 << 1) -#define S3C2410_SDICON_CLOCKTYPE (1 << 0) - -#define S3C2410_SDICMDCON_LONGRSP (1 << 10) -#define S3C2410_SDICMDCON_WAITRSP (1 << 9) -#define S3C2410_SDICMDCON_CMDSTART (1 << 8) -#define S3C2410_SDICMDCON_SENDERHOST (1 << 6) +#define S3C2440_SDICON_SDRESET BIT(8) +#define S3C2410_SDICON_FIFORESET BIT(1) +#define S3C2410_SDICON_CLOCKTYPE BIT(0) + +#define S3C2410_SDICMDCON_LONGRSP BIT(10) +#define S3C2410_SDICMDCON_WAITRSP BIT(9) +#define S3C2410_SDICMDCON_CMDSTART BIT(8) +#define S3C2410_SDICMDCON_SENDERHOST BIT(6) #define S3C2410_SDICMDCON_INDEX 0x3f -#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12) -#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11) -#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10) -#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9) +#define S3C2410_SDICMDSTAT_CRCFAIL BIT(12) +#define S3C2410_SDICMDSTAT_CMDSENT BIT(11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT BIT(10) +#define S3C2410_SDICMDSTAT_RSPFIN BIT(9) #define S3C2440_SDIDCON_DS_WORD (2 << 22) -#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20) -#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19) -#define S3C2410_SDIDCON_BLOCKMODE (1 << 17) -#define S3C2410_SDIDCON_WIDEBUS (1 << 16) -#define S3C2440_SDIDCON_DATSTART (1 << 14) +#define S3C2410_SDIDCON_TXAFTERRESP BIT(20) +#define S3C2410_SDIDCON_RXAFTERCMD BIT(19) +#define S3C2410_SDIDCON_BLOCKMODE BIT(17) +#define S3C2410_SDIDCON_WIDEBUS BIT(16) +#define S3C2440_SDIDCON_DATSTART BIT(14) #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12) #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12) #define S3C2410_SDIDCON_BLKNUM 0x7ff -#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8) -#define S3C2410_SDIDSTA_CRCFAIL (1 << 7) -#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6) -#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5) -#define S3C2410_SDIDSTA_XFERFINISH (1 << 4) +#define S3C2410_SDIDSTA_FIFOFAIL BIT(8) +#define S3C2410_SDIDSTA_CRCFAIL BIT(7) +#define S3C2410_SDIDSTA_RXCRCFAIL BIT(6) +#define S3C2410_SDIDSTA_DATATIMEOUT BIT(5) +#define S3C2410_SDIDSTA_XFERFINISH BIT(4) -#define S3C2410_SDIFSTA_TFHALF (1 << 11) +#define S3C2410_SDIFSTA_TFHALF BIT(11) #define S3C2410_SDIFSTA_COUNTMASK 0x7f /* diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h index 4b6752f..a6637fe 100644 --- a/drivers/mmc/sh_mmcif.h +++ b/drivers/mmc/sh_mmcif.h @@ -40,98 +40,98 @@ struct sh_mmcif_regs { #define CMD_MASK 0x3f000000 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) /* R1/R1b/R3/R4/R5 */ -#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) +#define CMD_SET_RTYP_6B ((0 << 23) | BIT(22)) /* R2 */ -#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) +#define CMD_SET_RTYP_17B (BIT(23) | (0 << 22)) /* R1b */ -#define CMD_SET_RBSY (1 << 21) -#define CMD_SET_CCSEN (1 << 20) +#define CMD_SET_RBSY BIT(21) +#define CMD_SET_CCSEN BIT(20) /* 1: on data, 0: no data */ -#define CMD_SET_WDAT (1 << 19) +#define CMD_SET_WDAT BIT(19) /* 1: write to card, 0: read from card */ -#define CMD_SET_DWEN (1 << 18) +#define CMD_SET_DWEN BIT(18) /* 1: multi block trans, 0: single */ -#define CMD_SET_CMLTE (1 << 17) +#define CMD_SET_CMLTE BIT(17) /* 1: CMD12 auto issue */ -#define CMD_SET_CMD12EN (1 << 16) +#define CMD_SET_CMD12EN BIT(16) /* index check */ #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* check bits check */ -#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) +#define CMD_SET_RIDXC_BITS ((0 << 15) | BIT(14)) /* no check */ -#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) +#define CMD_SET_RIDXC_NO (BIT(15) | (0 << 14)) /* 1: CRC7 check*/ #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* 1: check bits check*/ -#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) +#define CMD_SET_CRC7C_BITS ((0 << 13) | BIT(12)) /* 1: internal CRC7 check*/ -#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) +#define CMD_SET_CRC7C_INTERNAL (BIT(13) | (0 << 12)) /* 1: CRC16 check*/ -#define CMD_SET_CRC16C (1 << 10) +#define CMD_SET_CRC16C BIT(10) /* 1: not receive CRC status */ -#define CMD_SET_CRCSTE (1 << 8) +#define CMD_SET_CRCSTE BIT(8) /* 1: tran mission bit "Low" */ -#define CMD_SET_TBIT (1 << 7) +#define CMD_SET_TBIT BIT(7) /* 1: open/drain */ -#define CMD_SET_OPDM (1 << 6) -#define CMD_SET_CCSH (1 << 5) +#define CMD_SET_OPDM BIT(6) +#define CMD_SET_CCSH BIT(5) /* 1bit */ #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 4bit */ -#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) +#define CMD_SET_DATW_4 ((0 << 1) | BIT(0)) /* 8bit */ -#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) +#define CMD_SET_DATW_8 (BIT(1) | (0 << 0)) /* CE_CMD_CTRL */ -#define CMD_CTRL_BREAK (1 << 0) +#define CMD_CTRL_BREAK BIT(0) /* CE_BLOCK_SET */ #define BLOCK_SIZE_MASK 0x0000ffff /* CE_CLK_CTRL */ -#define CLK_ENABLE (1 << 24) -#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) -#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +#define CLK_ENABLE BIT(24) +#define CLK_CLEAR (BIT(19) | BIT(18) | BIT(17) | BIT(16)) +#define CLK_PCLK (BIT(19) | BIT(18) | BIT(17) | BIT(16)) /* respons timeout */ -#define SRSPTO_256 ((1 << 13) | (0 << 12)) +#define SRSPTO_256 (BIT(13) | (0 << 12)) /* respons busy timeout */ -#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8)) +#define SRBSYTO_29 (BIT(11) | BIT(10) | BIT(9) | BIT(8)) /* read/write timeout */ -#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) +#define SRWDTO_29 (BIT(7) | BIT(6) | BIT(5) | BIT(4)) /* ccs timeout */ -#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)) +#define SCCSTO_29 (BIT(3) | BIT(2) | BIT(1) | BIT(0)) /* CE_BUF_ACC */ -#define BUF_ACC_DMAWEN (1 << 25) -#define BUF_ACC_DMAREN (1 << 24) +#define BUF_ACC_DMAWEN BIT(25) +#define BUF_ACC_DMAREN BIT(24) #define BUF_ACC_BUSW_32 (0 << 17) -#define BUF_ACC_BUSW_16 (1 << 17) -#define BUF_ACC_ATYP (1 << 16) +#define BUF_ACC_BUSW_16 BIT(17) +#define BUF_ACC_ATYP BIT(16) /* CE_INT */ -#define INT_CCSDE (1 << 29) -#define INT_CMD12DRE (1 << 26) -#define INT_CMD12RBE (1 << 25) -#define INT_CMD12CRE (1 << 24) -#define INT_DTRANE (1 << 23) -#define INT_BUFRE (1 << 22) -#define INT_BUFWEN (1 << 21) -#define INT_BUFREN (1 << 20) -#define INT_CCSRCV (1 << 19) -#define INT_RBSYE (1 << 17) -#define INT_CRSPE (1 << 16) -#define INT_CMDVIO (1 << 15) -#define INT_BUFVIO (1 << 14) -#define INT_WDATERR (1 << 11) -#define INT_RDATERR (1 << 10) -#define INT_RIDXERR (1 << 9) -#define INT_RSPERR (1 << 8) -#define INT_CCSTO (1 << 5) -#define INT_CRCSTO (1 << 4) -#define INT_WDATTO (1 << 3) -#define INT_RDATTO (1 << 2) -#define INT_RBSYTO (1 << 1) -#define INT_RSPTO (1 << 0) +#define INT_CCSDE BIT(29) +#define INT_CMD12DRE BIT(26) +#define INT_CMD12RBE BIT(25) +#define INT_CMD12CRE BIT(24) +#define INT_DTRANE BIT(23) +#define INT_BUFRE BIT(22) +#define INT_BUFWEN BIT(21) +#define INT_BUFREN BIT(20) +#define INT_CCSRCV BIT(19) +#define INT_RBSYE BIT(17) +#define INT_CRSPE BIT(16) +#define INT_CMDVIO BIT(15) +#define INT_BUFVIO BIT(14) +#define INT_WDATERR BIT(11) +#define INT_RDATERR BIT(10) +#define INT_RIDXERR BIT(9) +#define INT_RSPERR BIT(8) +#define INT_CCSTO BIT(5) +#define INT_CRCSTO BIT(4) +#define INT_WDATTO BIT(3) +#define INT_RDATTO BIT(2) +#define INT_RBSYTO BIT(1) +#define INT_RSPTO BIT(0) #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ @@ -140,52 +140,52 @@ struct sh_mmcif_regs { /* CE_INT_MASK */ #define MASK_ALL 0x00000000 -#define MASK_MCCSDE (1 << 29) -#define MASK_MCMD12DRE (1 << 26) -#define MASK_MCMD12RBE (1 << 25) -#define MASK_MCMD12CRE (1 << 24) -#define MASK_MDTRANE (1 << 23) -#define MASK_MBUFRE (1 << 22) -#define MASK_MBUFWEN (1 << 21) -#define MASK_MBUFREN (1 << 20) -#define MASK_MCCSRCV (1 << 19) -#define MASK_MRBSYE (1 << 17) -#define MASK_MCRSPE (1 << 16) -#define MASK_MCMDVIO (1 << 15) -#define MASK_MBUFVIO (1 << 14) -#define MASK_MWDATERR (1 << 11) -#define MASK_MRDATERR (1 << 10) -#define MASK_MRIDXERR (1 << 9) -#define MASK_MRSPERR (1 << 8) -#define MASK_MCCSTO (1 << 5) -#define MASK_MCRCSTO (1 << 4) -#define MASK_MWDATTO (1 << 3) -#define MASK_MRDATTO (1 << 2) -#define MASK_MRBSYTO (1 << 1) -#define MASK_MRSPTO (1 << 0) +#define MASK_MCCSDE BIT(29) +#define MASK_MCMD12DRE BIT(26) +#define MASK_MCMD12RBE BIT(25) +#define MASK_MCMD12CRE BIT(24) +#define MASK_MDTRANE BIT(23) +#define MASK_MBUFRE BIT(22) +#define MASK_MBUFWEN BIT(21) +#define MASK_MBUFREN BIT(20) +#define MASK_MCCSRCV BIT(19) +#define MASK_MRBSYE BIT(17) +#define MASK_MCRSPE BIT(16) +#define MASK_MCMDVIO BIT(15) +#define MASK_MBUFVIO BIT(14) +#define MASK_MWDATERR BIT(11) +#define MASK_MRDATERR BIT(10) +#define MASK_MRIDXERR BIT(9) +#define MASK_MRSPERR BIT(8) +#define MASK_MCCSTO BIT(5) +#define MASK_MCRCSTO BIT(4) +#define MASK_MWDATTO BIT(3) +#define MASK_MRDATTO BIT(2) +#define MASK_MRBSYTO BIT(1) +#define MASK_MRSPTO BIT(0) /* CE_HOST_STS1 */ -#define STS1_CMDSEQ (1 << 31) +#define STS1_CMDSEQ BIT(31) /* CE_HOST_STS2 */ -#define STS2_CRCSTE (1 << 31) -#define STS2_CRC16E (1 << 30) -#define STS2_AC12CRCE (1 << 29) -#define STS2_RSPCRC7E (1 << 28) -#define STS2_CRCSTEBE (1 << 27) -#define STS2_RDATEBE (1 << 26) -#define STS2_AC12REBE (1 << 25) -#define STS2_RSPEBE (1 << 24) -#define STS2_AC12IDXE (1 << 23) -#define STS2_RSPIDXE (1 << 22) -#define STS2_CCSTO (1 << 15) -#define STS2_RDATTO (1 << 14) -#define STS2_DATBSYTO (1 << 13) -#define STS2_CRCSTTO (1 << 12) -#define STS2_AC12BSYTO (1 << 11) -#define STS2_RSPBSYTO (1 << 10) -#define STS2_AC12RSPTO (1 << 9) -#define STS2_RSPTO (1 << 8) +#define STS2_CRCSTE BIT(31) +#define STS2_CRC16E BIT(30) +#define STS2_AC12CRCE BIT(29) +#define STS2_RSPCRC7E BIT(28) +#define STS2_CRCSTEBE BIT(27) +#define STS2_RDATEBE BIT(26) +#define STS2_AC12REBE BIT(25) +#define STS2_RSPEBE BIT(24) +#define STS2_AC12IDXE BIT(23) +#define STS2_RSPIDXE BIT(22) +#define STS2_CCSTO BIT(15) +#define STS2_RDATTO BIT(14) +#define STS2_DATBSYTO BIT(13) +#define STS2_CRCSTTO BIT(12) +#define STS2_AC12BSYTO BIT(11) +#define STS2_RSPBSYTO BIT(10) +#define STS2_AC12RSPTO BIT(9) +#define STS2_RSPTO BIT(8) #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) @@ -195,15 +195,15 @@ struct sh_mmcif_regs { STS2_AC12RSPTO | STS2_RSPTO) /* CE_VERSION */ -#define SOFT_RST_ON (1 << 31) +#define SOFT_RST_ON BIT(31) #define SOFT_RST_OFF (0 << 31) #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ #ifdef CONFIG_RMOBILE -#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9)) -#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1)) +#define MMC_CLK_DIV_MIN(clk) (clk / BIT(9)) +#define MMC_CLK_DIV_MAX(clk) (clk / BIT(1)) #else -#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8)) +#define MMC_CLK_DIV_MIN(clk) (clk / BIT(8)) #define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA #endif diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index cc62c89..82a4684 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -162,7 +162,7 @@ static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk) { u32 clkdiv, i, timeout; - if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) { + if (sh_sdhi_readw(host, SDHI_INFO2) & BIT(14)) { printf(DRIVER_NAME": Busy state ! Cannot change the clock\n"); return -EBUSY; } diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 2cd8cf1..c958651 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -248,7 +248,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, for (i = 0; i < retry; i++) { /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ if (readl(&host->reg->prnsts) - & (1 << 20)) /* DAT[0] */ + & BIT(20)) /* DAT[0] */ break; } @@ -418,11 +418,11 @@ static void tegra_mmc_set_ios(struct mmc *mmc) * 0 = 1-bit mode */ if (mmc->bus_width == 8) - ctrl |= (1 << 5); + ctrl |= BIT(5); else if (mmc->bus_width == 4) - ctrl |= (1 << 1); + ctrl |= BIT(1); else - ctrl &= ~(1 << 1); + ctrl &= ~BIT(1); writeb(ctrl, &host->reg->hostctl); debug("mmc_set_ios: hostctl = %08X\n", ctrl); diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index b2d2682..a72299f 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -9,7 +9,7 @@ #define ATMEL_NAND_ECC_H #define ATMEL_ECC_CR 0x00 /* Control register */ -#define ATMEL_ECC_RST (1 << 0) /* Reset parity */ +#define ATMEL_ECC_RST BIT(0) /* Reset parity */ #define ATMEL_ECC_MR 0x04 /* Mode register */ #define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */ @@ -19,9 +19,9 @@ #define ATMEL_ECC_PAGESIZE_4224 (3) #define ATMEL_ECC_SR 0x08 /* Status register */ -#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */ -#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ -#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */ +#define ATMEL_ECC_RECERR BIT(0) /* Recoverable Error */ +#define ATMEL_ECC_ECCERR BIT(1) /* ECC Single Bit Error */ +#define ATMEL_ECC_MULERR BIT(2) /* Multiple Errors */ #define ATMEL_ECC_PR 0x0c /* Parity register */ #define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */ @@ -72,41 +72,41 @@ struct pmecc_regs { /* For PMECC Configuration Register */ #define PMECC_CFG_BCH_ERR2 (0 << 0) -#define PMECC_CFG_BCH_ERR4 (1 << 0) +#define PMECC_CFG_BCH_ERR4 BIT(0) #define PMECC_CFG_BCH_ERR8 (2 << 0) #define PMECC_CFG_BCH_ERR12 (3 << 0) #define PMECC_CFG_BCH_ERR24 (4 << 0) #define PMECC_CFG_SECTOR512 (0 << 4) -#define PMECC_CFG_SECTOR1024 (1 << 4) +#define PMECC_CFG_SECTOR1024 BIT(4) #define PMECC_CFG_PAGE_1SECTOR (0 << 8) -#define PMECC_CFG_PAGE_2SECTORS (1 << 8) +#define PMECC_CFG_PAGE_2SECTORS BIT(8) #define PMECC_CFG_PAGE_4SECTORS (2 << 8) #define PMECC_CFG_PAGE_8SECTORS (3 << 8) #define PMECC_CFG_READ_OP (0 << 12) -#define PMECC_CFG_WRITE_OP (1 << 12) +#define PMECC_CFG_WRITE_OP BIT(12) -#define PMECC_CFG_SPARE_ENABLE (1 << 16) +#define PMECC_CFG_SPARE_ENABLE BIT(16) #define PMECC_CFG_SPARE_DISABLE (0 << 16) -#define PMECC_CFG_AUTO_ENABLE (1 << 20) +#define PMECC_CFG_AUTO_ENABLE BIT(20) #define PMECC_CFG_AUTO_DISABLE (0 << 20) /* For PMECC Clock Control Register */ #define PMECC_CLK_133MHZ (2 << 0) /* For PMECC Control Register */ -#define PMECC_CTRL_RST (1 << 0) -#define PMECC_CTRL_DATA (1 << 1) -#define PMECC_CTRL_USER (1 << 2) -#define PMECC_CTRL_ENABLE (1 << 4) -#define PMECC_CTRL_DISABLE (1 << 5) +#define PMECC_CTRL_RST BIT(0) +#define PMECC_CTRL_DATA BIT(1) +#define PMECC_CTRL_USER BIT(2) +#define PMECC_CTRL_ENABLE BIT(4) +#define PMECC_CTRL_DISABLE BIT(5) /* For PMECC Status Register */ -#define PMECC_SR_BUSY (1 << 0) -#define PMECC_SR_ENABLE (1 << 4) +#define PMECC_SR_BUSY BIT(0) +#define PMECC_SR_ENABLE BIT(4) /* PMERRLOC Register Definitions */ struct pmecc_errloc_regs { @@ -141,15 +141,15 @@ struct pmecc_errloc_regs { /* For Error Location Configuration Register */ #define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) -#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0) +#define PMERRLOC_ELCFG_SECTOR_1024 BIT(0) #define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) /* For Error Location Disable Register */ -#define PMERRLOC_DISABLE (1 << 0) +#define PMERRLOC_DISABLE BIT(0) /* For Error Location Interrupt Status Register */ #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) -#define PMERRLOC_CALC_DONE (1 << 0) +#define PMERRLOC_CALC_DONE BIT(0) /* PMECC IP version */ #define PMECC_VERSION_SAMA5D4 0x113 diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index a397074..c203e38 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -757,12 +757,12 @@ static void nand_flash_init(void) acfg1 = 0 | (0 << 31) /* selectStrobe */ | (0 << 30) /* extWait */ - | (1 << 26) /* writeSetup 10 ns */ + | BIT(26) /* writeSetup 10 ns */ | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (1 << 13) /* readSetup 10 ns */ + | BIT(17) /* writeHold 10 ns */ + | BIT(13) /* readSetup 10 ns */ | (5 << 7) /* readStrobe 60 ns */ - | (1 << 4) /* readHold 10 ns */ + | BIT(4) /* readHold 10 ns */ | (3 << 2) /* turnAround ?? ns */ | (0 << 0) /* asyncSize 8-bit bus */ ; diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c index 22c5625..ad342dc 100644 --- a/drivers/mtd/nand/kb9202_nand.c +++ b/drivers/mtd/nand/kb9202_nand.c @@ -19,16 +19,16 @@ * hardware specific access to control-lines */ -#define MASK_ALE (1 << 22) /* our ALE is A22 */ -#define MASK_CLE (1 << 21) /* our CLE is A21 */ +#define MASK_ALE BIT(22) /* our ALE is A22 */ +#define MASK_CLE BIT(21) /* our CLE is A21 */ -#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ -#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ +#define KB9202_NAND_NCE BIT(28) /* EN* on D28 */ +#define KB9202_NAND_BUSY BIT(29) /* RB* on D29 */ -#define KB9202_SMC2_NWS (1 << 2) -#define KB9202_SMC2_TDF (1 << 8) -#define KB9202_SMC2_RWSETUP (1 << 24) -#define KB9202_SMC2_RWHOLD (1 << 29) +#define KB9202_SMC2_NWS BIT(2) +#define KB9202_SMC2_TDF BIT(8) +#define KB9202_SMC2_RWSETUP BIT(24) +#define KB9202_SMC2_RWHOLD BIT(29) /* * Board-specific function to access device control signals diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 4fc34d6..4193a74 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -37,9 +37,9 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, return; if (ctrl & NAND_CLE) - offs = (1 << 0); /* Commands with A[1:0] == 01 */ + offs = BIT(0); /* Commands with A[1:0] == 01 */ else if (ctrl & NAND_ALE) - offs = (1 << 1); /* Addresses with A[1:0] == 10 */ + offs = BIT(1); /* Addresses with A[1:0] == 10 */ else return; diff --git a/drivers/mtd/nand/kmeter1_nand.c b/drivers/mtd/nand/kmeter1_nand.c index df0bde5..5775d38 100644 --- a/drivers/mtd/nand/kmeter1_nand.c +++ b/drivers/mtd/nand/kmeter1_nand.c @@ -17,13 +17,13 @@ #define read_data() in_8(CONFIG_NAND_DATA_REG) #define write_data(val) out_8(CONFIG_NAND_DATA_REG, val) -#define KPN_RDY2 (1 << 7) -#define KPN_RDY1 (1 << 6) -#define KPN_WPN (1 << 4) -#define KPN_CE2N (1 << 3) -#define KPN_CE1N (1 << 2) -#define KPN_ALE (1 << 1) -#define KPN_CLE (1 << 0) +#define KPN_RDY2 BIT(7) +#define KPN_RDY1 BIT(6) +#define KPN_WPN BIT(4) +#define KPN_CE2N BIT(3) +#define KPN_CE1N BIT(2) +#define KPN_ALE BIT(1) +#define KPN_CLE BIT(0) #define KPN_DEFAULT_CHIP_DELAY 50 diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index e621c36..54e93e2 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -65,39 +65,39 @@ #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT) /* Bit Definitions: NFC_CONFIG */ -#define NFC_BLS_UNLOCKED (1 << 1) +#define NFC_BLS_UNLOCKED BIT(1) /* Bit Definitions: NFC_CONFIG1 */ -#define NFC_ECC_4BIT (1 << 0) -#define NFC_FULL_PAGE_DMA (1 << 1) -#define NFC_SPARE_ONLY (1 << 2) -#define NFC_ECC_ENABLE (1 << 3) -#define NFC_INT_MASK (1 << 4) -#define NFC_BIG_ENDIAN (1 << 5) -#define NFC_RESET (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) +#define NFC_ECC_4BIT BIT(0) +#define NFC_FULL_PAGE_DMA BIT(1) +#define NFC_SPARE_ONLY BIT(2) +#define NFC_ECC_ENABLE BIT(3) +#define NFC_INT_MASK BIT(4) +#define NFC_BIG_ENDIAN BIT(5) +#define NFC_RESET BIT(6) +#define NFC_CE BIT(7) +#define NFC_ONE_CYCLE BIT(8) #define NFC_PPB_32 (0 << 9) -#define NFC_PPB_64 (1 << 9) +#define NFC_PPB_64 BIT(9) #define NFC_PPB_128 (2 << 9) #define NFC_PPB_256 (3 << 9) #define NFC_PPB_MASK (3 << 9) -#define NFC_FULL_PAGE_INT (1 << 11) +#define NFC_FULL_PAGE_INT BIT(11) /* Bit Definitions: NFC_CONFIG2 */ -#define NFC_COMMAND (1 << 0) -#define NFC_ADDRESS (1 << 1) -#define NFC_INPUT (1 << 2) -#define NFC_OUTPUT (1 << 3) -#define NFC_ID (1 << 4) -#define NFC_STATUS (1 << 5) -#define NFC_CMD_FAIL (1 << 15) -#define NFC_INT (1 << 15) +#define NFC_COMMAND BIT(0) +#define NFC_ADDRESS BIT(1) +#define NFC_INPUT BIT(2) +#define NFC_OUTPUT BIT(3) +#define NFC_ID BIT(4) +#define NFC_STATUS BIT(5) +#define NFC_CMD_FAIL BIT(15) +#define NFC_INT BIT(15) /* Bit Definitions: NFC_WRPROT */ -#define NFC_WPC_LOCK_TIGHT (1 << 0) -#define NFC_WPC_LOCK (1 << 1) -#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_WPC_LOCK_TIGHT BIT(0) +#define NFC_WPC_LOCK BIT(1) +#define NFC_WPC_UNLOCK BIT(2) struct mpc5121_nfc_prv { struct mtd_info mtd; diff --git a/drivers/mtd/nand/mxc_nand.h b/drivers/mtd/nand/mxc_nand.h index a02d6e0..f887517 100644 --- a/drivers/mtd/nand/mxc_nand.h +++ b/drivers/mtd/nand/mxc_nand.h @@ -145,56 +145,56 @@ struct mxc_nand_ip_regs { #define NFC_STATUS 0x20 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) -#define NFC_CONFIG1_SP_EN (1 << 2) -#define NFC_CONFIG1_RST (1 << 6) -#define NFC_CONFIG1_CE (1 << 7) +#define NFC_CONFIG1_SP_EN BIT(2) +#define NFC_CONFIG1_RST BIT(6) +#define NFC_CONFIG1_CE BIT(7) #elif defined(MXC_NFC_V3_2) -#define NFC_CONFIG1_SP_EN (1 << 0) -#define NFC_CONFIG1_CE (1 << 1) -#define NFC_CONFIG1_RST (1 << 2) +#define NFC_CONFIG1_SP_EN BIT(0) +#define NFC_CONFIG1_CE BIT(1) +#define NFC_CONFIG1_RST BIT(2) #endif -#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) -#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) -#define NFC_V1_V2_CONFIG1_BIG (1 << 5) -#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) -#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) -#define NFC_V2_CONFIG1_FP_INT (1 << 11) +#define NFC_V1_V2_CONFIG1_ECC_EN BIT(3) +#define NFC_V1_V2_CONFIG1_INT_MSK BIT(4) +#define NFC_V1_V2_CONFIG1_BIG BIT(5) +#define NFC_V2_CONFIG1_ECC_MODE_4 BIT(0) +#define NFC_V2_CONFIG1_ONE_CYCLE BIT(8) +#define NFC_V2_CONFIG1_FP_INT BIT(11) #define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4) #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4) -#define NFC_V1_V2_CONFIG2_INT (1 << 15) +#define NFC_V1_V2_CONFIG2_INT BIT(15) #define NFC_V3_CONFIG2_PS_MASK (0x3 << 0) #define NFC_V3_CONFIG2_PS_512 (0 << 0) -#define NFC_V3_CONFIG2_PS_2048 (1 << 0) +#define NFC_V3_CONFIG2_PS_2048 BIT(0) #define NFC_V3_CONFIG2_PS_4096 (2 << 0) -#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) -#define NFC_V3_CONFIG2_ECC_EN (1 << 3) -#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) -#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5) -#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) +#define NFC_V3_CONFIG2_ONE_CYCLE BIT(2) +#define NFC_V3_CONFIG2_ECC_EN BIT(3) +#define NFC_V3_CONFIG2_2CMD_PHASES BIT(4) +#define NFC_V3_CONFIG2_NUM_ADDR_PH0 BIT(5) +#define NFC_V3_CONFIG2_ECC_MODE_8 BIT(6) #define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7) #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) #define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9) #define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9) #define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12) -#define NFC_V3_CONFIG2_INT_MSK (1 << 15) +#define NFC_V3_CONFIG2_INT_MSK BIT(15) #define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16) #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) #define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24) #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) -#define NFC_V3_CONFIG3_FW8 (1 << 3) +#define NFC_V3_CONFIG3_FW8 BIT(3) #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) #define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12) -#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) -#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) +#define NFC_V3_CONFIG3_RBB_MODE BIT(15) +#define NFC_V3_CONFIG3_NO_SDMA BIT(20) -#define NFC_V3_WRPROT_UNLOCK (1 << 2) +#define NFC_V3_WRPROT_UNLOCK BIT(2) #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) -#define NFC_V3_IPC_CREQ (1 << 0) -#define NFC_V3_IPC_INT (1 << 31) +#define NFC_V3_IPC_CREQ BIT(0) +#define NFC_V3_IPC_INT BIT(31) #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) #define operation config2 diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index c0e381a..31c597c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3256,15 +3256,15 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, /* Check version */ val = le16_to_cpu(p->revision); - if (val & (1 << 5)) + if (val & BIT(5)) chip->onfi_version = 23; - else if (val & (1 << 4)) + else if (val & BIT(4)) chip->onfi_version = 22; - else if (val & (1 << 3)) + else if (val & BIT(3)) chip->onfi_version = 21; - else if (val & (1 << 2)) + else if (val & BIT(2)) chip->onfi_version = 20; - else if (val & (1 << 1)) + else if (val & BIT(1)) chip->onfi_version = 10; if (!chip->onfi_version) { @@ -3369,9 +3369,9 @@ static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, /* Check version */ val = le16_to_cpu(p->revision); - if (val & (1 << 2)) + if (val & BIT(2)) chip->jedec_version = 10; - else if (val & (1 << 1)) + else if (val & BIT(1)) chip->jedec_version = 1; /* vendor specific version */ if (!chip->jedec_version) { diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c index a7cee51..af27c62 100644 --- a/drivers/mtd/nand/nomadik.c +++ b/drivers/mtd/nand/nomadik.c @@ -127,8 +127,8 @@ struct nand_ecclayout nomadik_ecc_layout = { .oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} }, }; -#define MASK_ALE (1 << 24) /* our ALE is AD21 */ -#define MASK_CLE (1 << 23) /* our CLE is AD22 */ +#define MASK_ALE BIT(24) /* our ALE is AD21 */ +#define MASK_CLE BIT(23) /* our CLE is AD22 */ /* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */ static void nomadik_nand_hwcontrol(struct mtd_info *mtd, diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 610f969..fbd563f 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -459,7 +459,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) -#define ENABLE_PREFETCH (1 << 7) +#define ENABLE_PREFETCH BIT(7) /** * omap_prefetch_enable - configures and starts prefetch transfer diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index b3a2a60..3ac73b3 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -117,7 +117,7 @@ int board_nand_init(struct nand_chip *nand) debug("board_nand_init()\n"); - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); + writel(readl(&clk_power->clkcon) | BIT(4), &clk_power->clkcon); /* initialize hardware */ #if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING) diff --git a/drivers/mtd/nand/tegra_nand.h b/drivers/mtd/nand/tegra_nand.h index ded9d71..caa6d553 100644 --- a/drivers/mtd/nand/tegra_nand.h +++ b/drivers/mtd/nand/tegra_nand.h @@ -6,30 +6,30 @@ /* register offset */ #define COMMAND_0 0x00 -#define CMD_GO (1 << 31) -#define CMD_CLE (1 << 30) -#define CMD_ALE (1 << 29) -#define CMD_PIO (1 << 28) -#define CMD_TX (1 << 27) -#define CMD_RX (1 << 26) -#define CMD_SEC_CMD (1 << 25) -#define CMD_AFT_DAT_MASK (1 << 24) +#define CMD_GO BIT(31) +#define CMD_CLE BIT(30) +#define CMD_ALE BIT(29) +#define CMD_PIO BIT(28) +#define CMD_TX BIT(27) +#define CMD_RX BIT(26) +#define CMD_SEC_CMD BIT(25) +#define CMD_AFT_DAT_MASK BIT(24) #define CMD_AFT_DAT_DISABLE 0 -#define CMD_AFT_DAT_ENABLE (1 << 24) +#define CMD_AFT_DAT_ENABLE BIT(24) #define CMD_TRANS_SIZE_SHIFT 20 #define CMD_TRANS_SIZE_PAGE 8 -#define CMD_A_VALID (1 << 19) -#define CMD_B_VALID (1 << 18) -#define CMD_RD_STATUS_CHK (1 << 17) -#define CMD_R_BSY_CHK (1 << 16) -#define CMD_CE7 (1 << 15) -#define CMD_CE6 (1 << 14) -#define CMD_CE5 (1 << 13) -#define CMD_CE4 (1 << 12) -#define CMD_CE3 (1 << 11) -#define CMD_CE2 (1 << 10) -#define CMD_CE1 (1 << 9) -#define CMD_CE0 (1 << 8) +#define CMD_A_VALID BIT(19) +#define CMD_B_VALID BIT(18) +#define CMD_RD_STATUS_CHK BIT(17) +#define CMD_R_BSY_CHK BIT(16) +#define CMD_CE7 BIT(15) +#define CMD_CE6 BIT(14) +#define CMD_CE5 BIT(13) +#define CMD_CE4 BIT(12) +#define CMD_CE3 BIT(11) +#define CMD_CE2 BIT(10) +#define CMD_CE1 BIT(9) +#define CMD_CE0 BIT(8) #define CMD_CLE_BYTE_SIZE_SHIFT 4 enum { CMD_CLE_BYTES1 = 0, @@ -50,51 +50,51 @@ enum { }; #define STATUS_0 0x04 -#define STATUS_RBSY0 (1 << 8) +#define STATUS_RBSY0 BIT(8) #define ISR_0 0x08 -#define ISR_IS_CMD_DONE (1 << 5) -#define ISR_IS_ECC_ERR (1 << 4) +#define ISR_IS_CMD_DONE BIT(5) +#define ISR_IS_ECC_ERR BIT(4) #define IER_0 0x0C #define CFG_0 0x10 -#define CFG_HW_ECC_MASK (1 << 31) +#define CFG_HW_ECC_MASK BIT(31) #define CFG_HW_ECC_DISABLE 0 -#define CFG_HW_ECC_ENABLE (1 << 31) -#define CFG_HW_ECC_SEL_MASK (1 << 30) +#define CFG_HW_ECC_ENABLE BIT(31) +#define CFG_HW_ECC_SEL_MASK BIT(30) #define CFG_HW_ECC_SEL_HAMMING 0 -#define CFG_HW_ECC_SEL_RS (1 << 30) -#define CFG_HW_ECC_CORRECTION_MASK (1 << 29) +#define CFG_HW_ECC_SEL_RS BIT(30) +#define CFG_HW_ECC_CORRECTION_MASK BIT(29) #define CFG_HW_ECC_CORRECTION_DISABLE 0 -#define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29) -#define CFG_PIPELINE_EN_MASK (1 << 28) +#define CFG_HW_ECC_CORRECTION_ENABLE BIT(29) +#define CFG_PIPELINE_EN_MASK BIT(28) #define CFG_PIPELINE_EN_DISABLE 0 -#define CFG_PIPELINE_EN_ENABLE (1 << 28) -#define CFG_ECC_EN_TAG_MASK (1 << 27) +#define CFG_PIPELINE_EN_ENABLE BIT(28) +#define CFG_ECC_EN_TAG_MASK BIT(27) #define CFG_ECC_EN_TAG_DISABLE 0 -#define CFG_ECC_EN_TAG_ENABLE (1 << 27) +#define CFG_ECC_EN_TAG_ENABLE BIT(27) #define CFG_TVALUE_MASK (3 << 24) enum { CFG_TVAL4 = 0 << 24, CFG_TVAL6 = 1 << 24, CFG_TVAL8 = 2 << 24 }; -#define CFG_SKIP_SPARE_MASK (1 << 23) +#define CFG_SKIP_SPARE_MASK BIT(23) #define CFG_SKIP_SPARE_DISABLE 0 -#define CFG_SKIP_SPARE_ENABLE (1 << 23) -#define CFG_COM_BSY_MASK (1 << 22) +#define CFG_SKIP_SPARE_ENABLE BIT(23) +#define CFG_COM_BSY_MASK BIT(22) #define CFG_COM_BSY_DISABLE 0 -#define CFG_COM_BSY_ENABLE (1 << 22) -#define CFG_BUS_WIDTH_MASK (1 << 21) +#define CFG_COM_BSY_ENABLE BIT(22) +#define CFG_BUS_WIDTH_MASK BIT(21) #define CFG_BUS_WIDTH_8BIT 0 -#define CFG_BUS_WIDTH_16BIT (1 << 21) -#define CFG_LPDDR1_MODE_MASK (1 << 20) +#define CFG_BUS_WIDTH_16BIT BIT(21) +#define CFG_LPDDR1_MODE_MASK BIT(20) #define CFG_LPDDR1_MODE_DISABLE 0 -#define CFG_LPDDR1_MODE_ENABLE (1 << 20) -#define CFG_EDO_MODE_MASK (1 << 19) +#define CFG_LPDDR1_MODE_ENABLE BIT(20) +#define CFG_EDO_MODE_MASK BIT(19) #define CFG_EDO_MODE_DISABLE 0 -#define CFG_EDO_MODE_ENABLE (1 << 19) +#define CFG_EDO_MODE_ENABLE BIT(19) #define CFG_PAGE_SIZE_SEL_MASK (7 << 16) enum { CFG_PAGE_SIZE_256 = 0 << 16, @@ -144,18 +144,18 @@ enum { #define ADDR_REG2_0 0x2C #define DMA_MST_CTRL_0 0x30 -#define DMA_MST_CTRL_GO_MASK (1 << 31) +#define DMA_MST_CTRL_GO_MASK BIT(31) #define DMA_MST_CTRL_GO_DISABLE 0 -#define DMA_MST_CTRL_GO_ENABLE (1 << 31) -#define DMA_MST_CTRL_DIR_MASK (1 << 30) +#define DMA_MST_CTRL_GO_ENABLE BIT(31) +#define DMA_MST_CTRL_DIR_MASK BIT(30) #define DMA_MST_CTRL_DIR_READ 0 -#define DMA_MST_CTRL_DIR_WRITE (1 << 30) -#define DMA_MST_CTRL_PERF_EN_MASK (1 << 29) +#define DMA_MST_CTRL_DIR_WRITE BIT(30) +#define DMA_MST_CTRL_PERF_EN_MASK BIT(29) #define DMA_MST_CTRL_PERF_EN_DISABLE 0 -#define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29) -#define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27) +#define DMA_MST_CTRL_PERF_EN_ENABLE BIT(29) +#define DMA_MST_CTRL_REUSE_BUFFER_MASK BIT(27) #define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0 -#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27) +#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE BIT(27) #define DMA_MST_CTRL_BURST_SIZE_SHIFT 24 #define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT) enum { @@ -164,13 +164,13 @@ enum { DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT, DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT }; -#define DMA_MST_CTRL_IS_DMA_DONE (1 << 20) -#define DMA_MST_CTRL_EN_A_MASK (1 << 2) +#define DMA_MST_CTRL_IS_DMA_DONE BIT(20) +#define DMA_MST_CTRL_EN_A_MASK BIT(2) #define DMA_MST_CTRL_EN_A_DISABLE 0 -#define DMA_MST_CTRL_EN_A_ENABLE (1 << 2) -#define DMA_MST_CTRL_EN_B_MASK (1 << 1) +#define DMA_MST_CTRL_EN_A_ENABLE BIT(2) +#define DMA_MST_CTRL_EN_B_MASK BIT(1) #define DMA_MST_CTRL_EN_B_DISABLE 0 -#define DMA_MST_CTRL_EN_B_ENABLE (1 << 1) +#define DMA_MST_CTRL_EN_B_ENABLE BIT(1) #define DMA_CFG_A_0 0x34 #define DMA_CFG_B_0 0x38 @@ -180,8 +180,8 @@ enum { #define ECC_PTR_0 0x48 #define DEC_STATUS_0 0x4C -#define DEC_STATUS_A_ECC_FAIL (1 << 1) -#define DEC_STATUS_B_ECC_FAIL (1 << 0) +#define DEC_STATUS_A_ECC_FAIL BIT(1) +#define DEC_STATUS_B_ECC_FAIL BIT(0) #define BCH_CONFIG_0 0xCC #define BCH_CONFIG_BCH_TVALUE_SHIFT 4 @@ -192,19 +192,19 @@ enum { BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT, BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT }; -#define BCH_CONFIG_BCH_ECC_MASK (1 << 0) +#define BCH_CONFIG_BCH_ECC_MASK BIT(0) #define BCH_CONFIG_BCH_ECC_DISABLE 0 -#define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0) +#define BCH_CONFIG_BCH_ECC_ENABLE BIT(0) #define BCH_DEC_RESULT_0 0xD0 -#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8) +#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK BIT(8) #define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF #define BCH_DEC_STATUS_BUF_0 0xD4 #define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000 #define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000 -#define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14) -#define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13) +#define BCH_DEC_STATUS_FAIL_TAG_MASK BIT(14) +#define BCH_DEC_STATUS_CORR_TAG_MASK BIT(13) #define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8) #define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index fe6b7d9..80e271f 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -26,7 +26,7 @@ enum onenand_spl_pagesize { #define ONENAND_PAGES_PER_BLOCK 64 #define onenand_block_address(block) (block) #define onenand_sector_address(page) (page << 2) -#define onenand_buffer_address() ((1 << 3) << 8) +#define onenand_buffer_address() (BIT(3) << 8) #define onenand_bufferram_address(block) (0) static inline uint16_t onenand_readw(uint32_t addr) diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index d576d31..54baa42 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -53,8 +53,8 @@ static const char *sandbox_sf_state_name(enum sandbox_sf_state state) } /* Bits for the status register */ -#define STAT_WIP (1 << 0) -#define STAT_WEL (1 << 1) +#define STAT_WIP BIT(0) +#define STAT_WEL BIT(1) /* Assume all SPI flashes have 3 byte addresses since they do atm */ #define SF_ADDR_LEN 3 diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4158e13..0e96b4d 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -92,10 +92,10 @@ enum { #endif /* Common status */ -#define STATUS_WIP (1 << 0) -#define STATUS_QEB_WINSPAN (1 << 1) -#define STATUS_QEB_MXIC (1 << 6) -#define STATUS_PEC (1 << 7) +#define STATUS_WIP BIT(0) +#define STATUS_QEB_WINSPAN BIT(1) +#define STATUS_QEB_MXIC BIT(6) +#define STATUS_PEC BIT(7) /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index fce0ff8..e7e2754 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -1190,7 +1190,7 @@ static void print_rsvd_warning(struct ubi_device *ubi, * The 1 << 18 (256KiB) number is picked randomly, just a reasonably * large number to distinguish between newly flashed and used images. */ - if (ai->max_sqnum > (1 << 18)) { + if (ai->max_sqnum > BIT(18)) { int min = ubi->beb_rsvd_level / 10; if (!min) diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h index 810a61726..be3f30d 100644 --- a/drivers/net/bcm-sf2-eth-gmac.h +++ b/drivers/net/bcm-sf2-eth-gmac.h @@ -100,9 +100,9 @@ /* flags for dma controller */ /* partity enable */ -#define DMA_CTRL_PEN (1 << 0) +#define DMA_CTRL_PEN BIT(0) /* rx overflow continue */ -#define DMA_CTRL_ROC (1 << 1) +#define DMA_CTRL_ROC BIT(1) /* receive descriptor table pointer */ /* last valid descriptor */ diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 427ad3e..4637e88 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -406,7 +406,7 @@ static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) u_int16_t data; if (davinci_eth_phy_read(phy_addr, 0, &data)) { - if (data & (1 << 6)) { /* speed selection MSB */ + if (data & BIT(6)) { /* speed selection MSB */ /* * Check if link detected is giga-bit * If Gigabit mode detected, enable gigbit in MAC diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h index 13cd68f..5ed3a57 100644 --- a/drivers/net/davinci_emac.h +++ b/drivers/net/davinci_emac.h @@ -67,12 +67,12 @@ typedef volatile struct _emac_desc #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) +#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) +#define EMAC_MACCONTROL_GIGFORCE BIT(17) +#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) +#define EMAC_MAC_ADDR_MATCH BIT(19) +#define EMAC_MAC_ADDR_IS_VALID BIT(20) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 4b9ec39..a8d6249 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -35,17 +35,17 @@ struct eth_mac_regs { }; /* MAC configuration register definitions */ -#define FRAMEBURSTENABLE (1 << 21) -#define MII_PORTSELECT (1 << 15) -#define FES_100 (1 << 14) -#define DISABLERXOWN (1 << 13) -#define FULLDPLXMODE (1 << 11) -#define RXENABLE (1 << 2) -#define TXENABLE (1 << 3) +#define FRAMEBURSTENABLE BIT(21) +#define MII_PORTSELECT BIT(15) +#define FES_100 BIT(14) +#define DISABLERXOWN BIT(13) +#define FULLDPLXMODE BIT(11) +#define RXENABLE BIT(2) +#define TXENABLE BIT(3) /* MII address register definitions */ -#define MII_BUSY (1 << 0) -#define MII_WRITE (1 << 1) +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) #define MII_CLKRANGE_60_100M (0) #define MII_CLKRANGE_100_150M (0x4) #define MII_CLKRANGE_20_35M (0x8) @@ -85,24 +85,24 @@ struct eth_dma_regs { #endif /* Bus mode register definitions */ -#define FIXEDBURST (1 << 16) +#define FIXEDBURST BIT(16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) -#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_21 BIT(14) #define PRIORXTX_11 (0 << 14) #define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) -#define RXHIGHPRIO (1 << 1) -#define DMAMAC_SRST (1 << 0) +#define RXHIGHPRIO BIT(1) +#define DMAMAC_SRST BIT(0) /* Poll demand definitions */ #define POLL_DATA (0xFFFFFFFF) /* Operation mode definitions */ -#define STOREFORWARD (1 << 21) -#define FLUSHTXFIFO (1 << 20) -#define TXSTART (1 << 13) -#define TXSECONDFRAME (1 << 2) -#define RXSTART (1 << 1) +#define STOREFORWARD BIT(21) +#define FLUSHTXFIFO BIT(20) +#define TXSTART BIT(13) +#define TXSECONDFRAME BIT(2) +#define RXSTART BIT(1) /* Descriptior related definitions */ #define MAC_MAX_FRAME_SZ (1600) @@ -121,46 +121,46 @@ struct dmamacdescr { /* tx status bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) -#define DESC_TXSTS_OWNBYDMA (1 << 31) -#define DESC_TXSTS_TXINT (1 << 30) -#define DESC_TXSTS_TXLAST (1 << 29) -#define DESC_TXSTS_TXFIRST (1 << 28) -#define DESC_TXSTS_TXCRCDIS (1 << 27) +#define DESC_TXSTS_OWNBYDMA BIT(31) +#define DESC_TXSTS_TXINT BIT(30) +#define DESC_TXSTS_TXLAST BIT(29) +#define DESC_TXSTS_TXFIRST BIT(28) +#define DESC_TXSTS_TXCRCDIS BIT(27) -#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXPADDIS BIT(26) #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) -#define DESC_TXSTS_TXRINGEND (1 << 21) -#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_TXRINGEND BIT(21) +#define DESC_TXSTS_TXCHAIN BIT(20) #define DESC_TXSTS_MSK (0x1FFFF << 0) #else -#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_OWNBYDMA BIT(31) #define DESC_TXSTS_MSK (0x1FFFF << 0) #endif /* rx status bits definitions */ -#define DESC_RXSTS_OWNBYDMA (1 << 31) -#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_OWNBYDMA BIT(31) +#define DESC_RXSTS_DAFILTERFAIL BIT(30) #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) #define DESC_RXSTS_FRMLENSHFT (16) -#define DESC_RXSTS_ERROR (1 << 15) -#define DESC_RXSTS_RXTRUNCATED (1 << 14) -#define DESC_RXSTS_SAFILTERFAIL (1 << 13) -#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) -#define DESC_RXSTS_RXDAMAGED (1 << 11) -#define DESC_RXSTS_RXVLANTAG (1 << 10) -#define DESC_RXSTS_RXFIRST (1 << 9) -#define DESC_RXSTS_RXLAST (1 << 8) -#define DESC_RXSTS_RXIPC_GIANT (1 << 7) -#define DESC_RXSTS_RXCOLLISION (1 << 6) -#define DESC_RXSTS_RXFRAMEETHER (1 << 5) -#define DESC_RXSTS_RXWATCHDOG (1 << 4) -#define DESC_RXSTS_RXMIIERROR (1 << 3) -#define DESC_RXSTS_RXDRIBBLING (1 << 2) -#define DESC_RXSTS_RXCRC (1 << 1) +#define DESC_RXSTS_ERROR BIT(15) +#define DESC_RXSTS_RXTRUNCATED BIT(14) +#define DESC_RXSTS_SAFILTERFAIL BIT(13) +#define DESC_RXSTS_RXIPC_GIANTFRAME BIT(12) +#define DESC_RXSTS_RXDAMAGED BIT(11) +#define DESC_RXSTS_RXVLANTAG BIT(10) +#define DESC_RXSTS_RXFIRST BIT(9) +#define DESC_RXSTS_RXLAST BIT(8) +#define DESC_RXSTS_RXIPC_GIANT BIT(7) +#define DESC_RXSTS_RXCOLLISION BIT(6) +#define DESC_RXSTS_RXFRAMEETHER BIT(5) +#define DESC_RXSTS_RXWATCHDOG BIT(4) +#define DESC_RXSTS_RXMIIERROR BIT(3) +#define DESC_RXSTS_RXDRIBBLING BIT(2) +#define DESC_RXSTS_RXCRC BIT(1) /* * dmamac_cntl definitions @@ -176,13 +176,13 @@ struct dmamacdescr { #else -#define DESC_TXCTRL_TXINT (1 << 31) -#define DESC_TXCTRL_TXLAST (1 << 30) -#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXINT BIT(31) +#define DESC_TXCTRL_TXLAST BIT(30) +#define DESC_TXCTRL_TXFIRST BIT(29) #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) -#define DESC_TXCTRL_TXCRCDIS (1 << 26) -#define DESC_TXCTRL_TXRINGEND (1 << 25) -#define DESC_TXCTRL_TXCHAIN (1 << 24) +#define DESC_TXCTRL_TXCRCDIS BIT(26) +#define DESC_TXCTRL_TXRINGEND BIT(25) +#define DESC_TXCTRL_TXCHAIN BIT(24) #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) #define DESC_TXCTRL_SIZE1SHFT (0) @@ -194,9 +194,9 @@ struct dmamacdescr { /* rx control bits definitions */ #if defined(CONFIG_DW_ALTDESCRIPTOR) -#define DESC_RXCTRL_RXINTDIS (1 << 31) -#define DESC_RXCTRL_RXRINGEND (1 << 15) -#define DESC_RXCTRL_RXCHAIN (1 << 14) +#define DESC_RXCTRL_RXINTDIS BIT(31) +#define DESC_RXCTRL_RXRINGEND BIT(15) +#define DESC_RXCTRL_RXCHAIN BIT(14) #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) #define DESC_RXCTRL_SIZE1SHFT (0) @@ -205,9 +205,9 @@ struct dmamacdescr { #else -#define DESC_RXCTRL_RXINTDIS (1 << 31) -#define DESC_RXCTRL_RXRINGEND (1 << 25) -#define DESC_RXCTRL_RXCHAIN (1 << 24) +#define DESC_RXCTRL_RXINTDIS BIT(31) +#define DESC_RXCTRL_RXRINGEND BIT(25) +#define DESC_RXCTRL_RXCHAIN BIT(24) #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) #define DESC_RXCTRL_SIZE1SHFT (0) diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c index 933d1fc..d3bfc93 100644 --- a/drivers/net/dnet.c +++ b/drivers/net/dnet.c @@ -79,7 +79,7 @@ static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value) ; /* prepare for a write operation */ - tmp = (1 << 13); + tmp = BIT(13); /* only 5 bits allowed for register offset */ reg &= 0x1f; diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h index fdb4fd2..5bbbaf3 100644 --- a/drivers/net/dnet.h +++ b/drivers/net/dnet.h @@ -80,80 +80,80 @@ struct dnet_registers { #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 -#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) +#define DNET_INTERNAL_GMII_MNG_CMD_FIN BIT(14) -#define DNET_INTERNAL_WRITE (1 << 31) +#define DNET_INTERNAL_WRITE BIT(31) /* MAC-CORE REGISTER FIELDS */ /* MAC-CORE MODE REGISTER FIELDS */ -#define DNET_INTERNAL_MODE_GBITEN (1 << 0) -#define DNET_INTERNAL_MODE_FCEN (1 << 1) -#define DNET_INTERNAL_MODE_RXEN (1 << 2) -#define DNET_INTERNAL_MODE_TXEN (1 << 3) +#define DNET_INTERNAL_MODE_GBITEN BIT(0) +#define DNET_INTERNAL_MODE_FCEN BIT(1) +#define DNET_INTERNAL_MODE_RXEN BIT(2) +#define DNET_INTERNAL_MODE_TXEN BIT(3) /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ -#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) -#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) -#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) -#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) -#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) -#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) -#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) -#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) -#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) +#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME BIT(8) +#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST BIT(7) +#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST BIT(4) +#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE BIT(3) +#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS BIT(2) +#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS BIT(1) +#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC BIT(0) +#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL BIT(6) +#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP BIT(5) /* SYSTEM CONTROL REGISTER FIELDS */ -#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) -#define DNET_SYS_CTL_SENDPAUSE (1 << 2) -#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) -#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) +#define DNET_SYS_CTL_IGNORENEXTPKT BIT(0) +#define DNET_SYS_CTL_SENDPAUSE BIT(2) +#define DNET_SYS_CTL_RXFIFOFLUSH BIT(3) +#define DNET_SYS_CTL_TXFIFOFLUSH BIT(4) /* TX STATUS REGISTER FIELDS */ -#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) -#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) +#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY BIT(2) +#define DNET_TX_STATUS_FIFO_ALMOST_FULL BIT(1) /* INTERRUPT SOURCE REGISTER FIELDS */ -#define DNET_INTR_SRC_TX_PKTSENT (1 << 0) -#define DNET_INTR_SRC_TX_FIFOAF (1 << 1) -#define DNET_INTR_SRC_TX_FIFOAE (1 << 2) -#define DNET_INTR_SRC_TX_DISCFRM (1 << 3) -#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) -#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) -#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) -#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) -#define DNET_INTR_SRC_TX_SUMMARY (1 << 16) -#define DNET_INTR_SRC_RX_SUMMARY (1 << 17) -#define DNET_INTR_SRC_PHY (1 << 19) +#define DNET_INTR_SRC_TX_PKTSENT BIT(0) +#define DNET_INTR_SRC_TX_FIFOAF BIT(1) +#define DNET_INTR_SRC_TX_FIFOAE BIT(2) +#define DNET_INTR_SRC_TX_DISCFRM BIT(3) +#define DNET_INTR_SRC_TX_FIFOFULL BIT(4) +#define DNET_INTR_SRC_RX_CMDFIFOAF BIT(8) +#define DNET_INTR_SRC_RX_CMDFIFOFF BIT(9) +#define DNET_INTR_SRC_RX_DATAFIFOFF BIT(10) +#define DNET_INTR_SRC_TX_SUMMARY BIT(16) +#define DNET_INTR_SRC_RX_SUMMARY BIT(17) +#define DNET_INTR_SRC_PHY BIT(19) /* INTERRUPT ENABLE REGISTER FIELDS */ -#define DNET_INTR_ENB_TX_PKTSENT (1 << 0) -#define DNET_INTR_ENB_TX_FIFOAF (1 << 1) -#define DNET_INTR_ENB_TX_FIFOAE (1 << 2) -#define DNET_INTR_ENB_TX_DISCFRM (1 << 3) -#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) -#define DNET_INTR_ENB_RX_PKTRDY (1 << 8) -#define DNET_INTR_ENB_RX_FIFOAF (1 << 9) -#define DNET_INTR_ENB_RX_FIFOERR (1 << 10) -#define DNET_INTR_ENB_RX_ERROR (1 << 11) -#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) -#define DNET_INTR_ENB_RX_FIFOAE (1 << 13) -#define DNET_INTR_ENB_TX_SUMMARY (1 << 16) -#define DNET_INTR_ENB_RX_SUMMARY (1 << 17) -#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) +#define DNET_INTR_ENB_TX_PKTSENT BIT(0) +#define DNET_INTR_ENB_TX_FIFOAF BIT(1) +#define DNET_INTR_ENB_TX_FIFOAE BIT(2) +#define DNET_INTR_ENB_TX_DISCFRM BIT(3) +#define DNET_INTR_ENB_TX_FIFOFULL BIT(4) +#define DNET_INTR_ENB_RX_PKTRDY BIT(8) +#define DNET_INTR_ENB_RX_FIFOAF BIT(9) +#define DNET_INTR_ENB_RX_FIFOERR BIT(10) +#define DNET_INTR_ENB_RX_ERROR BIT(11) +#define DNET_INTR_ENB_RX_FIFOFULL BIT(12) +#define DNET_INTR_ENB_RX_FIFOAE BIT(13) +#define DNET_INTR_ENB_TX_SUMMARY BIT(16) +#define DNET_INTR_ENB_RX_SUMMARY BIT(17) +#define DNET_INTR_ENB_GLOBAL_ENABLE BIT(18) /* * Capabilities. Used by the driver to know the capabilities that * the ethernet controller inside the FPGA have. */ -#define DNET_HAS_MDIO (1 << 0) -#define DNET_HAS_IRQ (1 << 1) -#define DNET_HAS_GIGABIT (1 << 2) -#define DNET_HAS_DMA (1 << 3) +#define DNET_HAS_MDIO BIT(0) +#define DNET_HAS_IRQ BIT(1) +#define DNET_HAS_GIGABIT BIT(2) +#define DNET_HAS_DMA BIT(3) -#define DNET_HAS_MII (1 << 4) /* or GMII */ -#define DNET_HAS_RMII (1 << 5) /* or RGMII */ +#define DNET_HAS_MII BIT(4) /* or GMII */ +#define DNET_HAS_RMII BIT(5) /* or RGMII */ #define DNET_CAPS_MASK 0xFFFF @@ -161,6 +161,6 @@ struct dnet_registers { #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ #define DNET_FIFO_TX_DATA_AE_TH (384) -#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ +#define DNET_FIFO_RX_CMD_AF_TH BIT(16) /* just one frame inside the FIFO */ #endif diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 96e6bb0..8603d0c 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1524,7 +1524,7 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) /* link autonegotiation/sync workarounds */ reg_tarc0 = E1000_READ_REG(hw, TARC0); - reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + reg_tarc0 &= ~(BIT(30)|BIT(29)|BIT(28)|BIT(27)); /* Enable not-done TX descriptor counting */ reg_txdctl = E1000_READ_REG(hw, TXDCTL); @@ -1544,32 +1544,32 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) case e1000_82572: /* Clear PHY TX compatible mode bits */ reg_tarc1 = E1000_READ_REG(hw, TARC1); - reg_tarc1 &= ~((1 << 30)|(1 << 29)); + reg_tarc1 &= ~(BIT(30)|BIT(29)); /* link autonegotiation/sync workarounds */ - reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); + reg_tarc0 |= (BIT(26)|BIT(25)|BIT(24)|BIT(23)); /* TX ring control fixes */ - reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); + reg_tarc1 |= (BIT(26)|BIT(25)|BIT(24)); /* Multiple read bit is reversed polarity */ reg_tctl = E1000_READ_REG(hw, TCTL); if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~(1 << 28); + reg_tarc1 &= ~BIT(28); else - reg_tarc1 |= (1 << 28); + reg_tarc1 |= BIT(28); E1000_WRITE_REG(hw, TARC1, reg_tarc1); break; case e1000_82573: case e1000_82574: reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - reg_ctrl_ext &= ~(1 << 23); - reg_ctrl_ext |= (1 << 22); + reg_ctrl_ext &= ~BIT(23); + reg_ctrl_ext |= BIT(22); /* TX byte count fix */ reg_ctrl = E1000_READ_REG(hw, CTRL); - reg_ctrl &= ~(1 << 29); + reg_ctrl &= ~BIT(29); E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); E1000_WRITE_REG(hw, CTRL, reg_ctrl); @@ -1579,16 +1579,16 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) if ((hw->media_type == e1000_media_type_fiber) || (hw->media_type == e1000_media_type_internal_serdes)) { - reg_tarc0 &= ~(1 << 20); + reg_tarc0 &= ~BIT(20); } /* Multiple read bit is reversed polarity */ reg_tctl = E1000_READ_REG(hw, TCTL); reg_tarc1 = E1000_READ_REG(hw, TARC1); if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~(1 << 28); + reg_tarc1 &= ~BIT(28); else - reg_tarc1 |= (1 << 28); + reg_tarc1 |= BIT(28); E1000_WRITE_REG(hw, TARC1, reg_tarc1); break; @@ -1597,25 +1597,25 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) if ((hw->revision_id < 3) || ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) - reg_tarc0 |= ((1 << 29)|(1 << 28)); + reg_tarc0 |= (BIT(29)|BIT(28)); reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); - reg_ctrl_ext |= (1 << 22); + reg_ctrl_ext |= BIT(22); E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); /* workaround TX hang with TSO=on */ - reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); + reg_tarc0 |= (BIT(27)|BIT(26)|BIT(24)|BIT(23)); /* Multiple read bit is reversed polarity */ reg_tctl = E1000_READ_REG(hw, TCTL); reg_tarc1 = E1000_READ_REG(hw, TARC1); if (reg_tctl & E1000_TCTL_MULR) - reg_tarc1 &= ~(1 << 28); + reg_tarc1 &= ~BIT(28); else - reg_tarc1 |= (1 << 28); + reg_tarc1 |= BIT(28); /* workaround TX hang with TSO=on */ - reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); + reg_tarc1 |= (BIT(30)|BIT(26)|BIT(24)); E1000_WRITE_REG(hw, TARC1, reg_tarc1); break; diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index f2cd32c..bad5390 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -272,7 +272,7 @@ static int get_phyreg (struct eth_device *dev, unsigned char addr, do { udelay(1000); cmd = INL (dev, SCBCtrlMDI); - } while (!(cmd & (1 << 28)) && (--timeout)); + } while (!(cmd & BIT(28)) && (--timeout)); if (timeout == 0) return -1; @@ -289,10 +289,10 @@ static int set_phyreg (struct eth_device *dev, unsigned char addr, int timeout = 50; /* write requested data */ - cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + cmd = BIT(26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); OUTL (dev, cmd | value, SCBCtrlMDI); - while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) + while (!(INL (dev, SCBCtrlMDI) & BIT(28)) && (--timeout)) udelay(1000); if (timeout == 0) diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c index a3721c5..2fb9441 100644 --- a/drivers/net/ep93xx_eth.c +++ b/drivers/net/ep93xx_eth.c @@ -564,7 +564,7 @@ static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, */ self_ctl = readl(&mac->selfctl); #if defined(CONFIG_MII_SUPPRESS_PREAMBLE) - writel(self_ctl & ~(1 << 8), &mac->selfctl); + writel(self_ctl & ~BIT(8), &mac->selfctl); #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(&mac->miists) & MIISTS_BUSY) @@ -615,7 +615,7 @@ static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, */ self_ctl = readl(&mac->selfctl); #if defined(CONFIG_MII_SUPPRESS_PREAMBLE) - writel(self_ctl & ~(1 << 8), &mac->selfctl); + writel(self_ctl & ~BIT(8), &mac->selfctl); #endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(&mac->miists) & MIISTS_BUSY) diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h index e6c949f..59a5c86 100644 --- a/drivers/net/ep93xx_eth.h +++ b/drivers/net/ep93xx_eth.h @@ -62,7 +62,7 @@ struct tx_descriptor { uint32_t word2; }; -#define TX_DESC_EOF (1 << 31) +#define TX_DESC_EOF BIT(31) /** * Transmit status queue entry diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index edb3c80..0a21bc3 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -53,22 +53,22 @@ #define MODER_LOOP (1 << 7) /* loopback */ #define MODER_NBO (1 << 8) /* no back-off */ #define MODER_EDE (1 << 9) /* excess defer enable */ -#define MODER_FULLD (1 << 10) /* full duplex */ -#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ -#define MODER_DCRC (1 << 12) /* delayed CRC enable */ -#define MODER_CRC (1 << 13) /* CRC enable */ -#define MODER_HUGE (1 << 14) /* huge packets enable */ -#define MODER_PAD (1 << 15) /* padding enabled */ -#define MODER_RSM (1 << 16) /* receive small packets */ +#define MODER_FULLD BIT(10) /* full duplex */ +#define MODER_RESET BIT(11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC BIT(12) /* delayed CRC enable */ +#define MODER_CRC BIT(13) /* CRC enable */ +#define MODER_HUGE BIT(14) /* huge packets enable */ +#define MODER_PAD BIT(15) /* padding enabled */ +#define MODER_RSM BIT(16) /* receive small packets */ /* interrupt source and mask registers */ -#define INT_MASK_TXF (1 << 0) /* transmit frame */ -#define INT_MASK_TXE (1 << 1) /* transmit error */ -#define INT_MASK_RXF (1 << 2) /* receive frame */ -#define INT_MASK_RXE (1 << 3) /* receive error */ -#define INT_MASK_BUSY (1 << 4) -#define INT_MASK_TXC (1 << 5) /* transmit control frame */ -#define INT_MASK_RXC (1 << 6) /* receive control frame */ +#define INT_MASK_TXF BIT(0) /* transmit frame */ +#define INT_MASK_TXE BIT(1) /* transmit error */ +#define INT_MASK_RXF BIT(2) /* receive frame */ +#define INT_MASK_RXE BIT(3) /* receive error */ +#define INT_MASK_BUSY BIT(4) +#define INT_MASK_TXC BIT(5) /* transmit control frame */ +#define INT_MASK_RXC BIT(6) /* receive control frame */ #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) @@ -90,18 +90,18 @@ #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) /* control module mode register */ -#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ -#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ -#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ +#define CTRLMODER_PASSALL BIT(0) /* pass all receive frames */ +#define CTRLMODER_RXFLOW BIT(1) /* receive control flow */ +#define CTRLMODER_TXFLOW BIT(2) /* transmit control flow */ /* MII mode register */ #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ -#define MIIMODER_NOPRE (1 << 8) /* no preamble */ +#define MIIMODER_NOPRE BIT(8) /* no preamble */ /* MII command register */ -#define MIICOMMAND_SCAN (1 << 0) /* scan status */ -#define MIICOMMAND_READ (1 << 1) /* read status */ -#define MIICOMMAND_WRITE (1 << 2) /* write control data */ +#define MIICOMMAND_SCAN BIT(0) /* scan status */ +#define MIICOMMAND_READ BIT(1) /* read status */ +#define MIICOMMAND_WRITE BIT(2) /* write control data */ /* MII address register */ #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) @@ -116,9 +116,9 @@ #define MIIRX_DATA_VAL(x) ((x) & 0xffff) /* MII status register */ -#define MIISTATUS_LINKFAIL (1 << 0) -#define MIISTATUS_BUSY (1 << 1) -#define MIISTATUS_INVALID (1 << 2) +#define MIISTATUS_LINKFAIL BIT(0) +#define MIISTATUS_BUSY BIT(1) +#define MIISTATUS_INVALID BIT(2) /* TX buffer descriptor */ #define TX_BD_CS (1 << 0) /* carrier sense lost */ @@ -128,11 +128,11 @@ #define TX_BD_RETRY_MASK (0x00f0) #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) #define TX_BD_UR (1 << 8) /* transmitter underrun */ -#define TX_BD_CRC (1 << 11) /* TX CRC enable */ -#define TX_BD_PAD (1 << 12) /* pad enable */ -#define TX_BD_WRAP (1 << 13) -#define TX_BD_IRQ (1 << 14) /* interrupt request enable */ -#define TX_BD_READY (1 << 15) /* TX buffer ready */ +#define TX_BD_CRC BIT(11) /* TX CRC enable */ +#define TX_BD_PAD BIT(12) /* pad enable */ +#define TX_BD_WRAP BIT(13) +#define TX_BD_IRQ BIT(14) /* interrupt request enable */ +#define TX_BD_READY BIT(15) /* TX buffer ready */ #define TX_BD_LEN(x) (((x) & 0xffff) << 16) #define TX_BD_LEN_MASK (0xffff << 16) @@ -149,9 +149,9 @@ #define RX_BD_OR (1 << 6) /* receiver overrun */ #define RX_BD_MISS (1 << 7) #define RX_BD_CF (1 << 8) /* control frame */ -#define RX_BD_WRAP (1 << 13) -#define RX_BD_IRQ (1 << 14) /* interrupt request enable */ -#define RX_BD_EMPTY (1 << 15) +#define RX_BD_WRAP BIT(13) +#define RX_BD_IRQ BIT(14) /* interrupt request enable */ +#define RX_BD_EMPTY BIT(15) #define RX_BD_LEN(x) (((x) & 0xffff) << 16) #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 0717cc6..fb9e514 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -205,21 +205,21 @@ struct ethernet_regs { #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) /* defines for MIIGSK */ /* RMII frequency control: 0=50MHz, 1=5MHz */ -#define MIIGSK_CFGR_FRCONT (1 << 6) +#define MIIGSK_CFGR_FRCONT BIT(6) /* loopback mode */ -#define MIIGSK_CFGR_LBMODE (1 << 4) +#define MIIGSK_CFGR_LBMODE BIT(4) /* echo mode */ -#define MIIGSK_CFGR_EMODE (1 << 3) +#define MIIGSK_CFGR_EMODE BIT(3) /* MII gasket mode field */ #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0) /* MMI/7-Wire mode */ #define MIIGSK_CFGR_IF_MODE_MII (0 << 0) /* RMII mode */ -#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0) +#define MIIGSK_CFGR_IF_MODE_RMII BIT(0) /* reflects MIIGSK Enable bit (RO) */ -#define MIIGSK_ENR_READY (1 << 2) +#define MIIGSK_ENR_READY BIT(2) /* enable MIGSK (set by default) */ -#define MIIGSK_ENR_EN (1 << 1) +#define MIIGSK_ENR_EN BIT(1) #endif /** diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index 71121ba..76c87af 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -71,48 +71,48 @@ struct ftgmac100 { /* * Interrupt status register & interrupt enable register */ -#define FTGMAC100_INT_RPKT_BUF (1 << 0) -#define FTGMAC100_INT_RPKT_FIFO (1 << 1) -#define FTGMAC100_INT_NO_RXBUF (1 << 2) -#define FTGMAC100_INT_RPKT_LOST (1 << 3) -#define FTGMAC100_INT_XPKT_ETH (1 << 4) -#define FTGMAC100_INT_XPKT_FIFO (1 << 5) -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) -#define FTGMAC100_INT_XPKT_LOST (1 << 7) -#define FTGMAC100_INT_AHB_ERR (1 << 8) -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) +#define FTGMAC100_INT_RPKT_BUF BIT(0) +#define FTGMAC100_INT_RPKT_FIFO BIT(1) +#define FTGMAC100_INT_NO_RXBUF BIT(2) +#define FTGMAC100_INT_RPKT_LOST BIT(3) +#define FTGMAC100_INT_XPKT_ETH BIT(4) +#define FTGMAC100_INT_XPKT_FIFO BIT(5) +#define FTGMAC100_INT_NO_NPTXBUF BIT(6) +#define FTGMAC100_INT_XPKT_LOST BIT(7) +#define FTGMAC100_INT_AHB_ERR BIT(8) +#define FTGMAC100_INT_PHYSTS_CHG BIT(9) +#define FTGMAC100_INT_NO_HPTXBUF BIT(10) /* * Interrupt timer control register */ #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) /* * Automatic polling timer control register */ #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) /* * DMA burst length and arbitration control register */ #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6) #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) -#define FTGMAC100_DBLAC_IFG_INC (1 << 23) +#define FTGMAC100_DBLAC_IFG_INC BIT(23) /* * DMA FIFO status register @@ -123,12 +123,12 @@ struct ftgmac100 { #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) /* * Receive buffer size register @@ -138,26 +138,26 @@ struct ftgmac100 { /* * MAC control register */ -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) -#define FTGMAC100_MACCR_RM_VLAN (1 << 4) -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) -#define FTGMAC100_MACCR_LOOP_EN (1 << 6) -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) -#define FTGMAC100_MACCR_FULLDUP (1 << 8) -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) -#define FTGMAC100_MACCR_CRC_APD (1 << 10) -#define FTGMAC100_MACCR_RX_RUNT (1 << 12) -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) -#define FTGMAC100_MACCR_RX_ALL (1 << 14) -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) -#define FTGMAC100_MACCR_FAST_MODE (1 << 19) -#define FTGMAC100_MACCR_SW_RST (1 << 31) +#define FTGMAC100_MACCR_TXDMA_EN BIT(0) +#define FTGMAC100_MACCR_RXDMA_EN BIT(1) +#define FTGMAC100_MACCR_TXMAC_EN BIT(2) +#define FTGMAC100_MACCR_RXMAC_EN BIT(3) +#define FTGMAC100_MACCR_RM_VLAN BIT(4) +#define FTGMAC100_MACCR_HPTXR_EN BIT(5) +#define FTGMAC100_MACCR_LOOP_EN BIT(6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) +#define FTGMAC100_MACCR_FULLDUP BIT(8) +#define FTGMAC100_MACCR_GIGA_MODE BIT(9) +#define FTGMAC100_MACCR_CRC_APD BIT(10) +#define FTGMAC100_MACCR_RX_RUNT BIT(12) +#define FTGMAC100_MACCR_JUMBO_LF BIT(13) +#define FTGMAC100_MACCR_RX_ALL BIT(14) +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17) +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) +#define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_SW_RST BIT(31) /* * PHY control register @@ -166,8 +166,8 @@ struct ftgmac100 { #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) -#define FTGMAC100_PHYCR_MIIRD (1 << 26) -#define FTGMAC100_PHYCR_MIIWR (1 << 27) +#define FTGMAC100_PHYCR_MIIRD BIT(26) +#define FTGMAC100_PHYCR_MIIWR BIT(27) /* * PHY data register @@ -186,20 +186,20 @@ struct ftgmac100_txdes { } __attribute__ ((aligned(16))); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) -#define FTGMAC100_TXDES0_EDOTR (1 << 15) -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_TXDES0_LTS (1 << 28) -#define FTGMAC100_TXDES0_FTS (1 << 29) -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) +#define FTGMAC100_TXDES0_EDOTR BIT(15) +#define FTGMAC100_TXDES0_CRC_ERR BIT(19) +#define FTGMAC100_TXDES0_LTS BIT(28) +#define FTGMAC100_TXDES0_FTS BIT(29) +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) -#define FTGMAC100_TXDES1_LLC (1 << 22) -#define FTGMAC100_TXDES1_TX2FIC (1 << 30) -#define FTGMAC100_TXDES1_TXIC (1 << 31) +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) +#define FTGMAC100_TXDES1_LLC BIT(22) +#define FTGMAC100_TXDES1_TX2FIC BIT(30) +#define FTGMAC100_TXDES1_TXIC BIT(31) /* * Receive descriptor, aligned to 16 bytes @@ -212,20 +212,20 @@ struct ftgmac100_rxdes { } __attribute__ ((aligned(16))); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) -#define FTGMAC100_RXDES0_EDORR (1 << 15) -#define FTGMAC100_RXDES0_MULTICAST (1 << 16) -#define FTGMAC100_RXDES0_BROADCAST (1 << 17) -#define FTGMAC100_RXDES0_RX_ERR (1 << 18) -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_RXDES0_FTL (1 << 20) -#define FTGMAC100_RXDES0_RUNT (1 << 21) -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) -#define FTGMAC100_RXDES0_LRS (1 << 28) -#define FTGMAC100_RXDES0_FRS (1 << 29) -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) +#define FTGMAC100_RXDES0_EDORR BIT(15) +#define FTGMAC100_RXDES0_MULTICAST BIT(16) +#define FTGMAC100_RXDES0_BROADCAST BIT(17) +#define FTGMAC100_RXDES0_RX_ERR BIT(18) +#define FTGMAC100_RXDES0_CRC_ERR BIT(19) +#define FTGMAC100_RXDES0_FTL BIT(20) +#define FTGMAC100_RXDES0_RUNT BIT(21) +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) +#define FTGMAC100_RXDES0_LRS BIT(28) +#define FTGMAC100_RXDES0_FRS BIT(29) +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) @@ -233,11 +233,11 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) -#define FTGMAC100_RXDES1_LLC (1 << 22) -#define FTGMAC100_RXDES1_DF (1 << 23) -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +#define FTGMAC100_RXDES1_LLC BIT(22) +#define FTGMAC100_RXDES1_DF BIT(23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) #endif /* __FTGMAC100_H */ diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h index b674d02..3ec0b42 100644 --- a/drivers/net/ftmac100.h +++ b/drivers/net/ftmac100.h @@ -54,44 +54,44 @@ struct ftmac100 { /* * Interrupt status register & interrupt mask register */ -#define FTMAC100_INT_RPKT_FINISH (1 << 0) -#define FTMAC100_INT_NORXBUF (1 << 1) -#define FTMAC100_INT_XPKT_FINISH (1 << 2) -#define FTMAC100_INT_NOTXBUF (1 << 3) -#define FTMAC100_INT_XPKT_OK (1 << 4) -#define FTMAC100_INT_XPKT_LOST (1 << 5) -#define FTMAC100_INT_RPKT_SAV (1 << 6) -#define FTMAC100_INT_RPKT_LOST (1 << 7) -#define FTMAC100_INT_AHB_ERR (1 << 8) -#define FTMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTMAC100_INT_RPKT_FINISH BIT(0) +#define FTMAC100_INT_NORXBUF BIT(1) +#define FTMAC100_INT_XPKT_FINISH BIT(2) +#define FTMAC100_INT_NOTXBUF BIT(3) +#define FTMAC100_INT_XPKT_OK BIT(4) +#define FTMAC100_INT_XPKT_LOST BIT(5) +#define FTMAC100_INT_RPKT_SAV BIT(6) +#define FTMAC100_INT_RPKT_LOST BIT(7) +#define FTMAC100_INT_AHB_ERR BIT(8) +#define FTMAC100_INT_PHYSTS_CHG BIT(9) /* * Automatic polling timer control register */ #define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) -#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTMAC100_APTC_RXPOLL_TIME_SEL BIT(4) #define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) -#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) +#define FTMAC100_APTC_TXPOLL_TIME_SEL BIT(12) /* * MAC control register */ -#define FTMAC100_MACCR_XDMA_EN (1 << 0) -#define FTMAC100_MACCR_RDMA_EN (1 << 1) -#define FTMAC100_MACCR_SW_RST (1 << 2) -#define FTMAC100_MACCR_LOOP_EN (1 << 3) -#define FTMAC100_MACCR_CRC_DIS (1 << 4) -#define FTMAC100_MACCR_XMT_EN (1 << 5) -#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) -#define FTMAC100_MACCR_RCV_EN (1 << 8) -#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) -#define FTMAC100_MACCR_RX_RUNT (1 << 10) -#define FTMAC100_MACCR_RX_FTL (1 << 11) -#define FTMAC100_MACCR_RCV_ALL (1 << 12) -#define FTMAC100_MACCR_CRC_APD (1 << 14) -#define FTMAC100_MACCR_FULLDUP (1 << 15) -#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) -#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTMAC100_MACCR_XDMA_EN BIT(0) +#define FTMAC100_MACCR_RDMA_EN BIT(1) +#define FTMAC100_MACCR_SW_RST BIT(2) +#define FTMAC100_MACCR_LOOP_EN BIT(3) +#define FTMAC100_MACCR_CRC_DIS BIT(4) +#define FTMAC100_MACCR_XMT_EN BIT(5) +#define FTMAC100_MACCR_ENRX_IN_HALFTX BIT(6) +#define FTMAC100_MACCR_RCV_EN BIT(8) +#define FTMAC100_MACCR_HT_MULTI_EN BIT(9) +#define FTMAC100_MACCR_RX_RUNT BIT(10) +#define FTMAC100_MACCR_RX_FTL BIT(11) +#define FTMAC100_MACCR_RCV_ALL BIT(12) +#define FTMAC100_MACCR_CRC_APD BIT(14) +#define FTMAC100_MACCR_FULLDUP BIT(15) +#define FTMAC100_MACCR_RX_MULTIPKT BIT(16) +#define FTMAC100_MACCR_RX_BROADPKT BIT(17) /* * Transmit descriptor, aligned to 16 bytes @@ -103,16 +103,16 @@ struct ftmac100_txdes { unsigned int txdes3; /* not used by HW */ } __attribute__ ((aligned(16))); -#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) -#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) -#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) +#define FTMAC100_TXDES0_TXPKT_LATECOL BIT(0) +#define FTMAC100_TXDES0_TXPKT_EXSCOL BIT(1) +#define FTMAC100_TXDES0_TXDMA_OWN BIT(31) #define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) -#define FTMAC100_TXDES1_LTS (1 << 27) -#define FTMAC100_TXDES1_FTS (1 << 28) -#define FTMAC100_TXDES1_TX2FIC (1 << 29) -#define FTMAC100_TXDES1_TXIC (1 << 30) -#define FTMAC100_TXDES1_EDOTR (1 << 31) +#define FTMAC100_TXDES1_LTS BIT(27) +#define FTMAC100_TXDES1_FTS BIT(28) +#define FTMAC100_TXDES1_TX2FIC BIT(29) +#define FTMAC100_TXDES1_TXIC BIT(30) +#define FTMAC100_TXDES1_EDOTR BIT(31) /* * Receive descriptor, aligned to 16 bytes @@ -125,18 +125,18 @@ struct ftmac100_rxdes { } __attribute__ ((aligned(16))); #define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) -#define FTMAC100_RXDES0_MULTICAST (1 << 16) -#define FTMAC100_RXDES0_BROADCAST (1 << 17) -#define FTMAC100_RXDES0_RX_ERR (1 << 18) -#define FTMAC100_RXDES0_CRC_ERR (1 << 19) -#define FTMAC100_RXDES0_FTL (1 << 20) -#define FTMAC100_RXDES0_RUNT (1 << 21) -#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) -#define FTMAC100_RXDES0_LRS (1 << 28) -#define FTMAC100_RXDES0_FRS (1 << 29) -#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) +#define FTMAC100_RXDES0_MULTICAST BIT(16) +#define FTMAC100_RXDES0_BROADCAST BIT(17) +#define FTMAC100_RXDES0_RX_ERR BIT(18) +#define FTMAC100_RXDES0_CRC_ERR BIT(19) +#define FTMAC100_RXDES0_FTL BIT(20) +#define FTMAC100_RXDES0_RUNT BIT(21) +#define FTMAC100_RXDES0_RX_ODD_NB BIT(22) +#define FTMAC100_RXDES0_LRS BIT(28) +#define FTMAC100_RXDES0_FRS BIT(29) +#define FTMAC100_RXDES0_RXDMA_OWN BIT(31) #define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) -#define FTMAC100_RXDES1_EDORR (1 << 31) +#define FTMAC100_RXDES1_EDORR BIT(31) #endif /* __FTMAC100_H */ diff --git a/drivers/net/ftmac110.h b/drivers/net/ftmac110.h index 2772ae7..f655cbb 100644 --- a/drivers/net/ftmac110.h +++ b/drivers/net/ftmac110.h @@ -37,43 +37,43 @@ struct ftmac110_regs { * Interrupt status/mask register(ISR/IMR) bits */ #define ISR_ALL 0x3ff -#define ISR_PHYSTCHG (1 << 9) /* phy status change */ -#define ISR_AHBERR (1 << 8) /* bus error */ -#define ISR_RXLOST (1 << 7) /* rx lost */ -#define ISR_RXFIFO (1 << 6) /* rx to fifo */ -#define ISR_TXLOST (1 << 5) /* tx lost */ -#define ISR_TXOK (1 << 4) /* tx to ethernet */ -#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */ -#define ISR_TXFIFO (1 << 2) /* tx to fifo */ -#define ISR_NORXBUF (1 << 1) /* out of rx buffer */ -#define ISR_RXOK (1 << 0) /* rx to buffer */ +#define ISR_PHYSTCHG BIT(9) /* phy status change */ +#define ISR_AHBERR BIT(8) /* bus error */ +#define ISR_RXLOST BIT(7) /* rx lost */ +#define ISR_RXFIFO BIT(6) /* rx to fifo */ +#define ISR_TXLOST BIT(5) /* tx lost */ +#define ISR_TXOK BIT(4) /* tx to ethernet */ +#define ISR_NOTXBUF BIT(3) /* out of tx buffer */ +#define ISR_TXFIFO BIT(2) /* tx to fifo */ +#define ISR_NORXBUF BIT(1) /* out of rx buffer */ +#define ISR_RXOK BIT(0) /* rx to buffer */ /* * MACCR control bits */ -#define MACCR_100M (1 << 18) /* 100Mbps mode */ -#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */ -#define MACCR_RXMCST (1 << 16) /* rx multicast packet */ -#define MACCR_FD (1 << 15) /* full duplex */ -#define MACCR_CRCAPD (1 << 14) /* tx crc append */ -#define MACCR_RXALL (1 << 12) /* rx all packets */ -#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */ -#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */ -#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */ -#define MACCR_RXEN (1 << 8) /* rx enable */ -#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */ -#define MACCR_TXEN (1 << 5) /* tx enable */ -#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */ -#define MACCR_LOOPBACK (1 << 3) /* loop-back */ -#define MACCR_RESET (1 << 2) /* reset */ -#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */ -#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */ +#define MACCR_100M BIT(18) /* 100Mbps mode */ +#define MACCR_RXBCST BIT(17) /* rx broadcast packet */ +#define MACCR_RXMCST BIT(16) /* rx multicast packet */ +#define MACCR_FD BIT(15) /* full duplex */ +#define MACCR_CRCAPD BIT(14) /* tx crc append */ +#define MACCR_RXALL BIT(12) /* rx all packets */ +#define MACCR_RXFTL BIT(11) /* rx packet even it's > 1518 byte */ +#define MACCR_RXRUNT BIT(10) /* rx packet even it's < 64 byte */ +#define MACCR_RXMCSTHT BIT(9) /* rx multicast hash table */ +#define MACCR_RXEN BIT(8) /* rx enable */ +#define MACCR_RXINHDTX BIT(6) /* rx in half duplex tx */ +#define MACCR_TXEN BIT(5) /* tx enable */ +#define MACCR_CRCDIS BIT(4) /* tx packet even it's crc error */ +#define MACCR_LOOPBACK BIT(3) /* loop-back */ +#define MACCR_RESET BIT(2) /* reset */ +#define MACCR_RXDMAEN BIT(1) /* rx dma enable */ +#define MACCR_TXDMAEN BIT(0) /* tx dma enable */ /* * PHYCR control bits */ -#define PHYCR_READ (1 << 26) -#define PHYCR_WRITE (1 << 27) +#define PHYCR_READ BIT(26) +#define PHYCR_WRITE BIT(27) #define PHYCR_REG_SHIFT 21 #define PHYCR_ADDR_SHIFT 16 @@ -82,14 +82,14 @@ struct ftmac110_regs { */ /* Tx Cycle Length */ -#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define ITC_TX_CYCLONG BIT(15) /* 100Mbps=81.92us; 10Mbps=819.2us */ #define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */ /* Tx Threshold: Aggregate n interrupts as 1 interrupt */ #define ITC_TX_THR(n) (((n) & 0x7) << 12) /* Tx Interrupt Timeout = n * Tx Cycle */ #define ITC_TX_ITMO(n) (((n) & 0xf) << 8) /* Rx Cycle Length */ -#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define ITC_RX_CYCLONG BIT(7) /* 100Mbps=81.92us; 10Mbps=819.2us */ #define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */ /* Rx Threshold: Aggregate n interrupts as 1 interrupt */ #define ITC_RX_THR(n) (((n) & 0x7) << 4) @@ -104,12 +104,12 @@ struct ftmac110_regs { */ /* Tx Cycle Length */ -#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define APTC_TX_CYCLONG BIT(12) /* 100Mbps=81.92us; 10Mbps=819.2us */ #define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */ /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */ #define APTC_TX_PTMO(n) (((n) & 0xf) << 8) /* Rx Cycle Length */ -#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */ +#define APTC_RX_CYCLONG BIT(4) /* 100Mbps=81.92us; 10Mbps=819.2us */ #define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */ /* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */ #define APTC_RX_PTMO(n) (((n) & 0xf) << 0) @@ -122,12 +122,12 @@ struct ftmac110_regs { #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */ #define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */ #define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */ -#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */ +#define DBLAC_RXTHR_EN BIT(9) /* enable rx threshold arbitration */ #define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */ #define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */ -#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */ -#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */ -#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */ +#define DBLAC_BURST_CAP16 BIT(2) /* support burst 16 */ +#define DBLAC_BURST_CAP8 BIT(1) /* support burst 8 */ +#define DBLAC_BURST_CAP4 BIT(0) /* support burst 4 */ #define DBLAC_DEFAULT \ (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2)) diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 0c5fdee..4da290f 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -147,7 +147,7 @@ static void __attribute__((unused)) data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, MDIO_DEVAD_NONE, 0); /* speed selection MSB */ - if (!(data & (1 << 6))) + if (!(data & BIT(6))) return; } diff --git a/drivers/net/ks8851_mll.h b/drivers/net/ks8851_mll.h index 7f90ae4..39ead47 100644 --- a/drivers/net/ks8851_mll.h +++ b/drivers/net/ks8851_mll.h @@ -28,13 +28,13 @@ #include #define KS_CCR 0x08 -#define CCR_EEPROM (1 << 9) -#define CCR_SPI (1 << 8) -#define CCR_8BIT (1 << 7) -#define CCR_16BIT (1 << 6) -#define CCR_32BIT (1 << 5) -#define CCR_SHARED (1 << 4) -#define CCR_32PIN (1 << 0) +#define CCR_EEPROM BIT(9) +#define CCR_SPI BIT(8) +#define CCR_8BIT BIT(7) +#define CCR_16BIT BIT(6) +#define CCR_32BIT BIT(5) +#define CCR_SHARED BIT(4) +#define CCR_32PIN BIT(0) /* MAC address registers */ #define KS_MARL 0x10 @@ -42,31 +42,31 @@ #define KS_MARH 0x14 #define KS_OBCR 0x20 -#define OBCR_ODS_16MA (1 << 6) +#define OBCR_ODS_16MA BIT(6) #define KS_EEPCR 0x22 -#define EEPCR_EESA (1 << 4) -#define EEPCR_EESB (1 << 3) -#define EEPCR_EEDO (1 << 2) -#define EEPCR_EESCK (1 << 1) -#define EEPCR_EECS (1 << 0) +#define EEPCR_EESA BIT(4) +#define EEPCR_EESB BIT(3) +#define EEPCR_EEDO BIT(2) +#define EEPCR_EESCK BIT(1) +#define EEPCR_EECS BIT(0) #define KS_MBIR 0x24 -#define MBIR_TXMBF (1 << 12) -#define MBIR_TXMBFA (1 << 11) -#define MBIR_RXMBF (1 << 4) -#define MBIR_RXMBFA (1 << 3) +#define MBIR_TXMBF BIT(12) +#define MBIR_TXMBFA BIT(11) +#define MBIR_RXMBF BIT(4) +#define MBIR_RXMBFA BIT(3) #define KS_GRR 0x26 -#define GRR_QMU (1 << 1) -#define GRR_GSR (1 << 0) +#define GRR_QMU BIT(1) +#define GRR_GSR BIT(0) #define KS_WFCR 0x2A -#define WFCR_MPRXE (1 << 7) -#define WFCR_WF3E (1 << 3) -#define WFCR_WF2E (1 << 2) -#define WFCR_WF1E (1 << 1) -#define WFCR_WF0E (1 << 0) +#define WFCR_MPRXE BIT(7) +#define WFCR_WF3E BIT(3) +#define WFCR_WF2E BIT(2) +#define WFCR_WF1E BIT(1) +#define WFCR_WF0E BIT(0) #define KS_WF0CRC0 0x30 #define KS_WF0CRC1 0x32 @@ -97,39 +97,39 @@ #define KS_WF3BM3 0x6A #define KS_TXCR 0x70 -#define TXCR_TCGICMP (1 << 8) -#define TXCR_TCGUDP (1 << 7) -#define TXCR_TCGTCP (1 << 6) -#define TXCR_TCGIP (1 << 5) -#define TXCR_FTXQ (1 << 4) -#define TXCR_TXFCE (1 << 3) -#define TXCR_TXPE (1 << 2) -#define TXCR_TXCRC (1 << 1) -#define TXCR_TXE (1 << 0) +#define TXCR_TCGICMP BIT(8) +#define TXCR_TCGUDP BIT(7) +#define TXCR_TCGTCP BIT(6) +#define TXCR_TCGIP BIT(5) +#define TXCR_FTXQ BIT(4) +#define TXCR_TXFCE BIT(3) +#define TXCR_TXPE BIT(2) +#define TXCR_TXCRC BIT(1) +#define TXCR_TXE BIT(0) #define KS_TXSR 0x72 -#define TXSR_TXLC (1 << 13) -#define TXSR_TXMC (1 << 12) +#define TXSR_TXLC BIT(13) +#define TXSR_TXMC BIT(12) #define TXSR_TXFID_MASK (0x3f << 0) #define TXSR_TXFID_SHIFT (0) #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) #define KS_RXCR1 0x74 -#define RXCR1_FRXQ (1 << 15) -#define RXCR1_RXUDPFCC (1 << 14) -#define RXCR1_RXTCPFCC (1 << 13) -#define RXCR1_RXIPFCC (1 << 12) -#define RXCR1_RXPAFMA (1 << 11) -#define RXCR1_RXFCE (1 << 10) -#define RXCR1_RXEFE (1 << 9) -#define RXCR1_RXMAFMA (1 << 8) -#define RXCR1_RXBE (1 << 7) -#define RXCR1_RXME (1 << 6) -#define RXCR1_RXUE (1 << 5) -#define RXCR1_RXAE (1 << 4) -#define RXCR1_RXINVF (1 << 1) -#define RXCR1_RXE (1 << 0) +#define RXCR1_FRXQ BIT(15) +#define RXCR1_RXUDPFCC BIT(14) +#define RXCR1_RXTCPFCC BIT(13) +#define RXCR1_RXIPFCC BIT(12) +#define RXCR1_RXPAFMA BIT(11) +#define RXCR1_RXFCE BIT(10) +#define RXCR1_RXEFE BIT(9) +#define RXCR1_RXMAFMA BIT(8) +#define RXCR1_RXBE BIT(7) +#define RXCR1_RXME BIT(6) +#define RXCR1_RXUE BIT(5) +#define RXCR1_RXAE BIT(4) +#define RXCR1_RXINVF BIT(1) +#define RXCR1_RXE BIT(0) #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ RXCR1_RXMAFMA | RXCR1_RXPAFMA) @@ -141,28 +141,28 @@ #define RXCR2_SRDBL_16B (0x2 << 5) #define RXCR2_SRDBL_32B (0x3 << 5) /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ -#define RXCR2_IUFFP (1 << 4) -#define RXCR2_RXIUFCEZ (1 << 3) -#define RXCR2_UDPLFE (1 << 2) -#define RXCR2_RXICMPFCC (1 << 1) -#define RXCR2_RXSAF (1 << 0) +#define RXCR2_IUFFP BIT(4) +#define RXCR2_RXIUFCEZ BIT(3) +#define RXCR2_UDPLFE BIT(2) +#define RXCR2_RXICMPFCC BIT(1) +#define RXCR2_RXSAF BIT(0) #define KS_TXMIR 0x78 #define KS_RXFHSR 0x7C -#define RXFSHR_RXFV (1 << 15) -#define RXFSHR_RXICMPFCS (1 << 13) -#define RXFSHR_RXIPFCS (1 << 12) -#define RXFSHR_RXTCPFCS (1 << 11) -#define RXFSHR_RXUDPFCS (1 << 10) -#define RXFSHR_RXBF (1 << 7) -#define RXFSHR_RXMF (1 << 6) -#define RXFSHR_RXUF (1 << 5) -#define RXFSHR_RXMR (1 << 4) -#define RXFSHR_RXFT (1 << 3) -#define RXFSHR_RXFTL (1 << 2) -#define RXFSHR_RXRF (1 << 1) -#define RXFSHR_RXCE (1 << 0) +#define RXFSHR_RXFV BIT(15) +#define RXFSHR_RXICMPFCS BIT(13) +#define RXFSHR_RXIPFCS BIT(12) +#define RXFSHR_RXTCPFCS BIT(11) +#define RXFSHR_RXUDPFCS BIT(10) +#define RXFSHR_RXBF BIT(7) +#define RXFSHR_RXMF BIT(6) +#define RXFSHR_RXUF BIT(5) +#define RXFSHR_RXMR BIT(4) +#define RXFSHR_RXFT BIT(3) +#define RXFSHR_RXFTL BIT(2) +#define RXFSHR_RXRF BIT(1) +#define RXFSHR_RXCE BIT(0) #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ RXFSHR_RXFTL | RXFSHR_RXMR |\ RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\ @@ -171,49 +171,49 @@ #define RXFHBCR_CNT_MASK 0x0FFF #define KS_TXQCR 0x80 -#define TXQCR_AETFE (1 << 2) -#define TXQCR_TXQMAM (1 << 1) -#define TXQCR_METFE (1 << 0) +#define TXQCR_AETFE BIT(2) +#define TXQCR_TXQMAM BIT(1) +#define TXQCR_METFE BIT(0) #define KS_RXQCR 0x82 -#define RXQCR_RXDTTS (1 << 12) -#define RXQCR_RXDBCTS (1 << 11) -#define RXQCR_RXFCTS (1 << 10) -#define RXQCR_RXIPHTOE (1 << 9) -#define RXQCR_RXDTTE (1 << 7) -#define RXQCR_RXDBCTE (1 << 6) -#define RXQCR_RXFCTE (1 << 5) -#define RXQCR_ADRFE (1 << 4) -#define RXQCR_SDA (1 << 3) -#define RXQCR_RRXEF (1 << 0) +#define RXQCR_RXDTTS BIT(12) +#define RXQCR_RXDBCTS BIT(11) +#define RXQCR_RXFCTS BIT(10) +#define RXQCR_RXIPHTOE BIT(9) +#define RXQCR_RXDTTE BIT(7) +#define RXQCR_RXDBCTE BIT(6) +#define RXQCR_RXFCTE BIT(5) +#define RXQCR_ADRFE BIT(4) +#define RXQCR_SDA BIT(3) +#define RXQCR_RRXEF BIT(0) #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) #define KS_TXFDPR 0x84 -#define TXFDPR_TXFPAI (1 << 14) +#define TXFDPR_TXFPAI BIT(14) #define TXFDPR_TXFP_MASK (0x7ff << 0) #define TXFDPR_TXFP_SHIFT (0) #define KS_RXFDPR 0x86 -#define RXFDPR_RXFPAI (1 << 14) +#define RXFDPR_RXFPAI BIT(14) #define KS_RXDTTR 0x8C #define KS_RXDBCTR 0x8E #define KS_IER 0x90 #define KS_ISR 0x92 -#define IRQ_LCI (1 << 15) -#define IRQ_TXI (1 << 14) -#define IRQ_RXI (1 << 13) -#define IRQ_RXOI (1 << 11) -#define IRQ_TXPSI (1 << 9) -#define IRQ_RXPSI (1 << 8) -#define IRQ_TXSAI (1 << 6) -#define IRQ_RXWFDI (1 << 5) -#define IRQ_RXMPDI (1 << 4) -#define IRQ_LDI (1 << 3) -#define IRQ_EDI (1 << 2) -#define IRQ_SPIBEI (1 << 1) -#define IRQ_DEDI (1 << 0) +#define IRQ_LCI BIT(15) +#define IRQ_TXI BIT(14) +#define IRQ_RXI BIT(13) +#define IRQ_RXOI BIT(11) +#define IRQ_TXPSI BIT(9) +#define IRQ_RXPSI BIT(8) +#define IRQ_TXSAI BIT(6) +#define IRQ_RXWFDI BIT(5) +#define IRQ_RXMPDI BIT(4) +#define IRQ_LDI BIT(3) +#define IRQ_EDI BIT(2) +#define IRQ_SPIBEI BIT(1) +#define IRQ_DEDI BIT(0) #define KS_RXFCTR 0x9C #define RXFCTR_THRESHOLD_MASK 0x00FF @@ -244,7 +244,7 @@ #define KS_CGCR 0xC6 #define KS_IACR 0xC8 -#define IACR_RDEN (1 << 12) +#define IACR_RDEN BIT(12) #define IACR_TSEL_MASK (0x3 << 10) #define IACR_TSEL_SHIFT (10) #define IACR_TSEL_MIB (0x3 << 10) @@ -255,14 +255,14 @@ #define KS_IAHDR 0xD2 #define KS_PMECR 0xD4 -#define PMECR_PME_DELAY (1 << 14) -#define PMECR_PME_POL (1 << 12) -#define PMECR_WOL_WAKEUP (1 << 11) -#define PMECR_WOL_MAGICPKT (1 << 10) -#define PMECR_WOL_LINKUP (1 << 9) -#define PMECR_WOL_ENERGY (1 << 8) -#define PMECR_AUTO_WAKE_EN (1 << 7) -#define PMECR_WAKEUP_NORMAL (1 << 6) +#define PMECR_PME_DELAY BIT(14) +#define PMECR_PME_POL BIT(12) +#define PMECR_WOL_WAKEUP BIT(11) +#define PMECR_WOL_MAGICPKT BIT(10) +#define PMECR_WOL_LINKUP BIT(9) +#define PMECR_WOL_ENERGY BIT(8) +#define PMECR_AUTO_WAKE_EN BIT(7) +#define PMECR_WAKEUP_NORMAL BIT(6) #define PMECR_WKEVT_MASK (0xf << 2) #define PMECR_WKEVT_SHIFT (2) #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) @@ -279,12 +279,12 @@ /* Standard MII PHY data */ #define KS_P1MBCR 0xE4 -#define P1MBCR_FORCE_FDX (1 << 8) +#define P1MBCR_FORCE_FDX BIT(8) #define KS_P1MBSR 0xE6 -#define P1MBSR_AN_COMPLETE (1 << 5) -#define P1MBSR_AN_CAPABLE (1 << 3) -#define P1MBSR_LINK_UP (1 << 2) +#define P1MBSR_AN_COMPLETE BIT(5) +#define P1MBSR_AN_CAPABLE BIT(3) +#define P1MBSR_LINK_UP BIT(2) #define KS_PHY1ILR 0xE8 #define KS_PHY1IHR 0xEA @@ -292,52 +292,52 @@ #define KS_P1ANLPR 0xEE #define KS_P1SCLMD 0xF4 -#define P1SCLMD_LEDOFF (1 << 15) -#define P1SCLMD_TXIDS (1 << 14) -#define P1SCLMD_RESTARTAN (1 << 13) -#define P1SCLMD_DISAUTOMDIX (1 << 10) -#define P1SCLMD_FORCEMDIX (1 << 9) -#define P1SCLMD_AUTONEGEN (1 << 7) -#define P1SCLMD_FORCE100 (1 << 6) -#define P1SCLMD_FORCEFDX (1 << 5) -#define P1SCLMD_ADV_FLOW (1 << 4) -#define P1SCLMD_ADV_100BT_FDX (1 << 3) -#define P1SCLMD_ADV_100BT_HDX (1 << 2) -#define P1SCLMD_ADV_10BT_FDX (1 << 1) -#define P1SCLMD_ADV_10BT_HDX (1 << 0) +#define P1SCLMD_LEDOFF BIT(15) +#define P1SCLMD_TXIDS BIT(14) +#define P1SCLMD_RESTARTAN BIT(13) +#define P1SCLMD_DISAUTOMDIX BIT(10) +#define P1SCLMD_FORCEMDIX BIT(9) +#define P1SCLMD_AUTONEGEN BIT(7) +#define P1SCLMD_FORCE100 BIT(6) +#define P1SCLMD_FORCEFDX BIT(5) +#define P1SCLMD_ADV_FLOW BIT(4) +#define P1SCLMD_ADV_100BT_FDX BIT(3) +#define P1SCLMD_ADV_100BT_HDX BIT(2) +#define P1SCLMD_ADV_10BT_FDX BIT(1) +#define P1SCLMD_ADV_10BT_HDX BIT(0) #define KS_P1CR 0xF6 -#define P1CR_HP_MDIX (1 << 15) -#define P1CR_REV_POL (1 << 13) -#define P1CR_OP_100M (1 << 10) -#define P1CR_OP_FDX (1 << 9) -#define P1CR_OP_MDI (1 << 7) -#define P1CR_AN_DONE (1 << 6) -#define P1CR_LINK_GOOD (1 << 5) -#define P1CR_PNTR_FLOW (1 << 4) -#define P1CR_PNTR_100BT_FDX (1 << 3) -#define P1CR_PNTR_100BT_HDX (1 << 2) -#define P1CR_PNTR_10BT_FDX (1 << 1) -#define P1CR_PNTR_10BT_HDX (1 << 0) +#define P1CR_HP_MDIX BIT(15) +#define P1CR_REV_POL BIT(13) +#define P1CR_OP_100M BIT(10) +#define P1CR_OP_FDX BIT(9) +#define P1CR_OP_MDI BIT(7) +#define P1CR_AN_DONE BIT(6) +#define P1CR_LINK_GOOD BIT(5) +#define P1CR_PNTR_FLOW BIT(4) +#define P1CR_PNTR_100BT_FDX BIT(3) +#define P1CR_PNTR_100BT_HDX BIT(2) +#define P1CR_PNTR_10BT_FDX BIT(1) +#define P1CR_PNTR_10BT_HDX BIT(0) /* TX Frame control */ -#define TXFR_TXIC (1 << 15) +#define TXFR_TXIC BIT(15) #define TXFR_TXFID_MASK (0x3f << 0) #define TXFR_TXFID_SHIFT (0) #define KS_P1SR 0xF8 -#define P1SR_HP_MDIX (1 << 15) -#define P1SR_REV_POL (1 << 13) -#define P1SR_OP_100M (1 << 10) -#define P1SR_OP_FDX (1 << 9) -#define P1SR_OP_MDI (1 << 7) -#define P1SR_AN_DONE (1 << 6) -#define P1SR_LINK_GOOD (1 << 5) -#define P1SR_PNTR_FLOW (1 << 4) -#define P1SR_PNTR_100BT_FDX (1 << 3) -#define P1SR_PNTR_100BT_HDX (1 << 2) -#define P1SR_PNTR_10BT_FDX (1 << 1) -#define P1SR_PNTR_10BT_HDX (1 << 0) +#define P1SR_HP_MDIX BIT(15) +#define P1SR_REV_POL BIT(13) +#define P1SR_OP_100M BIT(10) +#define P1SR_OP_FDX BIT(9) +#define P1SR_OP_MDI BIT(7) +#define P1SR_AN_DONE BIT(6) +#define P1SR_LINK_GOOD BIT(5) +#define P1SR_PNTR_FLOW BIT(4) +#define P1SR_PNTR_100BT_FDX BIT(3) +#define P1SR_PNTR_100BT_HDX BIT(2) +#define P1SR_PNTR_10BT_FDX BIT(1) +#define P1SR_PNTR_10BT_HDX BIT(0) #define ENUM_BUS_NONE 0 #define ENUM_BUS_8BIT 1 diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index 27a3f41..3319b7e 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -76,7 +76,7 @@ MVGBE_ADV_NO_FLOW_CTRL | \ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ + BIT(9) /* Reserved bit has to be 1 */ | \ MVGBE_DO_NOT_FORCE_LINK_FAIL | \ MVGBE_EN_AUTO_NEG_SPEED_GMII | \ MVGBE_DTE_ADV_0 | \ @@ -105,23 +105,23 @@ #define MVGBE_INTERFACE_GMII_MII 0 #define MVGBE_INTERFACE_PCM 1 #define MVGBE_LINK_IS_DOWN 0 -#define MVGBE_LINK_IS_UP (1 << 1) +#define MVGBE_LINK_IS_UP BIT(1) #define MVGBE_PORT_AT_HALF_DUPLEX 0 -#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2) +#define MVGBE_PORT_AT_FULL_DUPLEX BIT(2) #define MVGBE_RX_FLOW_CTRL_DISD 0 -#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3) +#define MVGBE_RX_FLOW_CTRL_ENBALED BIT(3) #define MVGBE_GMII_SPEED_100_10 0 -#define MVGBE_GMII_SPEED_1000 (1 << 4) +#define MVGBE_GMII_SPEED_1000 BIT(4) #define MVGBE_MII_SPEED_10 0 -#define MVGBE_MII_SPEED_100 (1 << 5) +#define MVGBE_MII_SPEED_100 BIT(5) #define MVGBE_NO_TX 0 -#define MVGBE_TX_IN_PROGRESS (1 << 7) +#define MVGBE_TX_IN_PROGRESS BIT(7) #define MVGBE_BYPASS_NO_ACTIVE 0 -#define MVGBE_BYPASS_ACTIVE (1 << 8) +#define MVGBE_BYPASS_ACTIVE BIT(8) #define MVGBE_PORT_NOT_AT_PARTN_STT 0 -#define MVGBE_PORT_AT_PARTN_STT (1 << 9) +#define MVGBE_PORT_AT_PARTN_STT BIT(9) #define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0 -#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10) +#define MVGBE_PORT_TX_FIFO_EMPTY BIT(10) /* These macros describes the Port configuration reg (Px_cR) bits */ #define MVGBE_UCAST_MOD_NRML 0 @@ -129,91 +129,91 @@ #define MVGBE_DFLT_RXQ(_x) (_x << 1) #define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4) #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0 -#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) +#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP BIT(7) #define MVGBE_RX_BC_IF_IP 0 -#define MVGBE_REJECT_BC_IF_IP (1 << 8) +#define MVGBE_REJECT_BC_IF_IP BIT(8) #define MVGBE_RX_BC_IF_ARP 0 -#define MVGBE_REJECT_BC_IF_ARP (1 << 9) -#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) +#define MVGBE_REJECT_BC_IF_ARP BIT(9) +#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY BIT(12) #define MVGBE_CPTR_TCP_FRMS_DIS 0 -#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14) +#define MVGBE_CPTR_TCP_FRMS_EN BIT(14) #define MVGBE_CPTR_UDP_FRMS_DIS 0 -#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15) +#define MVGBE_CPTR_UDP_FRMS_EN BIT(15) #define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16) #define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19) #define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22) -#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) +#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE BIT(25) /* These macros describes the Port configuration extend reg (Px_cXR) bits*/ #define MVGBE_CLASSIFY_EN 1 #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) +#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 BIT(1) #define MVGBE_PARTITION_DIS 0 -#define MVGBE_PARTITION_EN (1 << 2) +#define MVGBE_PARTITION_EN BIT(2) #define MVGBE_TX_CRC_GENERATION_EN 0 -#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3) +#define MVGBE_TX_CRC_GENERATION_DIS BIT(3) /* These macros describes the Port Sdma configuration reg (SDCR) bits */ #define MVGBE_RIFB 1 #define MVGBE_RX_BURST_SIZE_1_64BIT 0 -#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1) -#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2) -#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) -#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3) -#define MVGBE_BLM_RX_NO_SWAP (1 << 4) +#define MVGBE_RX_BURST_SIZE_2_64BIT BIT(1) +#define MVGBE_RX_BURST_SIZE_4_64BIT BIT(2) +#define MVGBE_RX_BURST_SIZE_8_64BIT (BIT(2) | BIT(1)) +#define MVGBE_RX_BURST_SIZE_16_64BIT BIT(3) +#define MVGBE_BLM_RX_NO_SWAP BIT(4) #define MVGBE_BLM_RX_BYTE_SWAP 0 -#define MVGBE_BLM_TX_NO_SWAP (1 << 5) +#define MVGBE_BLM_TX_NO_SWAP BIT(5) #define MVGBE_BLM_TX_BYTE_SWAP 0 -#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) +#define MVGBE_DESCRIPTORS_BYTE_SWAP BIT(6) #define MVGBE_DESCRIPTORS_NO_SWAP 0 #define MVGBE_TX_BURST_SIZE_1_64BIT 0 -#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22) -#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23) -#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) -#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24) +#define MVGBE_TX_BURST_SIZE_2_64BIT BIT(22) +#define MVGBE_TX_BURST_SIZE_4_64BIT BIT(23) +#define MVGBE_TX_BURST_SIZE_8_64BIT (BIT(23) | BIT(22)) +#define MVGBE_TX_BURST_SIZE_16_64BIT BIT(24) /* These macros describes the Port serial control reg (PSCR) bits */ #define MVGBE_SERIAL_PORT_DIS 0 #define MVGBE_SERIAL_PORT_EN 1 -#define MVGBE_FORCE_LINK_PASS (1 << 1) +#define MVGBE_FORCE_LINK_PASS BIT(1) #define MVGBE_DO_NOT_FORCE_LINK_PASS 0 #define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0 -#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) +#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX BIT(2) #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 -#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) +#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL BIT(3) #define MVGBE_ADV_NO_FLOW_CTRL 0 -#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) +#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL BIT(4) #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) +#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS BIT(5) #define MVGBE_FORCE_BP_MODE_NO_JAM 0 -#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7) -#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) +#define MVGBE_FORCE_BP_MODE_JAM_TX BIT(7) +#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT(8) #define MVGBE_FORCE_LINK_FAIL 0 -#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) -#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) +#define MVGBE_DO_NOT_FORCE_LINK_FAIL BIT(10) +#define MVGBE_DIS_AUTO_NEG_SPEED_GMII BIT(13) #define MVGBE_EN_AUTO_NEG_SPEED_GMII 0 #define MVGBE_DTE_ADV_0 0 -#define MVGBE_DTE_ADV_1 (1 << 14) +#define MVGBE_DTE_ADV_1 BIT(14) #define MVGBE_MIIPHY_MAC_MODE 0 -#define MVGBE_MIIPHY_PHY_MODE (1 << 15) +#define MVGBE_MIIPHY_PHY_MODE BIT(15) #define MVGBE_AUTO_NEG_NO_CHANGE 0 -#define MVGBE_RESTART_AUTO_NEG (1 << 16) +#define MVGBE_RESTART_AUTO_NEG BIT(16) #define MVGBE_MAX_RX_PACKET_1518BYTE 0 -#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17) -#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18) -#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) -#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19) -#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) -#define MVGBE_SET_EXT_LOOPBACK (1 << 20) +#define MVGBE_MAX_RX_PACKET_1522BYTE BIT(17) +#define MVGBE_MAX_RX_PACKET_1552BYTE BIT(18) +#define MVGBE_MAX_RX_PACKET_9022BYTE (BIT(18) | BIT(17)) +#define MVGBE_MAX_RX_PACKET_9192BYTE BIT(19) +#define MVGBE_MAX_RX_PACKET_9700BYTE (BIT(19) | BIT(17)) +#define MVGBE_SET_EXT_LOOPBACK BIT(20) #define MVGBE_CLR_EXT_LOOPBACK 0 -#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21) +#define MVGBE_SET_FULL_DUPLEX_MODE BIT(21) #define MVGBE_SET_HALF_DUPLEX_MODE 0 -#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) +#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT(22) #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 #define MVGBE_SET_GMII_SPEED_TO_10_100 0 -#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23) +#define MVGBE_SET_GMII_SPEED_TO_1000 BIT(23) #define MVGBE_SET_MII_SPEED_TO_10 0 -#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24) +#define MVGBE_SET_MII_SPEED_TO_100 BIT(24) /* SMI register fields */ #define MVGBE_PHY_SMI_TIMEOUT 10000 @@ -229,56 +229,56 @@ #define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS) #define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS) #define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS) -#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ -#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ +#define MVGBE_PHY_SMI_READ_VALID_MASK BIT(27) /* Read Valid */ +#define MVGBE_PHY_SMI_BUSY_MASK BIT(28) /* Busy */ /* SDMA command status fields macros */ /* Tx & Rx descriptors status */ #define MVGBE_ERROR_SUMMARY 1 /* Tx & Rx descriptors command */ -#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) +#define MVGBE_BUFFER_OWNED_BY_DMA BIT(31) /* Tx descriptors status */ #define MVGBE_LC_ERROR 0 -#define MVGBE_UR_ERROR (1 << 1) -#define MVGBE_RL_ERROR (1 << 2) -#define MVGBE_LLC_SNAP_FORMAT (1 << 9) -#define MVGBE_TX_LAST_FRAME (1 << 20) +#define MVGBE_UR_ERROR BIT(1) +#define MVGBE_RL_ERROR BIT(2) +#define MVGBE_LLC_SNAP_FORMAT BIT(9) +#define MVGBE_TX_LAST_FRAME BIT(20) /* Rx descriptors status */ #define MVGBE_CRC_ERROR 0 -#define MVGBE_OVERRUN_ERROR (1 << 1) -#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) -#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) -#define MVGBE_VLAN_TAGGED (1 << 19) -#define MVGBE_BPDU_FRAME (1 << 20) +#define MVGBE_OVERRUN_ERROR BIT(1) +#define MVGBE_MAX_FRAME_LENGTH_ERROR BIT(2) +#define MVGBE_RESOURCE_ERROR (BIT(2) | BIT(1)) +#define MVGBE_VLAN_TAGGED BIT(19) +#define MVGBE_BPDU_FRAME BIT(20) #define MVGBE_TCP_FRAME_OVER_IP_V_4 0 -#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) -#define MVGBE_OTHER_FRAME_TYPE (1 << 22) -#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23) -#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24) -#define MVGBE_FRAME_HEADER_OK (1 << 25) -#define MVGBE_RX_LAST_DESC (1 << 26) -#define MVGBE_RX_FIRST_DESC (1 << 27) -#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) -#define MVGBE_RX_EN_INTERRUPT (1 << 29) -#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30) +#define MVGBE_UDP_FRAME_OVER_IP_V_4 BIT(21) +#define MVGBE_OTHER_FRAME_TYPE BIT(22) +#define MVGBE_LAYER_2_IS_MVGBE_V_2 BIT(23) +#define MVGBE_FRAME_TYPE_IP_V_4 BIT(24) +#define MVGBE_FRAME_HEADER_OK BIT(25) +#define MVGBE_RX_LAST_DESC BIT(26) +#define MVGBE_RX_FIRST_DESC BIT(27) +#define MVGBE_UNKNOWN_DESTINATION_ADDR BIT(28) +#define MVGBE_RX_EN_INTERRUPT BIT(29) +#define MVGBE_LAYER_4_CHECKSUM_OK BIT(30) /* Rx descriptors byte count */ -#define MVGBE_FRAME_FRAGMENTED (1 << 2) +#define MVGBE_FRAME_FRAGMENTED BIT(2) /* Tx descriptors command */ -#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) -#define MVGBE_FRAME_SET_TO_VLAN (1 << 15) +#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC BIT(10) +#define MVGBE_FRAME_SET_TO_VLAN BIT(15) #define MVGBE_TCP_FRAME 0 -#define MVGBE_UDP_FRAME (1 << 16) -#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) -#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18) -#define MVGBE_ZERO_PADDING (1 << 19) -#define MVGBE_TX_LAST_DESC (1 << 20) -#define MVGBE_TX_FIRST_DESC (1 << 21) -#define MVGBE_GEN_CRC (1 << 22) -#define MVGBE_TX_EN_INTERRUPT (1 << 23) -#define MVGBE_AUTO_MODE (1 << 30) +#define MVGBE_UDP_FRAME BIT(16) +#define MVGBE_GEN_TCP_UDP_CHECKSUM BIT(17) +#define MVGBE_GEN_IP_V_4_CHECKSUM BIT(18) +#define MVGBE_ZERO_PADDING BIT(19) +#define MVGBE_TX_LAST_DESC BIT(20) +#define MVGBE_TX_FIRST_DESC BIT(21) +#define MVGBE_GEN_CRC BIT(22) +#define MVGBE_TX_EN_INTERRUPT BIT(23) +#define MVGBE_AUTO_MODE BIT(30) /* Address decode parameters */ /* Ethernet Base Address Register bits */ @@ -331,7 +331,7 @@ /* Window access control */ #define EWIN_ACCESS_NOT_ALLOWED 0 #define EWIN_ACCESS_READ_ONLY 1 -#define EWIN_ACCESS_FULL ((1 << 1) | 1) +#define EWIN_ACCESS_FULL (BIT(1) | 1) /* structures represents Controller registers */ struct mvgbe_barsz { diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index efaae16..484d64c 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -80,8 +80,8 @@ #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) -#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ -#define MVNETA_SMI_BUSY (1 << 28) /* Busy */ +#define MVNETA_SMI_READ_VALID BIT(27) /* Read Valid */ +#define MVNETA_SMI_BUSY BIT(28) /* Busy */ #define MVNETA_MBUS_RETRY 0x2010 #define MVNETA_UNIT_INTR_CAUSE 0x2080 #define MVNETA_UNIT_CONTROL 0x20B0 @@ -396,7 +396,7 @@ static struct buffer_location buffer_loc; * Page table entries are set to 1MB, or multiples of 1MB * (not < 1MB). driver uses less bd's so use 1MB bdspace. */ -#define BD_SPACE (1 << 20) +#define BD_SPACE BIT(20) /* Utility/helper methods */ diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 49f444a..5ce8b5c 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -111,10 +111,10 @@ static struct phy_driver KS8721_driver = { */ #define MII_KSZ90xx_PHY_CTL 0x1f -#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6) -#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5) -#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4) -#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3) +#define MIIM_KSZ90xx_PHYCTL_1000 BIT(6) +#define MIIM_KSZ90xx_PHYCTL_100 BIT(5) +#define MIIM_KSZ90xx_PHYCTL_10 BIT(4) +#define MIIM_KSZ90xx_PHYCTL_DUPLEX BIT(3) static int ksz90xx_startup(struct phy_device *phydev) { @@ -146,9 +146,9 @@ static int ksz90xx_startup(struct phy_device *phydev) #define MII_KSZ9021_EXTENDED_DATAW 0x0c #define MII_KSZ9021_EXTENDED_DATAR 0x0d -#define CTRL1000_PREFER_MASTER (1 << 10) -#define CTRL1000_CONFIG_MASTER (1 << 11) -#define CTRL1000_MANUAL_CONFIG (1 << 12) +#define CTRL1000_PREFER_MASTER BIT(10) +#define CTRL1000_CONFIG_MASTER BIT(11) +#define CTRL1000_MANUAL_CONFIG BIT(12) int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) { diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 302abe8..4cd57c5 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -40,7 +40,7 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr) printf("SMI busy timeout\n"); return -1; } - } while (reg & (1 << 15)); + } while (reg & BIT(15)); return 0; } @@ -59,7 +59,7 @@ static void mv88e61xx_switch_write(char *name, u32 phy_adr, miiphy_write(name, mii_dev_addr, 0x1, data); /* Write command to Switch indirect command register (write) */ miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << + reg_ofs | (phy_adr << 5) | BIT(10) | BIT(12) | (1 << 15)); } @@ -76,7 +76,7 @@ static void mv88e61xx_switch_read(char *name, u32 phy_adr, mv88e61xx_busychk_multic(name, mii_dev_addr); /* Write command to Switch indirect command register (read) */ miiphy_write(name, mii_dev_addr, 0x0, - reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << + reg_ofs | (phy_adr << 5) | BIT(11) | BIT(12) | (1 << 15)); mv88e61xx_busychk_multic(name, mii_dev_addr); /* Read data from Switch indirect data register */ @@ -331,8 +331,8 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) return -1; } - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { - swconfig->cpuport = (1 << 5); + if (!(swconfig->cpuport & (BIT(4) | BIT(5)))) { + swconfig->cpuport = BIT(5); printf("Invalid cpu port config, using default port5\n"); } diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 20a6746..c65199e 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -172,7 +172,7 @@ static int vsc8574_config(struct phy_device *phydev) val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { /* set bit 15:14 to '01' for QSGMII mode */ - val = (val & 0x3fff) | (1 << 14); + val = (val & 0x3fff) | BIT(14); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); /* Enable 4 ports MAC QSGMII */ @@ -217,7 +217,7 @@ static int vsc8514_config(struct phy_device *phydev) val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { /* set bit 15:14 to '01' for QSGMII mode */ - val = (val & 0x3fff) | (1 << 14); + val = (val & 0x3fff) | BIT(14); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19, val); /* Enable 4 ports MAC QSGMII */ @@ -267,19 +267,19 @@ static int vsc8664_config(struct phy_device *phydev) /* Enable MAC interface auto-negotiation */ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); - val |= (1 << 13); + val |= BIT(13); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, PHY_EXT_PAGE_ACCESS_EXTENDED); val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); - val |= (1 << 11); + val |= BIT(11); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); /* Enable LED blink */ val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); - val &= ~(1 << 2); + val &= ~BIT(2); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); genphy_config_aneg(phydev); diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 7b31f8c..1583850 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -264,7 +264,7 @@ static void emac_setup(struct eth_device *dev) /* Set MAC CTL1 */ emac_phy_read(dev->name, 1, 0, &phy_val); debug("PHY SETUP, reg 0 value: %x\n", phy_val); - duplex_flag = !!(phy_val & (1 << 8)); + duplex_flag = !!(phy_val & BIT(8)); reg_val = 0; if (duplex_flag) diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index 9da59a0..d0ac37e 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -280,33 +280,33 @@ printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) /* * PHY Register bit masks. */ -#define PHY_CTRL_RESET (1 << 15) -#define PHY_CTRL_LOOPBACK (1 << 14) -#define PHY_CTRL_SPEED0 (1 << 13) -#define PHY_CTRL_AN_EN (1 << 12) -#define PHY_CTRL_PWR_DN (1 << 11) -#define PHY_CTRL_ISOLATE (1 << 10) -#define PHY_CTRL_RESTART_AN (1 << 9) -#define PHY_CTRL_FULL_DUPLEX (1 << 8) -#define PHY_CTRL_CT_EN (1 << 7) -#define PHY_CTRL_SPEED1 (1 << 6) - -#define PHY_STAT_100BASE_T4 (1 << 15) -#define PHY_STAT_100BASE_X_FD (1 << 14) -#define PHY_STAT_100BASE_X_HD (1 << 13) -#define PHY_STAT_10BASE_T_FD (1 << 12) -#define PHY_STAT_10BASE_T_HD (1 << 11) -#define PHY_STAT_100BASE_T2_FD (1 << 10) -#define PHY_STAT_100BASE_T2_HD (1 << 9) -#define PHY_STAT_EXT_STAT (1 << 8) -#define PHY_STAT_RESERVED (1 << 7) -#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ -#define PHY_STAT_AN_COMPLETE (1 << 5) -#define PHY_STAT_REM_FAULT (1 << 4) -#define PHY_STAT_AN_CAP (1 << 3) -#define PHY_STAT_LINK_UP (1 << 2) -#define PHY_STAT_JABBER (1 << 1) -#define PHY_STAT_EXT_CAP (1 << 0) +#define PHY_CTRL_RESET BIT(15) +#define PHY_CTRL_LOOPBACK BIT(14) +#define PHY_CTRL_SPEED0 BIT(13) +#define PHY_CTRL_AN_EN BIT(12) +#define PHY_CTRL_PWR_DN BIT(11) +#define PHY_CTRL_ISOLATE BIT(10) +#define PHY_CTRL_RESTART_AN BIT(9) +#define PHY_CTRL_FULL_DUPLEX BIT(8) +#define PHY_CTRL_CT_EN BIT(7) +#define PHY_CTRL_SPEED1 BIT(6) + +#define PHY_STAT_100BASE_T4 BIT(15) +#define PHY_STAT_100BASE_X_FD BIT(14) +#define PHY_STAT_100BASE_X_HD BIT(13) +#define PHY_STAT_10BASE_T_FD BIT(12) +#define PHY_STAT_10BASE_T_HD BIT(11) +#define PHY_STAT_100BASE_T2_FD BIT(10) +#define PHY_STAT_100BASE_T2_HD BIT(9) +#define PHY_STAT_EXT_STAT BIT(8) +#define PHY_STAT_RESERVED BIT(7) +#define PHY_STAT_MFPS BIT(6) /* Management Frames Preamble Suppression */ +#define PHY_STAT_AN_COMPLETE BIT(5) +#define PHY_STAT_REM_FAULT BIT(4) +#define PHY_STAT_AN_CAP BIT(3) +#define PHY_STAT_LINK_UP BIT(2) +#define PHY_STAT_JABBER BIT(1) +#define PHY_STAT_EXT_CAP BIT(0) #define TBI_CONTROL_2 0x11 #define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 @@ -330,17 +330,17 @@ printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ #define SPEC_STAT_SPEED_MASK (3 << 14) -#define SPEC_STAT_FULL_DUP (1 << 13) -#define SPEC_STAT_PAGE_RCVD (1 << 12) -#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ -#define SPEC_STAT_LINK_UP (1 << 10) +#define SPEC_STAT_FULL_DUP BIT(13) +#define SPEC_STAT_PAGE_RCVD BIT(12) +#define SPEC_STAT_RESOLVED BIT(11) /* Speed and Duplex Resolved */ +#define SPEC_STAT_LINK_UP BIT(10) #define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ -#define SPEC_STAT_MDIX (1 << 6) -#define SPEC_STAT_POLARITY (1 << 1) -#define SPEC_STAT_JABBER (1 << 0) +#define SPEC_STAT_MDIX BIT(6) +#define SPEC_STAT_POLARITY BIT(1) +#define SPEC_STAT_JABBER BIT(0) #define SPEED_1000 (2 << 14) -#define SPEED_100 (1 << 14) +#define SPEED_100 BIT(14) #define SPEED_10 (0 << 14) #define TBI_ADDR 0x1E /* Ten Bit Interface address */ @@ -374,7 +374,7 @@ struct dma_descriptor { }; /* last next descriptor address flag */ -#define DMA_DESCR_LAST (1 << 31) +#define DMA_DESCR_LAST BIT(31) /* TX DMA descriptor config status bits */ #define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ @@ -383,14 +383,14 @@ struct dma_descriptor { #define DMA_DESCR_TX_HUGE (1 << 3) #define DMA_DESCR_TX_PAD (1 << 4) #define DMA_DESCR_TX_CRC (1 << 5) -#define DMA_DESCR_TX_DESCR_INT (1 << 14) +#define DMA_DESCR_TX_DESCR_INT BIT(14) #define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 -#define DMA_DESCR_TX_ONE_COLLISION (1 << 20) -#define DMA_DESCR_TX_LATE_COLLISION (1 << 24) -#define DMA_DESCR_TX_UNDERRUN (1 << 25) -#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) -#define DMA_DESCR_TX_OK (1 << 30) -#define DMA_DESCR_TX_OWNER (1 << 31) +#define DMA_DESCR_TX_ONE_COLLISION BIT(20) +#define DMA_DESCR_TX_LATE_COLLISION BIT(24) +#define DMA_DESCR_TX_UNDERRUN BIT(25) +#define DMA_DESCR_TX_RETRY_LIMIT BIT(26) +#define DMA_DESCR_TX_OK BIT(30) +#define DMA_DESCR_TX_OWNER BIT(31) /* RX DMA descriptor status bits */ #define DMA_DESCR_RX_EOF (1 << 0) @@ -401,10 +401,10 @@ struct dma_descriptor { #define DMA_DESCR_RX_HASH_MATCH (1 << 7) #define DMA_DESCR_RX_BAD_FRAME (1 << 8) #define DMA_DESCR_RX_OVERRUN (1 << 9) -#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) -#define DMA_DESCR_RX_CRC_ERROR (1 << 12) -#define DMA_DESCR_RX_DESCR_INT (1 << 13) -#define DMA_DESCR_RX_OWNER (1 << 15) +#define DMA_DESCR_RX_MAX_FRAME_LEN BIT(11) +#define DMA_DESCR_RX_CRC_ERROR BIT(12) +#define DMA_DESCR_RX_DESCR_INT BIT(13) +#define DMA_DESCR_RX_OWNER BIT(15) #define RX_BUFFER_SIZE PKTSIZE #define NUM_RX_DESC PKTBUFSRX diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index fed7358..578d07c 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -326,9 +326,9 @@ static void vsc9953_port_status_set(int port_nr, u8 enabled) val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]); if (enabled == 1) - val |= (1 << 13); + val |= BIT(13); else - val &= ~(1 << 13); + val &= ~BIT(13); out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val); } diff --git a/drivers/net/xilinx_ll_temac.h b/drivers/net/xilinx_ll_temac.h index 56362ba..67c7949 100644 --- a/drivers/net/xilinx_ll_temac.h +++ b/drivers/net/xilinx_ll_temac.h @@ -64,9 +64,9 @@ struct temac_reg { }; /* Reset and Address Filter Registers (raf), [1] p25 */ -#define RAF_SR (1 << 13) -#define RAF_EMFE (1 << 12) -#define RAF_NFE (1 << 11) +#define RAF_SR BIT(13) +#define RAF_EMFE BIT(12) +#define RAF_NFE BIT(11) #define RAF_RVSTM_POS 9 #define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS) #define RAF_TVSTM_POS 7 @@ -75,9 +75,9 @@ struct temac_reg { #define RAF_RVTM_MASK (3 << RAF_RVTM_POS) #define RAF_TVTM_POS 3 #define RAF_TVTM_MASK (3 << RAF_TVTM_POS) -#define RAF_BCREJ (1 << 2) -#define RAF_MCREJ (1 << 1) -#define RAF_HTRST (1 << 0) +#define RAF_BCREJ BIT(2) +#define RAF_MCREJ BIT(1) +#define RAF_HTRST BIT(0) /* Transmit Pause Frame Registers (tpf), [1] p28 */ #define TPF_TPFV_POS 0 @@ -88,21 +88,21 @@ struct temac_reg { #define IFGP_MASK (0xFF << IFGP_POS) /* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */ -#define ISPE_MR (1 << 7) -#define ISPE_RDL (1 << 6) -#define ISPE_TC (1 << 5) -#define ISPE_RFO (1 << 4) -#define ISPE_RR (1 << 3) -#define ISPE_RC (1 << 2) -#define ISPE_AN (1 << 1) -#define ISPE_HAC (1 << 0) +#define ISPE_MR BIT(7) +#define ISPE_RDL BIT(6) +#define ISPE_TC BIT(5) +#define ISPE_RFO BIT(4) +#define ISPE_RR BIT(3) +#define ISPE_RC BIT(2) +#define ISPE_AN BIT(1) +#define ISPE_HAC BIT(0) /* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */ #define TRTAG_TPID_POS 16 #define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS) #define TRTAG_PRIO_POS 13 #define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS) -#define TRTAG_CFI (1 << 12) +#define TRTAG_CFI BIT(12) #define TRTAG_VID_POS 0 #define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS) @@ -121,19 +121,19 @@ struct temac_reg { #define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS) /* Control Register (ctl), [1] p47 */ -#define CTL_WEN (1 << 15) +#define CTL_WEN BIT(15) #define CTL_ADDR_POS 0 #define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS) /* Ready Status Register Ethernet (rdy), [1] p48 */ -#define RSE_HACS_RDY (1 << 14) -#define RSE_CFG_WR (1 << 6) -#define RSE_CFG_RR (1 << 5) -#define RSE_AF_WR (1 << 4) -#define RSE_AF_RR (1 << 3) -#define RSE_MIIM_WR (1 << 2) -#define RSE_MIIM_RR (1 << 1) -#define RSE_FABR_RR (1 << 0) +#define RSE_HACS_RDY BIT(14) +#define RSE_CFG_WR BIT(6) +#define RSE_CFG_RR BIT(5) +#define RSE_AF_WR BIT(4) +#define RSE_AF_RR BIT(3) +#define RSE_MIIM_WR BIT(2) +#define RSE_MIIM_RR BIT(1) +#define RSE_FABR_RR BIT(0) /* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */ #define UAWL_UADDR_POS 0 @@ -181,28 +181,28 @@ enum temac_ctrl { /* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */ #define RCW0_PADDR_POS 0 #define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS) -#define RCW1_RST (1 << 31) -#define RCW1_JUM (1 << 30) -#define RCW1_FCS (1 << 29) -#define RCW1_RX (1 << 28) -#define RCW1_VLAN (1 << 27) -#define RCW1_HD (1 << 26) -#define RCW1_LT_DIS (1 << 25) +#define RCW1_RST BIT(31) +#define RCW1_JUM BIT(30) +#define RCW1_FCS BIT(29) +#define RCW1_RX BIT(28) +#define RCW1_VLAN BIT(27) +#define RCW1_HD BIT(26) +#define RCW1_LT_DIS BIT(25) #define RCW1_PADDR_POS 0 #define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS) /* Transmit Configuration Registers (TC), [1] p52 */ -#define TC_RST (1 << 31) -#define TC_JUM (1 << 30) -#define TC_FCS (1 << 29) -#define TC_TX (1 << 28) -#define TC_VLAN (1 << 27) -#define TC_HD (1 << 26) -#define TC_IFG (1 << 25) +#define TC_RST BIT(31) +#define TC_JUM BIT(30) +#define TC_FCS BIT(29) +#define TC_TX BIT(28) +#define TC_VLAN BIT(27) +#define TC_HD BIT(26) +#define TC_IFG BIT(25) /* Flow Control Configuration Registers (FCC), [1] p54 */ -#define FCC_FCTX (1 << 30) -#define FCC_FCRX (1 << 29) +#define FCC_FCTX BIT(30) +#define FCC_FCRX BIT(29) /* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */ #define EMMC_LSPD_POS 30 @@ -210,12 +210,12 @@ enum temac_ctrl { #define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS) #define EMMC_LSPD_100 (1 << EMMC_LSPD_POS) #define EMMC_LSPD_10 0 -#define EMMC_RGMII (1 << 29) -#define EMMC_SGMII (1 << 28) -#define EMMC_GPCS (1 << 27) -#define EMMC_HOST (1 << 26) -#define EMMC_TX16 (1 << 25) -#define EMMC_RX16 (1 << 24) +#define EMMC_RGMII BIT(29) +#define EMMC_SGMII BIT(28) +#define EMMC_GPCS BIT(27) +#define EMMC_HOST BIT(26) +#define EMMC_TX16 BIT(25) +#define EMMC_RX16 BIT(24) /* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */ #define PHYC_SLSPD_POS 30 @@ -228,11 +228,11 @@ enum temac_ctrl { #define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS) #define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS) #define PHYC_RLSPD_10 0 -#define PHYC_RGMII_HD (1 << 1) -#define PHYC_RGMII_LINK (1 << 0) +#define PHYC_RGMII_HD BIT(1) +#define PHYC_RGMII_LINK BIT(0) /* Management Configuration Registers (MC), [1] p57 */ -#define MC_MDIOEN (1 << 6) +#define MC_MDIOEN BIT(6) #define MC_CLKDIV_POS 0 #define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS) @@ -256,23 +256,23 @@ enum temac_ctrl { /* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */ #define MAW0_MADDR_POS 0 #define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS) -#define MAW1_RNW (1 << 23) +#define MAW1_RNW BIT(23) #define MAW1_MAIDX_POS 16 #define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS) #define MAW1_MADDR_POS 0 #define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS) /* Address Filter Mode Registers (AFM), [1] p63 */ -#define AFM_PM (1 << 31) +#define AFM_PM BIT(31) /* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */ -#define TISE_CFG_W (1 << 6) -#define TISE_CFG_R (1 << 5) -#define TISE_AF_W (1 << 4) -#define TISE_AF_R (1 << 3) -#define TISE_MIIM_W (1 << 2) -#define TISE_MIIM_R (1 << 1) -#define TISE_FABR_R (1 << 0) +#define TISE_CFG_W BIT(6) +#define TISE_CFG_R BIT(5) +#define TISE_AF_W BIT(4) +#define TISE_AF_R BIT(3) +#define TISE_MIIM_W BIT(2) +#define TISE_MIIM_R BIT(1) +#define TISE_FABR_R BIT(0) /* MII Management Write Data Registers (MIIMWD), [1] p66 */ #define MIIMWD_DATA_POS 0 diff --git a/drivers/net/xilinx_ll_temac_fifo.h b/drivers/net/xilinx_ll_temac_fifo.h index c1bf7cc..1ffd3ef 100644 --- a/drivers/net/xilinx_ll_temac_fifo.h +++ b/drivers/net/xilinx_ll_temac_fifo.h @@ -55,26 +55,26 @@ struct fifo_ctrl { }; /* Interrupt Status Register (ISR), [1] p11 */ -#define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ -#define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ -#define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */ -#define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */ -#define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */ -#define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */ -#define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */ -#define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */ -#define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */ +#define LL_FIFO_ISR_RPURE BIT(31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_ISR_RPORE BIT(30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_ISR_RPUE BIT(29) /* Receive Packet Underrun Error */ +#define LL_FIFO_ISR_TPOE BIT(28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_ISR_TC BIT(27) /* Transmit Complete */ +#define LL_FIFO_ISR_RC BIT(26) /* Receive Complete */ +#define LL_FIFO_ISR_TSE BIT(25) /* Transmit Size Error */ +#define LL_FIFO_ISR_TRC BIT(24) /* Transmit Reset Complete */ +#define LL_FIFO_ISR_RRC BIT(23) /* Receive Reset Complete */ /* Interrupt Enable Register (IER), [1] p12/p13 */ -#define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ -#define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ -#define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */ -#define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */ -#define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */ -#define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */ -#define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */ -#define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */ -#define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */ +#define LL_FIFO_IER_RPURE BIT(31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_IER_RPORE BIT(30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_IER_RPUE BIT(29) /* Receive Packet Underrun Error */ +#define LL_FIFO_IER_TPOE BIT(28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_IER_TC BIT(27) /* Transmit Complete */ +#define LL_FIFO_IER_RC BIT(26) /* Receive Complete */ +#define LL_FIFO_IER_TSE BIT(25) /* Transmit Size Error */ +#define LL_FIFO_IER_TRC BIT(24) /* Transmit Reset Complete */ +#define LL_FIFO_IER_RRC BIT(23) /* Receive Reset Complete */ /* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */ #define LL_FIFO_TDFR_KEY 0x000000A5UL diff --git a/drivers/net/xilinx_ll_temac_sdma.h b/drivers/net/xilinx_ll_temac_sdma.h index 41659c0..efecff8 100644 --- a/drivers/net/xilinx_ll_temac_sdma.h +++ b/drivers/net/xilinx_ll_temac_sdma.h @@ -62,16 +62,16 @@ struct cdmac_bd { }; /* CDMAC Descriptor Status and Control (stctrl), [1] p140, [2] p230 */ -#define CDMAC_BD_STCTRL_ERROR (1 << 7) -#define CDMAC_BD_STCTRL_IRQ_ON_END (1 << 6) -#define CDMAC_BD_STCTRL_STOP_ON_END (1 << 5) -#define CDMAC_BD_STCTRL_COMPLETED (1 << 4) -#define CDMAC_BD_STCTRL_SOP (1 << 3) -#define CDMAC_BD_STCTRL_EOP (1 << 2) -#define CDMAC_BD_STCTRL_DMACHBUSY (1 << 1) +#define CDMAC_BD_STCTRL_ERROR BIT(7) +#define CDMAC_BD_STCTRL_IRQ_ON_END BIT(6) +#define CDMAC_BD_STCTRL_STOP_ON_END BIT(5) +#define CDMAC_BD_STCTRL_COMPLETED BIT(4) +#define CDMAC_BD_STCTRL_SOP BIT(3) +#define CDMAC_BD_STCTRL_EOP BIT(2) +#define CDMAC_BD_STCTRL_DMACHBUSY BIT(1) /* CDMAC Descriptor APP0: Transmit LocalLink Footer Word 3, [3] p72 */ -#define CDMAC_BD_APP0_TXCSCNTRL (1 << 0) +#define CDMAC_BD_APP0_TXCSCNTRL BIT(0) /* CDMAC Descriptor APP1: Transmit LocalLink Footer Word 4, [3] p73 */ #define CDMAC_BD_APP1_TXCSBEGIN_POS 16 @@ -92,9 +92,9 @@ struct cdmac_bd { #define CDMAC_BD_APP1_MADDRL_MASK (~0UL << CDMAC_BD_APP1_MADDRL_POS) /* CDMAC Descriptor APP2: Receive LocalLink Footer Word 5, [3] p74 */ -#define CDMAC_BD_APP2_BCAST_FRAME (1 << 2) -#define CDMAC_BD_APP2_IPC_MCAST_FRAME (1 << 1) -#define CDMAC_BD_APP2_MAC_MCAST_FRAME (1 << 0) +#define CDMAC_BD_APP2_BCAST_FRAME BIT(2) +#define CDMAC_BD_APP2_IPC_MCAST_FRAME BIT(1) +#define CDMAC_BD_APP2_MAC_MCAST_FRAME BIT(0) /* CDMAC Descriptor APP3: Receive LocalLink Footer Word 6, [3] p74 */ #define CDMAC_BD_APP3_TLTPID_POS 16 @@ -183,14 +183,14 @@ enum dmac_ctrl { #define CHNL_CTRL_IC_MASK (0xFF << CHNL_CTRL_IC_POS) #define CHNL_CTRL_MSBADDR_POS 12 #define CHNL_CTRL_MSBADDR_MASK (0xF << CHNL_CTRL_MSBADDR_POS) -#define CHNL_CTRL_AME (1 << 11) -#define CHNL_CTRL_OBWC (1 << 10) -#define CHNL_CTRL_IOE (1 << 9) -#define CHNL_CTRL_LIC (1 << 8) -#define CHNL_CTRL_IE (1 << 7) -#define CHNL_CTRL_IEE (1 << 2) -#define CHNL_CTRL_IDE (1 << 1) -#define CHNL_CTRL_ICE (1 << 0) +#define CHNL_CTRL_AME BIT(11) +#define CHNL_CTRL_OBWC BIT(10) +#define CHNL_CTRL_IOE BIT(9) +#define CHNL_CTRL_LIC BIT(8) +#define CHNL_CTRL_IE BIT(7) +#define CHNL_CTRL_IEE BIT(2) +#define CHNL_CTRL_IDE BIT(1) +#define CHNL_CTRL_ICE BIT(0) /* All interrupt enable bits */ #define CHNL_CTRL_IRQ_MASK (CHNL_CTRL_IE | \ @@ -203,16 +203,16 @@ enum dmac_ctrl { #define IRQ_REG_DTV_MASK (0xFF << IRQ_REG_DTV_POS) #define IRQ_REG_CCV_POS 16 #define IRQ_REG_CCV_MASK (0xFF << IRQ_REG_CCV_POS) -#define IRQ_REG_WRCQ_EMPTY (1 << 14) +#define IRQ_REG_WRCQ_EMPTY BIT(14) #define IRQ_REG_CIC_POS 10 #define IRQ_REG_CIC_MASK (0xF << IRQ_REG_CIC_POS) #define IRQ_REG_DIC_POS 8 #define IRQ_REG_DIC_MASK (3 << 8) -#define IRQ_REG_PLB_RD_NMI (1 << 4) -#define IRQ_REG_PLB_WR_NMI (1 << 3) -#define IRQ_REG_EI (1 << 2) -#define IRQ_REG_DI (1 << 1) -#define IRQ_REG_CI (1 << 0) +#define IRQ_REG_PLB_RD_NMI BIT(4) +#define IRQ_REG_PLB_WR_NMI BIT(3) +#define IRQ_REG_EI BIT(2) +#define IRQ_REG_DI BIT(1) +#define IRQ_REG_CI BIT(0) /* All interrupt bits */ #define IRQ_REG_IRQ_MASK (IRQ_REG_PLB_RD_NMI | \ @@ -220,26 +220,26 @@ enum dmac_ctrl { IRQ_REG_EI | IRQ_REG_DI | IRQ_REG_CI) /* Rx/Tx Channel Status Register (*_chnl_sts), [1] p165, [2] p249/p255 */ -#define CHNL_STS_ERROR_TAIL (1 << 21) -#define CHNL_STS_ERROR_CMP (1 << 20) -#define CHNL_STS_ERROR_ADDR (1 << 19) -#define CHNL_STS_ERROR_NXTP (1 << 18) -#define CHNL_STS_ERROR_CURP (1 << 17) -#define CHNL_STS_ERROR_BSYWR (1 << 16) -#define CHNL_STS_ERROR (1 << 7) -#define CHNL_STS_IOE (1 << 6) -#define CHNL_STS_SOE (1 << 5) -#define CHNL_STS_CMPLT (1 << 4) -#define CHNL_STS_SOP (1 << 3) -#define CHNL_STS_EOP (1 << 2) -#define CHNL_STS_EBUSY (1 << 1) +#define CHNL_STS_ERROR_TAIL BIT(21) +#define CHNL_STS_ERROR_CMP BIT(20) +#define CHNL_STS_ERROR_ADDR BIT(19) +#define CHNL_STS_ERROR_NXTP BIT(18) +#define CHNL_STS_ERROR_CURP BIT(17) +#define CHNL_STS_ERROR_BSYWR BIT(16) +#define CHNL_STS_ERROR BIT(7) +#define CHNL_STS_IOE BIT(6) +#define CHNL_STS_SOE BIT(5) +#define CHNL_STS_CMPLT BIT(4) +#define CHNL_STS_SOP BIT(3) +#define CHNL_STS_EOP BIT(2) +#define CHNL_STS_EBUSY BIT(1) /* DMA Control Register (dma_control_reg), [1] p166, [2] p256 */ -#define DMA_CONTROL_PLBED (1 << 5) -#define DMA_CONTROL_RXOCEID (1 << 4) -#define DMA_CONTROL_TXOCEID (1 << 3) -#define DMA_CONTROL_TPE (1 << 2) -#define DMA_CONTROL_RESET (1 << 0) +#define DMA_CONTROL_PLBED BIT(5) +#define DMA_CONTROL_RXOCEID BIT(4) +#define DMA_CONTROL_TXOCEID BIT(3) +#define DMA_CONTROL_TPE BIT(2) +#define DMA_CONTROL_RESET BIT(0) #if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 67b5fdf..e81a79e 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -63,34 +63,34 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_MSI_AXI_BAR_ST 0x68 #define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_EN_FPCI BIT(0) #define AFI_FPCI_ERROR_MASKS 0xb0 #define AFI_INTR_MASK 0xb4 -#define AFI_INTR_MASK_INT_MASK (1 << 0) -#define AFI_INTR_MASK_MSI_MASK (1 << 8) +#define AFI_INTR_MASK_INT_MASK BIT(0) +#define AFI_INTR_MASK_MSI_MASK BIT(8) #define AFI_SM_INTR_ENABLE 0xc4 -#define AFI_SM_INTR_INTA_ASSERT (1 << 0) -#define AFI_SM_INTR_INTB_ASSERT (1 << 1) -#define AFI_SM_INTR_INTC_ASSERT (1 << 2) -#define AFI_SM_INTR_INTD_ASSERT (1 << 3) -#define AFI_SM_INTR_INTA_DEASSERT (1 << 4) -#define AFI_SM_INTR_INTB_DEASSERT (1 << 5) -#define AFI_SM_INTR_INTC_DEASSERT (1 << 6) -#define AFI_SM_INTR_INTD_DEASSERT (1 << 7) +#define AFI_SM_INTR_INTA_ASSERT BIT(0) +#define AFI_SM_INTR_INTB_ASSERT BIT(1) +#define AFI_SM_INTR_INTC_ASSERT BIT(2) +#define AFI_SM_INTR_INTD_ASSERT BIT(3) +#define AFI_SM_INTR_INTA_DEASSERT BIT(4) +#define AFI_SM_INTR_INTB_DEASSERT BIT(5) +#define AFI_SM_INTR_INTC_DEASSERT BIT(6) +#define AFI_SM_INTR_INTD_DEASSERT BIT(7) #define AFI_AFI_INTR_ENABLE 0xc8 -#define AFI_INTR_EN_INI_SLVERR (1 << 0) -#define AFI_INTR_EN_INI_DECERR (1 << 1) -#define AFI_INTR_EN_TGT_SLVERR (1 << 2) -#define AFI_INTR_EN_TGT_DECERR (1 << 3) -#define AFI_INTR_EN_TGT_WRERR (1 << 4) -#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) -#define AFI_INTR_EN_AXI_DECERR (1 << 6) -#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) -#define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_INTR_EN_INI_SLVERR BIT(0) +#define AFI_INTR_EN_INI_DECERR BIT(1) +#define AFI_INTR_EN_TGT_SLVERR BIT(2) +#define AFI_INTR_EN_TGT_DECERR BIT(3) +#define AFI_INTR_EN_TGT_WRERR BIT(4) +#define AFI_INTR_EN_DFPCI_DECERR BIT(5) +#define AFI_INTR_EN_AXI_DECERR BIT(6) +#define AFI_INTR_EN_FPCI_TIMEOUT BIT(7) +#define AFI_INTR_EN_PRSNT_SENSE BIT(8) #define AFI_PCIE_CONFIG 0x0f8 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) @@ -105,19 +105,19 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) #define AFI_FUSE 0x104 -#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) +#define AFI_FUSE_PCIE_T0_GEN2_DIS BIT(2) #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 #define AFI_PEX2_CTRL 0x128 -#define AFI_PEX_CTRL_RST (1 << 0) -#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) -#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) -#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) +#define AFI_PEX_CTRL_RST BIT(0) +#define AFI_PEX_CTRL_CLKREQ_EN BIT(1) +#define AFI_PEX_CTRL_REFCLK_EN BIT(3) +#define AFI_PEX_CTRL_OVERRIDE_EN BIT(4) #define AFI_PLLE_CONTROL 0x160 -#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) -#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) +#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL BIT(9) +#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN BIT(1) #define AFI_PEXBIAS_CTRL_0 0x168 @@ -126,7 +126,7 @@ DECLARE_GLOBAL_DATA_PTR; #define PADS_CTL 0x000000A0 #define PADS_CTL_IDDQ_1L (1 << 0) #define PADS_CTL_TX_DATA_EN_1L (1 << 6) -#define PADS_CTL_RX_DATA_EN_1L (1 << 10) +#define PADS_CTL_RX_DATA_EN_1L BIT(10) #define PADS_PLL_CTL_TEGRA20 0x000000B8 #define PADS_PLL_CTL_TEGRA30 0x000000B4 @@ -164,7 +164,7 @@ DECLARE_GLOBAL_DATA_PTR; ) #define RP_VEND_XP 0x00000F00 -#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_VEND_XP_DL_UP BIT(30) #define RP_PRIV_MISC 0x00000FE0 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) @@ -428,7 +428,7 @@ static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, case 0x02: /* 32 bit */ case 0x03: /* 64 bit */ - if (space & (1 << 30)) + if (space & BIT(30)) res = &pcie->prefetch; else res = &pcie->mem; @@ -605,8 +605,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) if (soc->has_cml_clk) { /* enable CML clock */ value = readl(NV_PA_CLK_RST_BASE + 0x48c); - value |= (1 << 0); - value &= ~(1 << 1); + value |= BIT(0); + value &= ~BIT(1); writel(value, NV_PA_CLK_RST_BASE + 0x48c); } diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index fd7e4d4..7eeee9e 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -43,8 +43,8 @@ #define PL_OFFSET 0x700 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) -#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) -#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) +#define PCIE_PHY_DEBUG_R1_LINK_UP BIT(4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING BIT(29) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -61,10 +61,10 @@ #define PCIE_PHY_RX_ASIC_OUT 0x100D #define PHY_RX_OVRD_IN_LO 0x1005 -#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) -#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) -#define PCIE_PHY_PUP_REQ (1 << 7) +#define PCIE_PHY_PUP_REQ BIT(7) /* iATU registers */ #define PCIE_ATU_VIEWPORT 0x900 diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c index a60bb5f..221f67a 100644 --- a/drivers/power/as3722.c +++ b/drivers/power/as3722.c @@ -16,9 +16,9 @@ #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) -#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) +#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH BIT(0) #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) -#define AS3722_GPIO_CONTROL_INVERT (1 << 7) +#define AS3722_GPIO_CONTROL_INVERT BIT(7) #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) #define AS3722_GPIO_SIGNAL_OUT 0x20 #define AS3722_SD_CONTROL 0x4d diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c index 9a093a5..d36714f 100644 --- a/drivers/power/exynos-tmu.c +++ b/drivers/power/exynos-tmu.c @@ -26,23 +26,23 @@ #define TRIMINFO_RELOAD 1 #define CORE_EN 1 -#define THERM_TRIP_EN (1 << 12) +#define THERM_TRIP_EN BIT(12) #define INTEN_RISE0 1 -#define INTEN_RISE1 (1 << 4) -#define INTEN_RISE2 (1 << 8) -#define INTEN_FALL0 (1 << 16) -#define INTEN_FALL1 (1 << 20) -#define INTEN_FALL2 (1 << 24) +#define INTEN_RISE1 BIT(4) +#define INTEN_RISE2 BIT(8) +#define INTEN_FALL0 BIT(16) +#define INTEN_FALL1 BIT(20) +#define INTEN_FALL2 BIT(24) #define TRIM_INFO_MASK 0xff #define INTCLEAR_RISE0 1 -#define INTCLEAR_RISE1 (1 << 4) -#define INTCLEAR_RISE2 (1 << 8) -#define INTCLEAR_FALL0 (1 << 16) -#define INTCLEAR_FALL1 (1 << 20) -#define INTCLEAR_FALL2 (1 << 24) +#define INTCLEAR_RISE1 BIT(4) +#define INTCLEAR_RISE2 BIT(8) +#define INTCLEAR_FALL0 BIT(16) +#define INTCLEAR_FALL1 BIT(20) +#define INTCLEAR_FALL2 BIT(24) #define INTCLEARALL (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \ INTCLEAR_RISE2 | INTCLEAR_FALL0 | \ INTCLEAR_FALL1 | INTCLEAR_FALL2) diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index e701787..54c376f 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -469,10 +469,10 @@ static int bcm_init(struct uec_mii_info *mii_info) val = uec_phy_read(mii_info, 0x18); /* Set RDX-RXC skew. */ - val |= (1 << 8); + val |= BIT(8); val |= (7 | (7 << 12)); /* Write bits 14:0. */ - val |= (1 << 15); + val |= BIT(15); uec_phy_write(mii_info, 0x18, val); } diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 11cbc25..7af3298 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -127,33 +127,33 @@ #define DUPLEX_FULL 0x01 /* Indicates what features are supported by the interface. */ -#define SUPPORTED_10baseT_Half (1 << 0) -#define SUPPORTED_10baseT_Full (1 << 1) -#define SUPPORTED_100baseT_Half (1 << 2) -#define SUPPORTED_100baseT_Full (1 << 3) -#define SUPPORTED_1000baseT_Half (1 << 4) -#define SUPPORTED_1000baseT_Full (1 << 5) -#define SUPPORTED_Autoneg (1 << 6) -#define SUPPORTED_TP (1 << 7) -#define SUPPORTED_AUI (1 << 8) -#define SUPPORTED_MII (1 << 9) -#define SUPPORTED_FIBRE (1 << 10) -#define SUPPORTED_BNC (1 << 11) -#define SUPPORTED_10000baseT_Full (1 << 12) - -#define ADVERTISED_10baseT_Half (1 << 0) -#define ADVERTISED_10baseT_Full (1 << 1) -#define ADVERTISED_100baseT_Half (1 << 2) -#define ADVERTISED_100baseT_Full (1 << 3) -#define ADVERTISED_1000baseT_Half (1 << 4) -#define ADVERTISED_1000baseT_Full (1 << 5) -#define ADVERTISED_Autoneg (1 << 6) -#define ADVERTISED_TP (1 << 7) -#define ADVERTISED_AUI (1 << 8) -#define ADVERTISED_MII (1 << 9) -#define ADVERTISED_FIBRE (1 << 10) -#define ADVERTISED_BNC (1 << 11) -#define ADVERTISED_10000baseT_Full (1 << 12) +#define SUPPORTED_10baseT_Half BIT(0) +#define SUPPORTED_10baseT_Full BIT(1) +#define SUPPORTED_100baseT_Half BIT(2) +#define SUPPORTED_100baseT_Full BIT(3) +#define SUPPORTED_1000baseT_Half BIT(4) +#define SUPPORTED_1000baseT_Full BIT(5) +#define SUPPORTED_Autoneg BIT(6) +#define SUPPORTED_TP BIT(7) +#define SUPPORTED_AUI BIT(8) +#define SUPPORTED_MII BIT(9) +#define SUPPORTED_FIBRE BIT(10) +#define SUPPORTED_BNC BIT(11) +#define SUPPORTED_10000baseT_Full BIT(12) + +#define ADVERTISED_10baseT_Half BIT(0) +#define ADVERTISED_10baseT_Full BIT(1) +#define ADVERTISED_100baseT_Half BIT(2) +#define ADVERTISED_100baseT_Full BIT(3) +#define ADVERTISED_1000baseT_Half BIT(4) +#define ADVERTISED_1000baseT_Full BIT(5) +#define ADVERTISED_Autoneg BIT(6) +#define ADVERTISED_TP BIT(7) +#define ADVERTISED_AUI BIT(8) +#define ADVERTISED_MII BIT(9) +#define ADVERTISED_FIBRE BIT(10) +#define ADVERTISED_BNC BIT(11) +#define ADVERTISED_10000baseT_Full BIT(12) /* Taken from mii_if_info and sungem_phy.h */ struct uec_mii_info { diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 713dad2..03fb8bf 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -34,11 +34,11 @@ struct ftrtc010 { /* * RTC Control Register */ -#define FTRTC010_CR_ENABLE (1 << 0) -#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ -#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ -#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ -#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ +#define FTRTC010_CR_ENABLE BIT(0) +#define FTRTC010_CR_INTERRUPT_SEC BIT(1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN BIT(2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR BIT(3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY BIT(4) /* per day irq */ static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; diff --git a/drivers/rtc/imxdi.c b/drivers/rtc/imxdi.c index 0d7d736..8062344 100644 --- a/drivers/rtc/imxdi.c +++ b/drivers/rtc/imxdi.c @@ -37,20 +37,20 @@ struct imxdi_regs { #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ -#define DCR_TCE (1 << 3) /* Time Counter Enable */ - -#define DSR_WBF (1 << 10) /* Write Busy Flag */ -#define DSR_WNF (1 << 9) /* Write Next Flag */ -#define DSR_WCF (1 << 8) /* Write Complete Flag */ -#define DSR_WEF (1 << 7) /* Write Error Flag */ -#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ -#define DSR_NVF (1 << 1) /* Non-Valid Flag */ -#define DSR_SVF (1 << 0) /* Security Violation Flag */ - -#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ -#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ -#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ -#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ +#define DCR_TCE BIT(3) /* Time Counter Enable */ + +#define DSR_WBF BIT(10) /* Write Busy Flag */ +#define DSR_WNF BIT(9) /* Write Next Flag */ +#define DSR_WCF BIT(8) /* Write Complete Flag */ +#define DSR_WEF BIT(7) /* Write Error Flag */ +#define DSR_CAF BIT(4) /* Clock Alarm Flag */ +#define DSR_NVF BIT(1) /* Non-Valid Flag */ +#define DSR_SVF BIT(0) /* Security Violation Flag */ + +#define DIER_WNIE BIT(9) /* Write Next Interrupt Enable */ +#define DIER_WCIE BIT(8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE BIT(7) /* Write Error Interrupt Enable */ +#define DIER_CAIE BIT(4) /* Clock Alarm Interrupt Enable */ /* Driver Private Data */ diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 3829bc5..2d6234a 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -40,17 +40,17 @@ #define M41T62_ALARM_REG_SIZE \ (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON) -#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */ -#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */ -#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ -#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ -#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ -#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ +#define M41T62_SEC_ST BIT(7) /* ST: Stop Bit */ +#define M41T62_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */ +#define M41T62_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */ +#define M41T62_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */ +#define M41T62_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */ +#define M41T62_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */ -#define M41T62_FEATURE_HT (1 << 0) -#define M41T62_FEATURE_BL (1 << 1) +#define M41T62_FEATURE_HT BIT(0) +#define M41T62_FEATURE_BL BIT(1) -#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ +#define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */ int rtc_get(struct rtc_time *tm) { diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 44857a6..d031da7 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -43,10 +43,10 @@ #define RTC_CONFIG_D 0x0D #define RTC_REG_SIZE 0x80 -#define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5) +#define RTC_CONFIG_A_REF_CLCK_32KHZ BIT(5) #define RTC_CONFIG_A_RATE_1024HZ 6 -#define RTC_CONFIG_B_24H (1 << 1) +#define RTC_CONFIG_B_24H BIT(1) #define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80 diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index c4d1259..f8adad8 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -29,7 +29,7 @@ #define RTC_MIS 0x18 /* Masked interrupt status register */ #define RTC_ICR 0x1c /* Interrupt clear register */ -#define RTC_CR_START (1 << 0) +#define RTC_CR_START BIT(0) #define RTC_WRITE_REG(addr, val) \ (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)) = (val)) diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c index f08040a..f41b4f3 100644 --- a/drivers/rtc/rv3029.c +++ b/drivers/rtc/rv3029.c @@ -10,13 +10,13 @@ #include #define RTC_RV3029_CTRL1 0x00 -#define RTC_RV3029_CTRL1_EERE (1 << 3) +#define RTC_RV3029_CTRL1_EERE BIT(3) #define RTC_RV3029_CTRL_STATUS 0x03 -#define RTC_RV3029_CTRLS_EEBUSY (1 << 7) +#define RTC_RV3029_CTRLS_EEBUSY BIT(7) #define RTC_RV3029_CTRL_RESET 0x04 -#define RTC_RV3029_CTRL_SYS_R (1 << 4) +#define RTC_RV3029_CTRL_SYS_R BIT(4) #define RTC_RV3029_CLOCK_PAGE 0x08 #define RTC_RV3029_PAGE_LEN 7 @@ -29,14 +29,14 @@ #define RV3029C2_W_MONTHS 0x05 #define RV3029C2_W_YEARS 0x06 -#define RV3029C2_REG_HR_12_24 (1 << 6) /* 24h/12h mode */ -#define RV3029C2_REG_HR_PM (1 << 5) /* PM/AM bit in 12h mode */ +#define RV3029C2_REG_HR_12_24 BIT(6) /* 24h/12h mode */ +#define RV3029C2_REG_HR_PM BIT(5) /* PM/AM bit in 12h mode */ #define RTC_RV3029_EEPROM_CTRL 0x30 -#define RTC_RV3029_TRICKLE_1K (1 << 4) -#define RTC_RV3029_TRICKLE_5K (1 << 5) -#define RTC_RV3029_TRICKLE_20K (1 << 6) -#define RTC_RV3029_TRICKLE_80K (1 << 7) +#define RTC_RV3029_TRICKLE_1K BIT(4) +#define RTC_RV3029_TRICKLE_5K BIT(5) +#define RTC_RV3029_TRICKLE_20K BIT(6) +#define RTC_RV3029_TRICKLE_80K BIT(7) int rtc_get( struct rtc_time *tmp ) { diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 9a81402..2b325d3 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -22,12 +22,12 @@ typedef volatile struct { #define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ /* control register */ -#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ -#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ -#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ -#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ -#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ -#define NIOS_JTAG_RRDY (1 << 12) /* read available */ +#define NIOS_JTAG_RE BIT(0) /* read intr enable */ +#define NIOS_JTAG_WE BIT(1) /* write intr enable */ +#define NIOS_JTAG_RI BIT(8) /* read intr pending */ +#define NIOS_JTAG_WI BIT(9) /* write intr pending*/ +#define NIOS_JTAG_AC BIT(10) /* activity indicator */ +#define NIOS_JTAG_RRDY BIT(12) /* read available */ #define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index d6b1484..da7b1b0 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -22,33 +22,33 @@ typedef volatile struct { } nios_uart_t; /* status register */ -#define NIOS_UART_PE (1 << 0) /* parity error */ -#define NIOS_UART_FE (1 << 1) /* frame error */ -#define NIOS_UART_BRK (1 << 2) /* break detect */ -#define NIOS_UART_ROE (1 << 3) /* rx overrun */ -#define NIOS_UART_TOE (1 << 4) /* tx overrun */ -#define NIOS_UART_TMT (1 << 5) /* tx empty */ -#define NIOS_UART_TRDY (1 << 6) /* tx ready */ -#define NIOS_UART_RRDY (1 << 7) /* rx ready */ -#define NIOS_UART_E (1 << 8) /* exception */ -#define NIOS_UART_DCTS (1 << 10) /* cts change */ -#define NIOS_UART_CTS (1 << 11) /* cts */ -#define NIOS_UART_EOP (1 << 12) /* eop detected */ +#define NIOS_UART_PE BIT(0) /* parity error */ +#define NIOS_UART_FE BIT(1) /* frame error */ +#define NIOS_UART_BRK BIT(2) /* break detect */ +#define NIOS_UART_ROE BIT(3) /* rx overrun */ +#define NIOS_UART_TOE BIT(4) /* tx overrun */ +#define NIOS_UART_TMT BIT(5) /* tx empty */ +#define NIOS_UART_TRDY BIT(6) /* tx ready */ +#define NIOS_UART_RRDY BIT(7) /* rx ready */ +#define NIOS_UART_E BIT(8) /* exception */ +#define NIOS_UART_DCTS BIT(10) /* cts change */ +#define NIOS_UART_CTS BIT(11) /* cts */ +#define NIOS_UART_EOP BIT(12) /* eop detected */ /* control register */ -#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ -#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ -#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ -#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ -#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_UART_IE (1 << 8) /* exception int ena */ -#define NIOS_UART_TBRK (1 << 9) /* transmit break */ -#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ -#define NIOS_UART_RTS (1 << 11) /* rts */ -#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ +#define NIOS_UART_IPE BIT(0) /* parity error int ena*/ +#define NIOS_UART_IFE BIT(1) /* frame error int ena */ +#define NIOS_UART_IBRK BIT(2) /* break detect int ena */ +#define NIOS_UART_IROE BIT(3) /* rx overrun int ena */ +#define NIOS_UART_ITOE BIT(4) /* tx overrun int ena */ +#define NIOS_UART_ITMT BIT(5) /* tx empty int ena */ +#define NIOS_UART_ITRDY BIT(6) /* tx ready int ena */ +#define NIOS_UART_IRRDY BIT(7) /* rx ready int ena */ +#define NIOS_UART_IE BIT(8) /* exception int ena */ +#define NIOS_UART_TBRK BIT(9) /* transmit break */ +#define NIOS_UART_IDCTS BIT(10) /* cts change int ena */ +#define NIOS_UART_RTS BIT(11) /* rts */ +#define NIOS_UART_IEOP BIT(12) /* eop detected int ena */ DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 5dfb02f..7144c6b 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -33,8 +33,8 @@ /* * ARMV6 */ -#define DCC_RBIT (1 << 30) -#define DCC_WBIT (1 << 29) +#define DCC_RBIT BIT(30) +#define DCC_WBIT BIT(29) #define write_dcc(x) \ __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) @@ -49,8 +49,8 @@ /* * XSCALE */ -#define DCC_RBIT (1 << 31) -#define DCC_WBIT (1 << 28) +#define DCC_RBIT BIT(31) +#define DCC_WBIT BIT(28) #define write_dcc(x) \ __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x)) @@ -62,8 +62,8 @@ __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) #else -#define DCC_RBIT (1 << 0) -#define DCC_WBIT (1 << 1) +#define DCC_RBIT BIT(0) +#define DCC_WBIT BIT(1) #define write_dcc(x) \ __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index fd110b3..9d9f4da 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SOC_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 -#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE (BIT(14) | BIT(13) | BIT(0)) #undef UART_MCRVAL #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index f68c8d0..89ab4d5 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -19,8 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; /* YANU Imagos serial port */ /*-----------------------------------------------------------------*/ -#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ -#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_MAX_PRESCALER_N (BIT(4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M (BIT(11) -1) /* 2047 */ #define YANU_FIFO_SIZE (16) #define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) #define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 54e596c..ed5bd1e 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -31,9 +31,9 @@ struct arc_serial_platdata { }; /* Bit definitions of STATUS register */ -#define UART_RXEMPTY (1 << 5) -#define UART_OVERFLOW_ERR (1 << 1) -#define UART_TXEMPTY (1 << 7) +#define UART_RXEMPTY BIT(5) +#define UART_OVERFLOW_ERR BIT(1) +#define UART_TXEMPTY BIT(7) static int arc_serial_setbrg(struct udevice *dev, int baudrate) { diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 63fc388..ef085b7 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -12,32 +12,32 @@ #include #include -#define US1_TDRE (1 << 7) -#define US1_RDRF (1 << 5) -#define US1_OR (1 << 3) -#define UC2_TE (1 << 3) -#define UC2_RE (1 << 2) -#define CFIFO_TXFLUSH (1 << 7) -#define CFIFO_RXFLUSH (1 << 6) -#define SFIFO_RXOF (1 << 2) -#define SFIFO_RXUF (1 << 0) - -#define STAT_LBKDIF (1 << 31) -#define STAT_RXEDGIF (1 << 30) -#define STAT_TDRE (1 << 23) -#define STAT_RDRF (1 << 21) -#define STAT_IDLE (1 << 20) -#define STAT_OR (1 << 19) -#define STAT_NF (1 << 18) -#define STAT_FE (1 << 17) -#define STAT_PF (1 << 16) -#define STAT_MA1F (1 << 15) -#define STAT_MA2F (1 << 14) +#define US1_TDRE BIT(7) +#define US1_RDRF BIT(5) +#define US1_OR BIT(3) +#define UC2_TE BIT(3) +#define UC2_RE BIT(2) +#define CFIFO_TXFLUSH BIT(7) +#define CFIFO_RXFLUSH BIT(6) +#define SFIFO_RXOF BIT(2) +#define SFIFO_RXUF BIT(0) + +#define STAT_LBKDIF BIT(31) +#define STAT_RXEDGIF BIT(30) +#define STAT_TDRE BIT(23) +#define STAT_RDRF BIT(21) +#define STAT_IDLE BIT(20) +#define STAT_OR BIT(19) +#define STAT_NF BIT(18) +#define STAT_FE BIT(17) +#define STAT_PF BIT(16) +#define STAT_MA1F BIT(15) +#define STAT_MA2F BIT(14) #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \ STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F) -#define CTRL_TE (1 << 19) -#define CTRL_RE (1 << 18) +#define CTRL_TE BIT(19) +#define CTRL_RE BIT(18) #define FIFO_TXFE 0x80 #define FIFO_RXFE 0x40 diff --git a/drivers/serial/serial_max3100.c b/drivers/serial/serial_max3100.c index 027d919..9641515 100644 --- a/drivers/serial/serial_max3100.c +++ b/drivers/serial/serial_max3100.c @@ -50,15 +50,15 @@ DECLARE_GLOBAL_DATA_PTR; /* MAX3100 definitions */ #define MAX3100_WC (3 << 14) /* write configuration */ -#define MAX3100_RC (1 << 14) /* read configuration */ +#define MAX3100_RC BIT(14) /* read configuration */ #define MAX3100_WD (2 << 14) /* write data */ #define MAX3100_RD (0 << 14) /* read data */ /* configuration register bits */ -#define MAX3100_FEN (1 << 13) /* FIFO enable */ -#define MAX3100_SHDN (1 << 12) /* shutdown bit */ -#define MAX3100_TM (1 << 11) /* T bit irq mask */ -#define MAX3100_RM (1 << 10) /* R bit irq mask */ +#define MAX3100_FEN BIT(13) /* FIFO enable */ +#define MAX3100_SHDN BIT(12) /* shutdown bit */ +#define MAX3100_TM BIT(11) /* T bit irq mask */ +#define MAX3100_RM BIT(10) /* R bit irq mask */ #define MAX3100_PM (1 << 9) /* P bit irq mask */ #define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */ #define MAX3100_IR (1 << 7) /* IRDA timing mode */ @@ -69,17 +69,17 @@ DECLARE_GLOBAL_DATA_PTR; #define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */ /* data register bits (write) */ -#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */ +#define MAX3100_TE BIT(10) /* transmit enable bit (active low) */ #define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */ /* data register bits (read) */ -#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */ -#define MAX3100_FE (1 << 10) /* framing error when in normal mode */ +#define MAX3100_RA BIT(10) /* receiver activity when in shutdown mode */ +#define MAX3100_FE BIT(10) /* framing error when in normal mode */ #define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */ /* data register bits (both directions) */ -#define MAX3100_R (1 << 15) /* receive bit */ -#define MAX3100_T (1 << 14) /* transmit bit */ +#define MAX3100_R BIT(15) /* receive bit */ +#define MAX3100_T BIT(14) /* transmit bit */ #define MAX3100_P (1 << 8) /* parity bit */ #define MAX3100_D_MASK 0x00FF /* data bits mask */ #define MAX3100_D(x) ((x) & 0x00FF) /* data bits */ diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h index 288a4f1..8d1b7b4 100644 --- a/drivers/serial/serial_pl01x_internal.h +++ b/drivers/serial/serial_pl01x_internal.h @@ -56,24 +56,24 @@ struct pl01x_regs { * PL010 definitions * */ -#define UART_PL010_CR_LPE (1 << 7) -#define UART_PL010_CR_RTIE (1 << 6) -#define UART_PL010_CR_TIE (1 << 5) -#define UART_PL010_CR_RIE (1 << 4) -#define UART_PL010_CR_MSIE (1 << 3) -#define UART_PL010_CR_IIRLP (1 << 2) -#define UART_PL010_CR_SIREN (1 << 1) -#define UART_PL010_CR_UARTEN (1 << 0) +#define UART_PL010_CR_LPE BIT(7) +#define UART_PL010_CR_RTIE BIT(6) +#define UART_PL010_CR_TIE BIT(5) +#define UART_PL010_CR_RIE BIT(4) +#define UART_PL010_CR_MSIE BIT(3) +#define UART_PL010_CR_IIRLP BIT(2) +#define UART_PL010_CR_SIREN BIT(1) +#define UART_PL010_CR_UARTEN BIT(0) #define UART_PL010_LCRH_WLEN_8 (3 << 5) #define UART_PL010_LCRH_WLEN_7 (2 << 5) -#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_6 BIT(5) #define UART_PL010_LCRH_WLEN_5 (0 << 5) -#define UART_PL010_LCRH_FEN (1 << 4) -#define UART_PL010_LCRH_STP2 (1 << 3) -#define UART_PL010_LCRH_EPS (1 << 2) -#define UART_PL010_LCRH_PEN (1 << 1) -#define UART_PL010_LCRH_BRK (1 << 0) +#define UART_PL010_LCRH_FEN BIT(4) +#define UART_PL010_LCRH_STP2 BIT(3) +#define UART_PL010_LCRH_EPS BIT(2) +#define UART_PL010_LCRH_PEN BIT(1) +#define UART_PL010_LCRH_BRK BIT(0) #define UART_PL010_BAUD_460800 1 @@ -91,38 +91,38 @@ struct pl01x_regs { * PL011 definitions * */ -#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_SPS BIT(7) #define UART_PL011_LCRH_WLEN_8 (3 << 5) #define UART_PL011_LCRH_WLEN_7 (2 << 5) -#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_6 BIT(5) #define UART_PL011_LCRH_WLEN_5 (0 << 5) -#define UART_PL011_LCRH_FEN (1 << 4) -#define UART_PL011_LCRH_STP2 (1 << 3) -#define UART_PL011_LCRH_EPS (1 << 2) -#define UART_PL011_LCRH_PEN (1 << 1) -#define UART_PL011_LCRH_BRK (1 << 0) +#define UART_PL011_LCRH_FEN BIT(4) +#define UART_PL011_LCRH_STP2 BIT(3) +#define UART_PL011_LCRH_EPS BIT(2) +#define UART_PL011_LCRH_PEN BIT(1) +#define UART_PL011_LCRH_BRK BIT(0) -#define UART_PL011_CR_CTSEN (1 << 15) -#define UART_PL011_CR_RTSEN (1 << 14) -#define UART_PL011_CR_OUT2 (1 << 13) -#define UART_PL011_CR_OUT1 (1 << 12) -#define UART_PL011_CR_RTS (1 << 11) -#define UART_PL011_CR_DTR (1 << 10) -#define UART_PL011_CR_RXE (1 << 9) -#define UART_PL011_CR_TXE (1 << 8) -#define UART_PL011_CR_LPE (1 << 7) -#define UART_PL011_CR_IIRLP (1 << 2) -#define UART_PL011_CR_SIREN (1 << 1) -#define UART_PL011_CR_UARTEN (1 << 0) +#define UART_PL011_CR_CTSEN BIT(15) +#define UART_PL011_CR_RTSEN BIT(14) +#define UART_PL011_CR_OUT2 BIT(13) +#define UART_PL011_CR_OUT1 BIT(12) +#define UART_PL011_CR_RTS BIT(11) +#define UART_PL011_CR_DTR BIT(10) +#define UART_PL011_CR_RXE BIT(9) +#define UART_PL011_CR_TXE BIT(8) +#define UART_PL011_CR_LPE BIT(7) +#define UART_PL011_CR_IIRLP BIT(2) +#define UART_PL011_CR_SIREN BIT(1) +#define UART_PL011_CR_UARTEN BIT(0) -#define UART_PL011_IMSC_OEIM (1 << 10) -#define UART_PL011_IMSC_BEIM (1 << 9) -#define UART_PL011_IMSC_PEIM (1 << 8) -#define UART_PL011_IMSC_FEIM (1 << 7) -#define UART_PL011_IMSC_RTIM (1 << 6) -#define UART_PL011_IMSC_TXIM (1 << 5) -#define UART_PL011_IMSC_RXIM (1 << 4) -#define UART_PL011_IMSC_DSRMIM (1 << 3) -#define UART_PL011_IMSC_DCDMIM (1 << 2) -#define UART_PL011_IMSC_CTSMIM (1 << 1) -#define UART_PL011_IMSC_RIMIM (1 << 0) +#define UART_PL011_IMSC_OEIM BIT(10) +#define UART_PL011_IMSC_BEIM BIT(9) +#define UART_PL011_IMSC_PEIM BIT(8) +#define UART_PL011_IMSC_FEIM BIT(7) +#define UART_PL011_IMSC_RTIM BIT(6) +#define UART_PL011_IMSC_TXIM BIT(5) +#define UART_PL011_IMSC_RXIM BIT(4) +#define UART_PL011_IMSC_DSRMIM BIT(3) +#define UART_PL011_IMSC_DCDMIM BIT(2) +#define UART_PL011_IMSC_CTSMIM BIT(1) +#define UART_PL011_IMSC_RIMIM BIT(0) diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index d514004..0b3b974 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #define FFUART_INDEX 1 #define STUART_INDEX 2 #elif CONFIG_CPU_PXA25X -#define UART_CLK_BASE (1 << 4) /* HWUART */ +#define UART_CLK_BASE BIT(4) /* HWUART */ #define UART_CLK_REG CKEN #define HWUART_INDEX 0 #define STUART_INDEX 1 diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 8469afd..4e532b6 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -22,10 +22,10 @@ DECLARE_GLOBAL_DATA_PTR; #define RX_FIFO_COUNT_SHIFT 0 #define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT) -#define RX_FIFO_FULL (1 << 8) +#define RX_FIFO_FULL BIT(8) #define TX_FIFO_COUNT_SHIFT 16 #define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT) -#define TX_FIFO_FULL (1 << 24) +#define TX_FIFO_FULL BIT(24) /* Information about a serial port */ struct s5p_serial_platdata { diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 3c80096..d53c0d3 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -11,7 +11,7 @@ #include #define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define RCC_APB2ENR_USART1EN (1 << 4) +#define RCC_APB2ENR_USART1EN BIT(4) #define USART_BASE STM32_USART1_BASE #define RCC_USART_ENABLE RCC_APB2ENR_USART1EN @@ -26,12 +26,12 @@ struct stm32_serial { u32 gtpr; }; -#define USART_CR1_RE (1 << 2) -#define USART_CR1_TE (1 << 3) -#define USART_CR1_UE (1 << 13) +#define USART_CR1_RE BIT(2) +#define USART_CR1_TE BIT(3) +#define USART_CR1_UE BIT(13) -#define USART_SR_FLAG_RXNE (1 << 5) -#define USART_SR_FLAG_TXE (1 << 7) +#define USART_SR_FLAG_RXNE BIT(5) +#define USART_SR_FLAG_TXE BIT(7) #define USART_BRR_F_MASK 0xF #define USART_BRR_M_SHIFT 4 diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index a4d03d9..2302117 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -29,19 +29,19 @@ struct altera_spi_regs { u32 slave_sel; }; -#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3) -#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4) -#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5) -#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6) -#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7) -#define ALTERA_SPI_STATUS_E_MSK (1 << 8) - -#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3) -#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4) -#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6) -#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7) -#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8) -#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10) +#define ALTERA_SPI_STATUS_ROE_MSK BIT(3) +#define ALTERA_SPI_STATUS_TOE_MSK BIT(4) +#define ALTERA_SPI_STATUS_TMT_MSK BIT(5) +#define ALTERA_SPI_STATUS_TRDY_MSK BIT(6) +#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) +#define ALTERA_SPI_STATUS_E_MSK BIT(8) + +#define ALTERA_SPI_CONTROL_IROE_MSK BIT(3) +#define ALTERA_SPI_CONTROL_ITOE_MSK BIT(4) +#define ALTERA_SPI_CONTROL_ITRDY_MSK BIT(6) +#define ALTERA_SPI_CONTROL_IRRDY_MSK BIT(7) +#define ALTERA_SPI_CONTROL_IE_MSK BIT(8) +#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST; diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 1538a23..5b892d2 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -15,19 +15,19 @@ #define ATMEL_SPI_VERSION 0x00fc /* Bits in CR */ -#define ATMEL_SPI_CR_SPIEN (1 << 0) -#define ATMEL_SPI_CR_SPIDIS (1 << 1) -#define ATMEL_SPI_CR_SWRST (1 << 7) -#define ATMEL_SPI_CR_LASTXFER (1 << 24) +#define ATMEL_SPI_CR_SPIEN BIT(0) +#define ATMEL_SPI_CR_SPIDIS BIT(1) +#define ATMEL_SPI_CR_SWRST BIT(7) +#define ATMEL_SPI_CR_LASTXFER BIT(24) /* Bits in MR */ -#define ATMEL_SPI_MR_MSTR (1 << 0) -#define ATMEL_SPI_MR_PS (1 << 1) -#define ATMEL_SPI_MR_PCSDEC (1 << 2) -#define ATMEL_SPI_MR_FDIV (1 << 3) -#define ATMEL_SPI_MR_MODFDIS (1 << 4) -#define ATMEL_SPI_MR_WDRBT (1 << 5) -#define ATMEL_SPI_MR_LLB (1 << 7) +#define ATMEL_SPI_MR_MSTR BIT(0) +#define ATMEL_SPI_MR_PS BIT(1) +#define ATMEL_SPI_MR_PCSDEC BIT(2) +#define ATMEL_SPI_MR_FDIV BIT(3) +#define ATMEL_SPI_MR_MODFDIS BIT(4) +#define ATMEL_SPI_MR_WDRBT BIT(5) +#define ATMEL_SPI_MR_LLB BIT(7) #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) @@ -38,25 +38,25 @@ /* Bits in TDR */ #define ATMEL_SPI_TDR_TD(x) (x) #define ATMEL_SPI_TDR_PCS(x) ((x) << 16) -#define ATMEL_SPI_TDR_LASTXFER (1 << 24) +#define ATMEL_SPI_TDR_LASTXFER BIT(24) /* Bits in SR/IER/IDR/IMR */ -#define ATMEL_SPI_SR_RDRF (1 << 0) -#define ATMEL_SPI_SR_TDRE (1 << 1) -#define ATMEL_SPI_SR_MODF (1 << 2) -#define ATMEL_SPI_SR_OVRES (1 << 3) -#define ATMEL_SPI_SR_ENDRX (1 << 4) -#define ATMEL_SPI_SR_ENDTX (1 << 5) -#define ATMEL_SPI_SR_RXBUFF (1 << 6) -#define ATMEL_SPI_SR_TXBUFE (1 << 7) -#define ATMEL_SPI_SR_NSSR (1 << 8) -#define ATMEL_SPI_SR_TXEMPTY (1 << 9) -#define ATMEL_SPI_SR_SPIENS (1 << 16) +#define ATMEL_SPI_SR_RDRF BIT(0) +#define ATMEL_SPI_SR_TDRE BIT(1) +#define ATMEL_SPI_SR_MODF BIT(2) +#define ATMEL_SPI_SR_OVRES BIT(3) +#define ATMEL_SPI_SR_ENDRX BIT(4) +#define ATMEL_SPI_SR_ENDTX BIT(5) +#define ATMEL_SPI_SR_RXBUFF BIT(6) +#define ATMEL_SPI_SR_TXBUFE BIT(7) +#define ATMEL_SPI_SR_NSSR BIT(8) +#define ATMEL_SPI_SR_TXEMPTY BIT(9) +#define ATMEL_SPI_SR_SPIENS BIT(16) /* Bits in CSRx */ -#define ATMEL_SPI_CSRx_CPOL (1 << 0) -#define ATMEL_SPI_CSRx_NCPHA (1 << 1) -#define ATMEL_SPI_CSRx_CSAAT (1 << 3) +#define ATMEL_SPI_CSRx_CPOL BIT(0) +#define ATMEL_SPI_CSRx_NCPHA BIT(1) +#define ATMEL_SPI_CSRx_CSAAT BIT(3) #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) #define ATMEL_SPI_CSRx_SCBR_MAX 0xff diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index eba01d1..8359d76 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave) ssel = bfin_read32(&bss->regs->ssel); ssel |= 1 << slave->cs; if (bss->cs_pol) - ssel |= (1 << 8) << slave->cs; + ssel |= BIT(8) << slave->cs; else - ssel &= ~((1 << 8) << slave->cs); + ssel &= ~(BIT(8) << slave->cs); bfin_write32(&bss->regs->ssel, ssel); } @@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave) u32 ssel; ssel = bfin_read32(&bss->regs->ssel); if (bss->cs_pol) - ssel &= ~((1 << 8) << slave->cs); + ssel &= ~(BIT(8) << slave->cs); else - ssel |= (1 << 8) << slave->cs; + ssel |= BIT(8) << slave->cs; /* deassert cs */ bfin_write32(&bss->regs->ssel, ssel); SSYNC(); diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 00a115f..ff375e5 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -64,10 +64,10 @@ #define CQSPI_REG_CONFIG 0x00 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 -#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) -#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) -#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) -#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) +#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7) +#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_BAUD_LSB 19 #define CQSPI_REG_CONFIG_IDLE_LSB 31 @@ -128,18 +128,18 @@ #define CQSPI_REG_IRQMASK 0x44 #define CQSPI_REG_INDIRECTRD 0x60 -#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) -#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) -#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) -#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) +#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 #define CQSPI_REG_INDIRECTRDBYTES 0x6C #define CQSPI_REG_CMDCTRL 0x90 -#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) -#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 @@ -155,10 +155,10 @@ #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF #define CQSPI_REG_INDIRECTWR 0x70 -#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) -#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) -#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) -#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) +#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 8f5c0fc..18f9786 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR; /* Bit fields in SR, 7 bits */ #define SR_MASK 0x7f /* cover 7 bits */ -#define SR_BUSY (1 << 0) -#define SR_TF_NOT_FULL (1 << 1) -#define SR_TF_EMPT (1 << 2) -#define SR_RF_NOT_EMPT (1 << 3) -#define SR_RF_FULL (1 << 4) -#define SR_TX_ERR (1 << 5) -#define SR_DCOL (1 << 6) +#define SR_BUSY BIT(0) +#define SR_TF_NOT_FULL BIT(1) +#define SR_TF_EMPT BIT(2) +#define SR_RF_NOT_EMPT BIT(3) +#define SR_RF_FULL BIT(4) +#define SR_TX_ERR BIT(5) +#define SR_DCOL BIT(6) #define RX_TIMEOUT 1000 /* timeout in ms */ diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 67f6b2d..4703f10 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step) writel(0, ®s->swap_cfg); } - assert(count && count < (1 << 16)); + assert(count && count < BIT(16)); setbits_le32(®s->ch_cfg, SPI_CH_RST); clrbits_le32(®s->ch_cfg, SPI_CH_RST); @@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen, */ bytelen = bitlen / 8; for (upto = 0; !ret && upto < bytelen; upto += todo) { - todo = min(bytelen - upto, (1 << 16) - 4); + todo = min(bytelen - upto, BIT(16) - 4); ret = spi_rx_tx(priv, todo, &din, &dout, flags); if (ret) break; diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 6476f91..924a730 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; /* fsl_dspi_platdata flags */ -#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* idle data value */ #define DSPI_IDLE_VAL 0x0 diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 375dc07..b1586d1 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -32,26 +32,26 @@ struct fsl_spi_slave { #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 -#define ESPI_EV_RNE (1 << 9) -#define ESPI_EV_TNF (1 << 8) -#define ESPI_EV_DON (1 << 14) -#define ESPI_EV_TXE (1 << 15) +#define ESPI_EV_RNE BIT(9) +#define ESPI_EV_TNF BIT(8) +#define ESPI_EV_DON BIT(14) +#define ESPI_EV_TXE BIT(15) #define ESPI_EV_RFCNT_SHIFT 24 #define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) -#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_EN BIT(31) /* Enable interface */ #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ #define ESPI_COM_CS(x) ((x) << 30) #define ESPI_COM_TRANLEN(x) ((x) << 0) -#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) -#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) -#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) -#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30) +#define ESPI_CSMODE_REV_MSB_FIRST BIT(29) +#define ESPI_CSMODE_DIV16 BIT(28) #define ESPI_CSMODE_PM(x) ((x) << 24) -#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20) #define ESPI_CSMODE_LEN(x) ((x) << 16) #define ESPI_CSMODE_CSBEF(x) ((x) << 12) #define ESPI_CSMODE_CSAFT(x) ((x) << 8) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 868df5f..e1a0ec9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* fsl_qspi_platdata flags */ -#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0) +#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) /* default SCK frequency, unit: HZ */ #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 @@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) /* Enable the module again (enable the DDR too) */ reg |= QSPI_MCR_DDR_EN_MASK; /* Enable bit 29 for imx6sx */ - reg |= (1 << 29); + reg |= BIT(29); qspi_write32(priv->flags, ®s->mcr, reg); } diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c index c7d6480..5a08abe 100644 --- a/drivers/spi/ftssp010_spi.c +++ b/drivers/spi/ftssp010_spi.c @@ -47,24 +47,24 @@ struct ftssp010_regs { /* Control Register 0 */ #define CR0_FFMT_MASK (7 << 12) #define CR0_FFMT_SSP (0 << 12) -#define CR0_FFMT_SPI (1 << 12) +#define CR0_FFMT_SPI BIT(12) #define CR0_FFMT_MICROWIRE (2 << 12) #define CR0_FFMT_I2S (3 << 12) #define CR0_FFMT_AC97 (4 << 12) -#define CR0_FLASH (1 << 11) +#define CR0_FLASH BIT(11) #define CR0_FSDIST(x) (((x) & 0x03) << 8) -#define CR0_LOOP (1 << 7) /* loopback mode */ -#define CR0_LSB (1 << 6) /* LSB */ -#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ -#define CR0_FSJUSTIFY (1 << 4) +#define CR0_LOOP BIT(7) /* loopback mode */ +#define CR0_LSB BIT(6) /* LSB */ +#define CR0_FSPO BIT(5) /* fs atcive low (I2S only) */ +#define CR0_FSJUSTIFY BIT(4) #define CR0_OPM_SLAVE (0 << 2) #define CR0_OPM_MASTER (3 << 2) #define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ #define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ -#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ +#define CR0_OPM_I2S_SLST BIT(2) /* slave stereo mode */ #define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ -#define CR0_SCLKPO (1 << 1) /* clock polarity */ -#define CR0_SCLKPH (1 << 0) /* clock phase */ +#define CR0_SCLKPO BIT(1) /* clock polarity */ +#define CR0_SCLKPH BIT(0) /* clock phase */ /* Control Register 1 */ #define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ @@ -73,19 +73,19 @@ struct ftssp010_regs { /* Control Register 2 */ #define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ -#define CR2_FS (1 << 9) /* CS/FS signal level */ -#define CR2_TXEN (1 << 8) /* tx enable */ -#define CR2_RXEN (1 << 7) /* rx enable */ -#define CR2_RESET (1 << 6) /* chip reset */ -#define CR2_TXFC (1 << 3) /* tx fifo Clear */ -#define CR2_RXFC (1 << 2) /* rx fifo Clear */ -#define CR2_TXDOE (1 << 1) /* tx data output enable */ -#define CR2_EN (1 << 0) /* chip enable */ +#define CR2_FS BIT(9) /* CS/FS signal level */ +#define CR2_TXEN BIT(8) /* tx enable */ +#define CR2_RXEN BIT(7) /* rx enable */ +#define CR2_RESET BIT(6) /* chip reset */ +#define CR2_TXFC BIT(3) /* tx fifo Clear */ +#define CR2_RXFC BIT(2) /* rx fifo Clear */ +#define CR2_TXDOE BIT(1) /* tx data output enable */ +#define CR2_EN BIT(0) /* chip enable */ /* Status Register */ -#define SR_RFF (1 << 0) /* rx fifo full */ -#define SR_TFNF (1 << 1) /* tx fifo not full */ -#define SR_BUSY (1 << 2) /* chip busy */ +#define SR_RFF BIT(0) /* rx fifo full */ +#define SR_TFNF BIT(1) /* tx fifo not full */ +#define SR_BUSY BIT(2) /* chip busy */ #define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ #define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ @@ -93,11 +93,11 @@ struct ftssp010_regs { #define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ #define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ #define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ -#define FEAR_AC97 (1 << 24) -#define FEAR_I2S (1 << 25) -#define FEAR_SPI_MWR (1 << 26) -#define FEAR_SSP (1 << 27) -#define FEAR_SPDIF (1 << 28) +#define FEAR_AC97 BIT(24) +#define FEAR_I2S BIT(25) +#define FEAR_SPI_MWR BIT(26) +#define FEAR_SSP BIT(27) +#define FEAR_SPDIF BIT(28) /* FTGPIO010 chip registers */ struct ftgpio010_regs { diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 50354fd..feffb08 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -689,13 +689,13 @@ static int ich_spi_probe(struct udevice *bus) ich9_spi = priv->base; bios_cntl = ich_readb(priv, ich9_spi->bcr); - bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ bios_cntl |= 1; /* Write Protect Disable (WPD) */ ich_writeb(priv, bios_cntl, ich9_spi->bcr); } else { pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); if (plat->ich_version == 9) - bios_cntl &= ~(1 << 5); + bios_cntl &= ~BIT(5); pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); } diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 0d59c36..00cbcbf 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -55,7 +55,7 @@ void spi_init(void) * some registers */ spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; - spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8 + spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8 (16.67MHz typ.) */ spi->event = 0xffffffff; /* Clear all SPI events */ spi->mask = 0x00000000; /* Mask all SPI interrupts */ diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index ab7cd84..269a5c7 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -52,40 +52,40 @@ struct mcspi { /* per-register bitmasks */ #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0) -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) +#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0) +#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) -#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0) -#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2) -#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3) +#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) +#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) +#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) -#define OMAP3_MCSPI_CHCONF_PHA (1 << 0) -#define OMAP3_MCSPI_CHCONF_POL (1 << 1) +#define OMAP3_MCSPI_CHCONF_PHA BIT(0) +#define OMAP3_MCSPI_CHCONF_POL BIT(1) #define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) -#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6) +#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) #define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7) #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) #define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12) -#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14) -#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15) -#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16) -#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17) -#define OMAP3_MCSPI_CHCONF_IS (1 << 18) -#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19) -#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20) - -#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0) -#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1) -#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2) - -#define OMAP3_MCSPI_CHCTRL_EN (1 << 0) +#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) +#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) +#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) +#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) +#define OMAP3_MCSPI_CHCONF_IS BIT(18) +#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) +#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) + +#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) +#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) +#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) + +#define OMAP3_MCSPI_CHCTRL_EN BIT(0) #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) -#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0) +#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) struct omap3_spi_slave { struct spi_slave slave; diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 77ede6b..7209e1d 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -21,19 +21,19 @@ #define SPPCR_IO3FV 0x04 #define SPPCR_IO2FV 0x02 #define SPPCR_IO1FV 0x01 -#define SPBDCR_RXBC0 (1 << 0) -#define SPCMD_SCKDEN (1 << 15) -#define SPCMD_SLNDEN (1 << 14) -#define SPCMD_SPNDEN (1 << 13) -#define SPCMD_SSLKP (1 << 7) -#define SPCMD_BRDV0 (1 << 2) +#define SPBDCR_RXBC0 BIT(0) +#define SPCMD_SCKDEN BIT(15) +#define SPCMD_SLNDEN BIT(14) +#define SPCMD_SPNDEN BIT(13) +#define SPCMD_SSLKP BIT(7) +#define SPCMD_BRDV0 BIT(2) #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ SPCMD_SPNDEN | SPCMD_SSLKP | \ SPCMD_BRDV0 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ SPCMD_BRDV0 -#define SPBFCR_TXRST (1 << 7) -#define SPBFCR_RXRST (1 << 6) +#define SPBFCR_TXRST BIT(7) +#define SPBFCR_RXRST BIT(6) /* SH QSPI register set */ struct sh_qspi_regs { diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 4bec663..61a0ecf 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -33,54 +33,54 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND1 */ -#define SPI_CMD1_GO (1 << 31) -#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_GO BIT(31) +#define SPI_CMD1_M_S BIT(30) #define SPI_CMD1_MODE_MASK 0x3 #define SPI_CMD1_MODE_SHIFT 28 #define SPI_CMD1_CS_SEL_MASK 0x3 #define SPI_CMD1_CS_SEL_SHIFT 26 -#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) -#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) -#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) -#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) -#define SPI_CMD1_CS_SW_HW (1 << 21) -#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) +#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) +#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) +#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) +#define SPI_CMD1_CS_SW_HW BIT(21) +#define SPI_CMD1_CS_SW_VAL BIT(20) #define SPI_CMD1_IDLE_SDA_MASK 0x3 #define SPI_CMD1_IDLE_SDA_SHIFT 18 -#define SPI_CMD1_BIDIR (1 << 17) -#define SPI_CMD1_LSBI_FE (1 << 16) -#define SPI_CMD1_LSBY_FE (1 << 15) -#define SPI_CMD1_BOTH_EN_BIT (1 << 14) -#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) -#define SPI_CMD1_RX_EN (1 << 12) -#define SPI_CMD1_TX_EN (1 << 11) -#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIDIR BIT(17) +#define SPI_CMD1_LSBI_FE BIT(16) +#define SPI_CMD1_LSBY_FE BIT(15) +#define SPI_CMD1_BOTH_EN_BIT BIT(14) +#define SPI_CMD1_BOTH_EN_BYTE BIT(13) +#define SPI_CMD1_RX_EN BIT(12) +#define SPI_CMD1_TX_EN BIT(11) +#define SPI_CMD1_PACKED BIT(5) #define SPI_CMD1_BIT_LEN_MASK 0x1F #define SPI_CMD1_BIT_LEN_SHIFT 0 /* COMMAND2 */ -#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) -#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) /* TRANSFER STATUS */ -#define SPI_XFER_STS_RDY (1 << 30) +#define SPI_XFER_STS_RDY BIT(30) /* FIFO STATUS */ -#define SPI_FIFO_STS_CS_INACTIVE (1 << 31) -#define SPI_FIFO_STS_FRAME_END (1 << 30) -#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) -#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) -#define SPI_FIFO_STS_ERR (1 << 8) -#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) -#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) -#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) -#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) -#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) -#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) -#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) -#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) +#define SPI_FIFO_STS_CS_INACTIVE BIT(31) +#define SPI_FIFO_STS_FRAME_END BIT(30) +#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) +#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) +#define SPI_FIFO_STS_ERR BIT(8) +#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) +#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) +#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) +#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) +#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) +#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) +#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) +#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 82c1b84..4d3f1e4 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -20,37 +20,37 @@ DECLARE_GLOBAL_DATA_PTR; -#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_GO BIT(30) #define SPI_CMD_ACTIVE_SCLK_SHIFT 26 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_CK_SDA BIT(21) #define SPI_CMD_ACTIVE_SDA_SHIFT 18 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_CS_POL BIT(16) +#define SPI_CMD_TXEN BIT(15) +#define SPI_CMD_RXEN BIT(14) +#define SPI_CMD_CS_VAL BIT(13) +#define SPI_CMD_CS_SOFT BIT(12) +#define SPI_CMD_CS_DELAY BIT(9) +#define SPI_CMD_CS3_EN BIT(8) +#define SPI_CMD_CS2_EN BIT(7) +#define SPI_CMD_CS1_EN BIT(6) +#define SPI_CMD_CS0_EN BIT(5) +#define SPI_CMD_BIT_LENGTH BIT(4) #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) +#define SPI_STAT_BSY BIT(31) +#define SPI_STAT_RDY BIT(30) +#define SPI_STAT_RXF_FLUSH BIT(29) +#define SPI_STAT_TXF_FLUSH BIT(28) +#define SPI_STAT_RXF_UNR BIT(27) +#define SPI_STAT_TXF_OVF BIT(26) +#define SPI_STAT_RXF_EMPTY BIT(25) +#define SPI_STAT_RXF_FULL BIT(24) +#define SPI_STAT_TXF_EMPTY BIT(23) +#define SPI_STAT_TXF_FULL BIT(22) +#define SPI_STAT_SEL_TXRX_N BIT(16) +#define SPI_STAT_CUR_BLKCNT BIT(15) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index f6fb89b..674c7ab 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -33,40 +33,40 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND */ -#define SLINK_CMD_ENB (1 << 31) -#define SLINK_CMD_GO (1 << 30) -#define SLINK_CMD_M_S (1 << 28) -#define SLINK_CMD_CK_SDA (1 << 21) -#define SLINK_CMD_CS_POL (1 << 13) -#define SLINK_CMD_CS_VAL (1 << 12) -#define SLINK_CMD_CS_SOFT (1 << 11) -#define SLINK_CMD_BIT_LENGTH (1 << 4) +#define SLINK_CMD_ENB BIT(31) +#define SLINK_CMD_GO BIT(30) +#define SLINK_CMD_M_S BIT(28) +#define SLINK_CMD_CK_SDA BIT(21) +#define SLINK_CMD_CS_POL BIT(13) +#define SLINK_CMD_CS_VAL BIT(12) +#define SLINK_CMD_CS_SOFT BIT(11) +#define SLINK_CMD_BIT_LENGTH BIT(4) #define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F /* COMMAND2 */ -#define SLINK_CMD2_TXEN (1 << 30) -#define SLINK_CMD2_RXEN (1 << 31) -#define SLINK_CMD2_SS_EN (1 << 18) +#define SLINK_CMD2_TXEN BIT(30) +#define SLINK_CMD2_RXEN BIT(31) +#define SLINK_CMD2_SS_EN BIT(18) #define SLINK_CMD2_SS_EN_SHIFT 18 #define SLINK_CMD2_SS_EN_MASK 0x000C0000 -#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) +#define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) /* STATUS */ -#define SLINK_STAT_BSY (1 << 31) -#define SLINK_STAT_RDY (1 << 30) -#define SLINK_STAT_ERR (1 << 29) -#define SLINK_STAT_RXF_FLUSH (1 << 27) -#define SLINK_STAT_TXF_FLUSH (1 << 26) -#define SLINK_STAT_RXF_OVF (1 << 25) -#define SLINK_STAT_TXF_UNR (1 << 24) -#define SLINK_STAT_RXF_EMPTY (1 << 23) -#define SLINK_STAT_RXF_FULL (1 << 22) -#define SLINK_STAT_TXF_EMPTY (1 << 21) -#define SLINK_STAT_TXF_FULL (1 << 20) -#define SLINK_STAT_TXF_OVF (1 << 19) -#define SLINK_STAT_RXF_UNR (1 << 18) -#define SLINK_STAT_CUR_BLKCNT (1 << 15) +#define SLINK_STAT_BSY BIT(31) +#define SLINK_STAT_RDY BIT(30) +#define SLINK_STAT_ERR BIT(29) +#define SLINK_STAT_RXF_FLUSH BIT(27) +#define SLINK_STAT_TXF_FLUSH BIT(26) +#define SLINK_STAT_RXF_OVF BIT(25) +#define SLINK_STAT_TXF_UNR BIT(24) +#define SLINK_STAT_RXF_EMPTY BIT(23) +#define SLINK_STAT_RXF_FULL BIT(22) +#define SLINK_STAT_TXF_EMPTY BIT(21) +#define SLINK_STAT_TXF_FULL BIT(20) +#define SLINK_STAT_TXF_OVF BIT(19) +#define SLINK_STAT_RXF_UNR BIT(18) +#define SLINK_STAT_CUR_BLKCNT BIT(15) /* STATUS2 */ -#define SLINK_STAT2_RXF_FULL_CNT (1 << 16) -#define SLINK_STAT2_TXF_FULL_CNT (1 << 0) +#define SLINK_STAT2_RXF_FULL_CNT BIT(16) +#define SLINK_STAT2_TXF_FULL_CNT BIT(0) #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 3356c0f..ca3acfd 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -18,13 +18,13 @@ #define QSPI_TIMEOUT 2000000 #define QSPI_FCLK 192000000 /* clock control */ -#define QSPI_CLK_EN (1 << 31) +#define QSPI_CLK_EN BIT(31) #define QSPI_CLK_DIV_MAX 0xffff /* command */ #define QSPI_EN_CS(n) (n << 28) #define QSPI_WLEN(n) ((n-1) << 19) -#define QSPI_3_PIN (1 << 18) -#define QSPI_RD_SNGL (1 << 16) +#define QSPI_3_PIN BIT(18) +#define QSPI_RD_SNGL BIT(16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) @@ -34,8 +34,8 @@ #define QSPI_CSPOL(n) (1 << (1 + n*8)) #define QSPI_CKPOL(n) (1 << (n*8)) /* status */ -#define QSPI_WC (1 << 1) -#define QSPI_BUSY (1 << 0) +#define QSPI_WC BIT(1) +#define QSPI_BUSY BIT(0) #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 diff --git a/drivers/spi/xilinx_spi.h b/drivers/spi/xilinx_spi.h index ce7d82c..d84cd28 100644 --- a/drivers/spi/xilinx_spi.h +++ b/drivers/spi/xilinx_spi.h @@ -49,52 +49,52 @@ struct xilinx_spi_reg { }; /* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ -#define DGIER_GIE (1 << 31) +#define DGIER_GIE BIT(31) /* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ -#define IPISR_DRR_NOT_EMPTY (1 << 8) -#define IPISR_SLAVE_SELECT (1 << 7) -#define IPISR_TXF_HALF_EMPTY (1 << 6) -#define IPISR_DRR_OVERRUN (1 << 5) -#define IPISR_DRR_FULL (1 << 4) -#define IPISR_DTR_UNDERRUN (1 << 3) -#define IPISR_DTR_EMPTY (1 << 2) -#define IPISR_SLAVE_MODF (1 << 1) -#define IPISR_MODF (1 << 0) +#define IPISR_DRR_NOT_EMPTY BIT(8) +#define IPISR_SLAVE_SELECT BIT(7) +#define IPISR_TXF_HALF_EMPTY BIT(6) +#define IPISR_DRR_OVERRUN BIT(5) +#define IPISR_DRR_FULL BIT(4) +#define IPISR_DTR_UNDERRUN BIT(3) +#define IPISR_DTR_EMPTY BIT(2) +#define IPISR_SLAVE_MODF BIT(1) +#define IPISR_MODF BIT(0) /* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ -#define IPIER_DRR_NOT_EMPTY (1 << 8) -#define IPIER_SLAVE_SELECT (1 << 7) -#define IPIER_TXF_HALF_EMPTY (1 << 6) -#define IPIER_DRR_OVERRUN (1 << 5) -#define IPIER_DRR_FULL (1 << 4) -#define IPIER_DTR_UNDERRUN (1 << 3) -#define IPIER_DTR_EMPTY (1 << 2) -#define IPIER_SLAVE_MODF (1 << 1) -#define IPIER_MODF (1 << 0) +#define IPIER_DRR_NOT_EMPTY BIT(8) +#define IPIER_SLAVE_SELECT BIT(7) +#define IPIER_TXF_HALF_EMPTY BIT(6) +#define IPIER_DRR_OVERRUN BIT(5) +#define IPIER_DRR_FULL BIT(4) +#define IPIER_DTR_UNDERRUN BIT(3) +#define IPIER_DTR_EMPTY BIT(2) +#define IPIER_SLAVE_MODF BIT(1) +#define IPIER_MODF BIT(0) /* Softare Reset Register (srr), [1] p9, [2] p8 */ #define SRR_RESET_CODE 0x0000000A /* SPI Control Register (spicr), [1] p9, [2] p8 */ -#define SPICR_LSB_FIRST (1 << 9) -#define SPICR_MASTER_INHIBIT (1 << 8) -#define SPICR_MANUAL_SS (1 << 7) -#define SPICR_RXFIFO_RESEST (1 << 6) -#define SPICR_TXFIFO_RESEST (1 << 5) -#define SPICR_CPHA (1 << 4) -#define SPICR_CPOL (1 << 3) -#define SPICR_MASTER_MODE (1 << 2) -#define SPICR_SPE (1 << 1) -#define SPICR_LOOP (1 << 0) +#define SPICR_LSB_FIRST BIT(9) +#define SPICR_MASTER_INHIBIT BIT(8) +#define SPICR_MANUAL_SS BIT(7) +#define SPICR_RXFIFO_RESEST BIT(6) +#define SPICR_TXFIFO_RESEST BIT(5) +#define SPICR_CPHA BIT(4) +#define SPICR_CPOL BIT(3) +#define SPICR_MASTER_MODE BIT(2) +#define SPICR_SPE BIT(1) +#define SPICR_LOOP BIT(0) /* SPI Status Register (spisr), [1] p11, [2] p10 */ -#define SPISR_SLAVE_MODE_SELECT (1 << 5) -#define SPISR_MODF (1 << 4) -#define SPISR_TX_FULL (1 << 3) -#define SPISR_TX_EMPTY (1 << 2) -#define SPISR_RX_FULL (1 << 1) -#define SPISR_RX_EMPTY (1 << 0) +#define SPISR_SLAVE_MODE_SELECT BIT(5) +#define SPISR_MODF BIT(4) +#define SPISR_TX_FULL BIT(3) +#define SPISR_TX_EMPTY BIT(2) +#define SPISR_RX_FULL BIT(1) +#define SPISR_RX_EMPTY BIT(0) /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ #define SPIDTR_8BIT_MASK (0xff << 0) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index e9129da..ff1ec6a 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -14,17 +14,17 @@ #include /* zynq spi register bit masks ZYNQ_SPI___MASK */ -#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ -#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ +#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ #define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ #define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ -#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ -#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ -#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ -#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ -#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ +#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ +#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ +#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ -#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ +#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_FIFO_DEPTH 128 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 0bd9cfd..9f80876 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -28,10 +28,10 @@ #define TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) -#define TEMPSENSE0_FINISHED (1 << 2) -#define TEMPSENSE0_MEASURE_TEMP (1 << 1) -#define TEMPSENSE0_POWER_DOWN (1 << 0) -#define MISC0_REFTOP_SELBIASOFF (1 << 3) +#define TEMPSENSE0_FINISHED BIT(2) +#define TEMPSENSE0_MEASURE_TEMP BIT(1) +#define TEMPSENSE0_POWER_DOWN BIT(0) +#define MISC0_REFTOP_SELBIASOFF BIT(3) #define TEMPSENSE1_MEASURE_FREQ 0xffff static int read_cpu_temperature(struct udevice *dev) diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index d09f8ce..aa01b18 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -45,20 +45,20 @@ static struct tpm_locality *lpc_tpm_dev = (struct tpm_locality *)CONFIG_TPM_TIS_BASE_ADDRESS; /* Some registers' bit field definitions */ -#define TIS_STS_VALID (1 << 7) /* 0x80 */ -#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ -#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ -#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ -#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ -#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ - -#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ -#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ -#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ -#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ -#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ -#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ -#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ +#define TIS_STS_VALID BIT(7) /* 0x80 */ +#define TIS_STS_COMMAND_READY BIT(6) /* 0x40 */ +#define TIS_STS_TPM_GO BIT(5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE BIT(4) /* 0x10 */ +#define TIS_STS_EXPECT BIT(3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY BIT(1) /* 0x02 */ + +#define TIS_ACCESS_TPM_REG_VALID_STS BIT(7) /* 0x80 */ +#define TIS_ACCESS_ACTIVE_LOCALITY BIT(5) /* 0x20 */ +#define TIS_ACCESS_BEEN_SEIZED BIT(4) /* 0x10 */ +#define TIS_ACCESS_SEIZE BIT(3) /* 0x08 */ +#define TIS_ACCESS_PENDING_REQUEST BIT(2) /* 0x04 */ +#define TIS_ACCESS_REQUEST_USE BIT(1) /* 0x02 */ +#define TIS_ACCESS_TPM_ESTABLISHMENT BIT(0) /* 0x01 */ #define TIS_STS_BURST_COUNT_MASK (0xffff) #define TIS_STS_BURST_COUNT_SHIFT (8) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 72d2fcd..7f8d9af 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -138,7 +138,7 @@ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) -#define DWC3_GCTL_U2RSTECN (1 << 16) +#define DWC3_GCTL_U2RSTECN BIT(16) #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) #define DWC3_GCTL_CLK_BUS (0) #define DWC3_GCTL_CLK_PIPE (1) @@ -151,30 +151,30 @@ #define DWC3_GCTL_PRTCAP_DEVICE 2 #define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_CORESOFTRESET (1 << 11) -#define DWC3_GCTL_SOFITPSYNC (1 << 10) +#define DWC3_GCTL_CORESOFTRESET BIT(11) +#define DWC3_GCTL_SOFITPSYNC BIT(10) #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) -#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +#define DWC3_GCTL_DISSCRAMBLE BIT(3) +#define DWC3_GCTL_U2EXIT_LFPS BIT(2) +#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) +#define DWC3_GCTL_DSBLCLKGTNG BIT(0) /* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) -#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) +#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) /* Global USB3 PIPE Control Register */ -#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) -#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) -#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) +#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) +#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) -#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) -#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) -#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) -#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) +#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) +#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) +#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) +#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) @@ -183,7 +183,7 @@ #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) /* Global Event Size Registers */ -#define DWC3_GEVNTSIZ_INTMASK (1 << 31) +#define DWC3_GEVNTSIZ_INTMASK BIT(31) #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) /* Global HWPARAMS1 Register */ @@ -212,7 +212,7 @@ #define DWC3_MAX_HIBER_SCRATCHBUFS 15 /* Global HWPARAMS6 Register */ -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7) /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) @@ -221,21 +221,21 @@ #define DWC3_DCFG_SPEED_MASK (7 << 0) #define DWC3_DCFG_SUPERSPEED (4 << 0) #define DWC3_DCFG_HIGHSPEED (0 << 0) -#define DWC3_DCFG_FULLSPEED2 (1 << 0) +#define DWC3_DCFG_FULLSPEED2 BIT(0) #define DWC3_DCFG_LOWSPEED (2 << 0) #define DWC3_DCFG_FULLSPEED1 (3 << 0) -#define DWC3_DCFG_LPM_CAP (1 << 22) +#define DWC3_DCFG_LPM_CAP BIT(22) /* Device Control Register */ -#define DWC3_DCTL_RUN_STOP (1 << 31) -#define DWC3_DCTL_CSFTRST (1 << 30) -#define DWC3_DCTL_LSFTRST (1 << 29) +#define DWC3_DCTL_RUN_STOP BIT(31) +#define DWC3_DCTL_CSFTRST BIT(30) +#define DWC3_DCTL_LSFTRST BIT(29) #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) -#define DWC3_DCTL_APPL1RES (1 << 23) +#define DWC3_DCTL_APPL1RES BIT(23) /* These apply for core versions 1.87a and earlier */ #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) @@ -250,15 +250,15 @@ #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) -#define DWC3_DCTL_KEEP_CONNECT (1 << 19) -#define DWC3_DCTL_L1_HIBER_EN (1 << 18) -#define DWC3_DCTL_CRS (1 << 17) -#define DWC3_DCTL_CSS (1 << 16) +#define DWC3_DCTL_KEEP_CONNECT BIT(19) +#define DWC3_DCTL_L1_HIBER_EN BIT(18) +#define DWC3_DCTL_CRS BIT(17) +#define DWC3_DCTL_CSS BIT(16) -#define DWC3_DCTL_INITU2ENA (1 << 12) -#define DWC3_DCTL_ACCEPTU2ENA (1 << 11) -#define DWC3_DCTL_INITU1ENA (1 << 10) -#define DWC3_DCTL_ACCEPTU1ENA (1 << 9) +#define DWC3_DCTL_INITU2ENA BIT(12) +#define DWC3_DCTL_ACCEPTU2ENA BIT(11) +#define DWC3_DCTL_INITU1ENA BIT(10) +#define DWC3_DCTL_ACCEPTU1ENA BIT(9) #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) @@ -273,36 +273,36 @@ #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) /* Device Event Enable Register */ -#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) -#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) -#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) -#define DWC3_DEVTEN_ERRTICERREN (1 << 9) -#define DWC3_DEVTEN_SOFEN (1 << 7) -#define DWC3_DEVTEN_EOPFEN (1 << 6) -#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) -#define DWC3_DEVTEN_WKUPEVTEN (1 << 4) -#define DWC3_DEVTEN_ULSTCNGEN (1 << 3) -#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) -#define DWC3_DEVTEN_USBRSTEN (1 << 1) -#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) +#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) +#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) +#define DWC3_DEVTEN_CMDCMPLTEN BIT(10) +#define DWC3_DEVTEN_ERRTICERREN BIT(9) +#define DWC3_DEVTEN_SOFEN BIT(7) +#define DWC3_DEVTEN_EOPFEN BIT(6) +#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) +#define DWC3_DEVTEN_WKUPEVTEN BIT(4) +#define DWC3_DEVTEN_ULSTCNGEN BIT(3) +#define DWC3_DEVTEN_CONNECTDONEEN BIT(2) +#define DWC3_DEVTEN_USBRSTEN BIT(1) +#define DWC3_DEVTEN_DISCONNEVTEN BIT(0) /* Device Status Register */ -#define DWC3_DSTS_DCNRD (1 << 29) +#define DWC3_DSTS_DCNRD BIT(29) /* This applies for core versions 1.87a and earlier */ -#define DWC3_DSTS_PWRUPREQ (1 << 24) +#define DWC3_DSTS_PWRUPREQ BIT(24) /* These apply for core versions 1.94a and later */ -#define DWC3_DSTS_RSS (1 << 25) -#define DWC3_DSTS_SSS (1 << 24) +#define DWC3_DSTS_RSS BIT(25) +#define DWC3_DSTS_SSS BIT(24) -#define DWC3_DSTS_COREIDLE (1 << 23) -#define DWC3_DSTS_DEVCTRLHLT (1 << 22) +#define DWC3_DSTS_COREIDLE BIT(23) +#define DWC3_DSTS_DEVCTRLHLT BIT(22) #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) -#define DWC3_DSTS_RXFIFOEMPTY (1 << 17) +#define DWC3_DSTS_RXFIFOEMPTY BIT(17) #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) @@ -311,7 +311,7 @@ #define DWC3_DSTS_SUPERSPEED (4 << 0) #define DWC3_DSTS_HIGHSPEED (0 << 0) -#define DWC3_DSTS_FULLSPEED2 (1 << 0) +#define DWC3_DSTS_FULLSPEED2 BIT(0) #define DWC3_DSTS_LOWSPEED (2 << 0) #define DWC3_DSTS_FULLSPEED1 (3 << 0) @@ -330,25 +330,25 @@ #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) -#define DWC3_DGCMD_CMDACT (1 << 10) -#define DWC3_DGCMD_CMDIOC (1 << 8) +#define DWC3_DGCMD_CMDACT BIT(10) +#define DWC3_DGCMD_CMDIOC BIT(8) /* Device Generic Command Parameter Register */ -#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) +#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) -#define DWC3_DGCMDPAR_TX_FIFO (1 << 5) +#define DWC3_DGCMDPAR_TX_FIFO BIT(5) #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) -#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) +#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) /* Device Endpoint Command Register */ #define DWC3_DEPCMD_PARAM_SHIFT 16 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) -#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) -#define DWC3_DEPCMD_CMDACT (1 << 10) -#define DWC3_DEPCMD_CMDIOC (1 << 8) +#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) +#define DWC3_DEPCMD_CMDACT BIT(10) +#define DWC3_DEPCMD_CMDIOC BIT(8) #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) @@ -399,8 +399,8 @@ struct dwc3_event_buffer { struct dwc3 *dwc; }; -#define DWC3_EP_FLAG_STALLED (1 << 0) -#define DWC3_EP_FLAG_WEDGED (1 << 1) +#define DWC3_EP_FLAG_STALLED BIT(0) +#define DWC3_EP_FLAG_WEDGED BIT(1) #define DWC3_EP_DIRECTION_TX true #define DWC3_EP_DIRECTION_RX false @@ -444,15 +444,15 @@ struct dwc3_ep { u32 saved_state; unsigned flags; -#define DWC3_EP_ENABLED (1 << 0) -#define DWC3_EP_STALL (1 << 1) -#define DWC3_EP_WEDGE (1 << 2) -#define DWC3_EP_BUSY (1 << 4) -#define DWC3_EP_PENDING_REQUEST (1 << 5) -#define DWC3_EP_MISSED_ISOC (1 << 6) +#define DWC3_EP_ENABLED BIT(0) +#define DWC3_EP_STALL BIT(1) +#define DWC3_EP_WEDGE BIT(2) +#define DWC3_EP_BUSY BIT(4) +#define DWC3_EP_PENDING_REQUEST BIT(5) +#define DWC3_EP_MISSED_ISOC BIT(6) /* This last one is specific to EP0 */ -#define DWC3_EP0_DIR_IN (1 << 31) +#define DWC3_EP0_DIR_IN BIT(31) unsigned current_trb; @@ -518,13 +518,13 @@ enum dwc3_link_state { #define DWC3_TRB_STS_XFER_IN_PROG 4 /* TRB Control */ -#define DWC3_TRB_CTRL_HWO (1 << 0) -#define DWC3_TRB_CTRL_LST (1 << 1) -#define DWC3_TRB_CTRL_CHN (1 << 2) -#define DWC3_TRB_CTRL_CSP (1 << 3) +#define DWC3_TRB_CTRL_HWO BIT(0) +#define DWC3_TRB_CTRL_LST BIT(1) +#define DWC3_TRB_CTRL_CHN BIT(2) +#define DWC3_TRB_CTRL_CSP BIT(3) #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) -#define DWC3_TRB_CTRL_ISP_IMI (1 << 10) -#define DWC3_TRB_CTRL_IOC (1 << 11) +#define DWC3_TRB_CTRL_ISP_IMI BIT(10) +#define DWC3_TRB_CTRL_IOC BIT(11) #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) @@ -885,13 +885,13 @@ struct dwc3_event_depevt { u32 status:4; /* Within XferNotReady */ -#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) +#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) /* Within XferComplete */ -#define DEPEVT_STATUS_BUSERR (1 << 0) -#define DEPEVT_STATUS_SHORT (1 << 1) -#define DEPEVT_STATUS_IOC (1 << 2) -#define DEPEVT_STATUS_LST (1 << 3) +#define DEPEVT_STATUS_BUSERR BIT(0) +#define DEPEVT_STATUS_SHORT BIT(1) +#define DEPEVT_STATUS_IOC BIT(2) +#define DEPEVT_STATUS_LST BIT(3) /* Stream event only */ #define DEPEVT_STREAMEVT_FOUND 1 diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 46af109..9c6d0b9 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -71,40 +71,40 @@ #define USBOTGSS_DEBUG_OFFSET 0x0600 /* SYSCONFIG REGISTER */ -#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) +#define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16) /* IRQ_EOI REGISTER */ -#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) +#define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0) /* IRQS0 BITS */ -#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) +#define USBOTGSS_IRQO_COREIRQ_ST BIT(0) /* IRQMISC BITS */ -#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) -#define USBOTGSS_IRQMISC_OEVT (1 << 16) -#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) -#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) -#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) -#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) -#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) -#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) -#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) -#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) +#define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17) +#define USBOTGSS_IRQMISC_OEVT BIT(16) +#define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13) +#define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12) +#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11) +#define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8) +#define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5) +#define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4) +#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3) +#define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0) /* UTMI_OTG_CTRL REGISTER */ -#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) -#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) -#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) -#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) +#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS BIT(5) +#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS BIT(4) +#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS BIT(3) +#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP BIT(0) /* UTMI_OTG_STATUS REGISTER */ -#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) -#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) -#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) -#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) -#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) -#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) -#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) +#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31) +#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9) +#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8) +#define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4) +#define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3) +#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2) +#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1) struct dwc3_omap { struct device *dev; diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index c7db219..cb1af60 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -29,16 +29,16 @@ struct dwc3; /* DEPCFG parameter 1 */ #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) -#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8) -#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) -#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10) -#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11) -#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13) +#define DWC3_DEPCFG_XFER_COMPLETE_EN BIT(8) +#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9) +#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10) +#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11) +#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13) #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) -#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24) +#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24) #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) -#define DWC3_DEPCFG_BULK_BASED (1 << 30) -#define DWC3_DEPCFG_FIFO_BASED (1 << 31) +#define DWC3_DEPCFG_BULK_BASED BIT(30) +#define DWC3_DEPCFG_FIFO_BASED BIT(31) /* DEPCFG parameter 0 */ #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) @@ -47,10 +47,10 @@ struct dwc3; #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) /* This applies for core versions earlier than 1.94a */ -#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31) +#define DWC3_DEPCFG_IGN_SEQ_NUM BIT(31) /* These apply for core versions 1.94a and later */ #define DWC3_DEPCFG_ACTION_INIT (0 << 30) -#define DWC3_DEPCFG_ACTION_RESTORE (1 << 30) +#define DWC3_DEPCFG_ACTION_RESTORE BIT(30) #define DWC3_DEPCFG_ACTION_MODIFY (2 << 30) /* DEPXFERCFG parameter 0 */ diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 94dfe85..49e895d 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -20,14 +20,14 @@ #define AX88179_EEPROM_MAGIC 0x17900b95 #define AX_MCAST_FLTSIZE 8 #define AX_MAX_MCAST 64 -#define AX_INT_PPLS_LINK (1 << 16) +#define AX_INT_PPLS_LINK BIT(16) #define AX_RXHDR_L4_TYPE_MASK 0x1c #define AX_RXHDR_L4_TYPE_UDP 4 #define AX_RXHDR_L4_TYPE_TCP 16 #define AX_RXHDR_L3CSUM_ERR 2 #define AX_RXHDR_L4CSUM_ERR 1 -#define AX_RXHDR_CRC_ERR (1 << 29) -#define AX_RXHDR_DROP_ERR (1 << 31) +#define AX_RXHDR_CRC_ERR BIT(29) +#define AX_RXHDR_DROP_ERR BIT(31) #define AX_ENDPOINT_INT 0x01 #define AX_ENDPOINT_IN 0x02 #define AX_ENDPOINT_OUT 0x03 @@ -39,124 +39,124 @@ #define AX_PAUSE_WATERLVL_LOW 0x55 #define PHYSICAL_LINK_STATUS 0x02 - #define AX_USB_SS (1 << 2) - #define AX_USB_HS (1 << 1) + #define AX_USB_SS BIT(2) + #define AX_USB_HS BIT(1) #define GENERAL_STATUS 0x03 - #define AX_SECLD (1 << 2) + #define AX_SECLD BIT(2) #define AX_SROM_ADDR 0x07 #define AX_SROM_CMD 0x0a - #define EEP_RD (1 << 2) - #define EEP_BUSY (1 << 4) + #define EEP_RD BIT(2) + #define EEP_BUSY BIT(4) #define AX_SROM_DATA_LOW 0x08 #define AX_SROM_DATA_HIGH 0x09 #define AX_RX_CTL 0x0b - #define AX_RX_CTL_DROPCRCERR (1 << 8) - #define AX_RX_CTL_IPE (1 << 9) - #define AX_RX_CTL_START (1 << 7) - #define AX_RX_CTL_AP (1 << 5) - #define AX_RX_CTL_AM (1 << 4) - #define AX_RX_CTL_AB (1 << 3) - #define AX_RX_CTL_AMALL (1 << 1) - #define AX_RX_CTL_PRO (1 << 0) + #define AX_RX_CTL_DROPCRCERR BIT(8) + #define AX_RX_CTL_IPE BIT(9) + #define AX_RX_CTL_START BIT(7) + #define AX_RX_CTL_AP BIT(5) + #define AX_RX_CTL_AM BIT(4) + #define AX_RX_CTL_AB BIT(3) + #define AX_RX_CTL_AMALL BIT(1) + #define AX_RX_CTL_PRO BIT(0) #define AX_RX_CTL_STOP 0 #define AX_NODE_ID 0x10 #define AX_MULFLTARY 0x16 #define AX_MEDIUM_STATUS_MODE 0x22 - #define AX_MEDIUM_GIGAMODE (1 << 0) - #define AX_MEDIUM_FULL_DUPLEX (1 << 1) - #define AX_MEDIUM_EN_125MHZ (1 << 3) - #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) - #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) - #define AX_MEDIUM_RECEIVE_EN (1 << 8) - #define AX_MEDIUM_PS (1 << 9) + #define AX_MEDIUM_GIGAMODE BIT(0) + #define AX_MEDIUM_FULL_DUPLEX BIT(1) + #define AX_MEDIUM_EN_125MHZ BIT(3) + #define AX_MEDIUM_RXFLOW_CTRLEN BIT(4) + #define AX_MEDIUM_TXFLOW_CTRLEN BIT(5) + #define AX_MEDIUM_RECEIVE_EN BIT(8) + #define AX_MEDIUM_PS BIT(9) #define AX_MEDIUM_JUMBO_EN 0x8040 #define AX_MONITOR_MOD 0x24 - #define AX_MONITOR_MODE_RWLC (1 << 1) - #define AX_MONITOR_MODE_RWMP (1 << 2) - #define AX_MONITOR_MODE_PMEPOL (1 << 5) - #define AX_MONITOR_MODE_PMETYPE (1 << 6) + #define AX_MONITOR_MODE_RWLC BIT(1) + #define AX_MONITOR_MODE_RWMP BIT(2) + #define AX_MONITOR_MODE_PMEPOL BIT(5) + #define AX_MONITOR_MODE_PMETYPE BIT(6) #define AX_GPIO_CTRL 0x25 - #define AX_GPIO_CTRL_GPIO3EN (1 << 7) - #define AX_GPIO_CTRL_GPIO2EN (1 << 6) - #define AX_GPIO_CTRL_GPIO1EN (1 << 5) + #define AX_GPIO_CTRL_GPIO3EN BIT(7) + #define AX_GPIO_CTRL_GPIO2EN BIT(6) + #define AX_GPIO_CTRL_GPIO1EN BIT(5) #define AX_PHYPWR_RSTCTL 0x26 - #define AX_PHYPWR_RSTCTL_BZ (1 << 4) - #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) - #define AX_PHYPWR_RSTCTL_AT (1 << 12) + #define AX_PHYPWR_RSTCTL_BZ BIT(4) + #define AX_PHYPWR_RSTCTL_IPRL BIT(5) + #define AX_PHYPWR_RSTCTL_AT BIT(12) #define AX_RX_BULKIN_QCTRL 0x2e #define AX_CLK_SELECT 0x33 - #define AX_CLK_SELECT_BCS (1 << 0) - #define AX_CLK_SELECT_ACS (1 << 1) - #define AX_CLK_SELECT_ULR (1 << 3) + #define AX_CLK_SELECT_BCS BIT(0) + #define AX_CLK_SELECT_ACS BIT(1) + #define AX_CLK_SELECT_ULR BIT(3) #define AX_RXCOE_CTL 0x34 - #define AX_RXCOE_IP (1 << 0) - #define AX_RXCOE_TCP (1 << 1) - #define AX_RXCOE_UDP (1 << 2) - #define AX_RXCOE_TCPV6 (1 << 5) - #define AX_RXCOE_UDPV6 (1 << 6) + #define AX_RXCOE_IP BIT(0) + #define AX_RXCOE_TCP BIT(1) + #define AX_RXCOE_UDP BIT(2) + #define AX_RXCOE_TCPV6 BIT(5) + #define AX_RXCOE_UDPV6 BIT(6) #define AX_TXCOE_CTL 0x35 - #define AX_TXCOE_IP (1 << 0) - #define AX_TXCOE_TCP (1 << 1) - #define AX_TXCOE_UDP (1 << 2) - #define AX_TXCOE_TCPV6 (1 << 5) - #define AX_TXCOE_UDPV6 (1 << 6) + #define AX_TXCOE_IP BIT(0) + #define AX_TXCOE_TCP BIT(1) + #define AX_TXCOE_UDP BIT(2) + #define AX_TXCOE_TCPV6 BIT(5) + #define AX_TXCOE_UDPV6 BIT(6) #define AX_LEDCTRL 0x73 #define GMII_PHY_PHYSR 0x11 #define GMII_PHY_PHYSR_SMASK 0xc000 - #define GMII_PHY_PHYSR_GIGA (1 << 15) - #define GMII_PHY_PHYSR_100 (1 << 14) - #define GMII_PHY_PHYSR_FULL (1 << 13) - #define GMII_PHY_PHYSR_LINK (1 << 10) + #define GMII_PHY_PHYSR_GIGA BIT(15) + #define GMII_PHY_PHYSR_100 BIT(14) + #define GMII_PHY_PHYSR_FULL BIT(13) + #define GMII_PHY_PHYSR_LINK BIT(10) #define GMII_LED_ACT 0x1a #define GMII_LED_ACTIVE_MASK 0xff8f - #define GMII_LED0_ACTIVE (1 << 4) - #define GMII_LED1_ACTIVE (1 << 5) - #define GMII_LED2_ACTIVE (1 << 6) + #define GMII_LED0_ACTIVE BIT(4) + #define GMII_LED1_ACTIVE BIT(5) + #define GMII_LED2_ACTIVE BIT(6) #define GMII_LED_LINK 0x1c #define GMII_LED_LINK_MASK 0xf888 - #define GMII_LED0_LINK_10 (1 << 0) - #define GMII_LED0_LINK_100 (1 << 1) - #define GMII_LED0_LINK_1000 (1 << 2) - #define GMII_LED1_LINK_10 (1 << 4) - #define GMII_LED1_LINK_100 (1 << 5) - #define GMII_LED1_LINK_1000 (1 << 6) - #define GMII_LED2_LINK_10 (1 << 8) - #define GMII_LED2_LINK_100 (1 << 9) - #define GMII_LED2_LINK_1000 (1 << 10) - #define LED0_ACTIVE (1 << 0) - #define LED0_LINK_10 (1 << 1) - #define LED0_LINK_100 (1 << 2) - #define LED0_LINK_1000 (1 << 3) - #define LED0_FD (1 << 4) + #define GMII_LED0_LINK_10 BIT(0) + #define GMII_LED0_LINK_100 BIT(1) + #define GMII_LED0_LINK_1000 BIT(2) + #define GMII_LED1_LINK_10 BIT(4) + #define GMII_LED1_LINK_100 BIT(5) + #define GMII_LED1_LINK_1000 BIT(6) + #define GMII_LED2_LINK_10 BIT(8) + #define GMII_LED2_LINK_100 BIT(9) + #define GMII_LED2_LINK_1000 BIT(10) + #define LED0_ACTIVE BIT(0) + #define LED0_LINK_10 BIT(1) + #define LED0_LINK_100 BIT(2) + #define LED0_LINK_1000 BIT(3) + #define LED0_FD BIT(4) #define LED0_USB3_MASK 0x001f - #define LED1_ACTIVE (1 << 5) - #define LED1_LINK_10 (1 << 6) - #define LED1_LINK_100 (1 << 7) - #define LED1_LINK_1000 (1 << 8) - #define LED1_FD (1 << 9) + #define LED1_ACTIVE BIT(5) + #define LED1_LINK_10 BIT(6) + #define LED1_LINK_100 BIT(7) + #define LED1_LINK_1000 BIT(8) + #define LED1_FD BIT(9) #define LED1_USB3_MASK 0x03e0 - #define LED2_ACTIVE (1 << 10) - #define LED2_LINK_1000 (1 << 13) - #define LED2_LINK_100 (1 << 12) - #define LED2_LINK_10 (1 << 11) - #define LED2_FD (1 << 14) - #define LED_VALID (1 << 15) + #define LED2_ACTIVE BIT(10) + #define LED2_LINK_1000 BIT(13) + #define LED2_LINK_100 BIT(12) + #define LED2_LINK_10 BIT(11) + #define LED2_FD BIT(14) + #define LED_VALID BIT(15) #define LED2_USB3_MASK 0x7c00 #define GMII_PHYPAGE 0x1e diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h index 92e462d..ede46f3 100644 --- a/drivers/usb/gadget/atmel_usba_udc.h +++ b/drivers/usb/gadget/atmel_usba_udc.h @@ -41,8 +41,8 @@ #define USBA_FADDR_EN (1 << 7) #define USBA_EN_USBA (1 << 8) #define USBA_DETACH (1 << 9) -#define USBA_REMOTE_WAKE_UP (1 << 10) -#define USBA_PULLD_DIS (1 << 11) +#define USBA_REMOTE_WAKE_UP BIT(10) +#define USBA_PULLD_DIS BIT(11) #if defined(CONFIG_AVR32) #define USBA_ENABLE_MASK USBA_EN_USBA @@ -57,7 +57,7 @@ #define USBA_MICRO_FRAME_NUM_SIZE 3 #define USBA_FRAME_NUMBER_OFFSET 3 #define USBA_FRAME_NUMBER_SIZE 11 -#define USBA_FRAME_NUM_ERROR (1 << 31) +#define USBA_FRAME_NUM_ERROR BIT(31) /* Bitfields in INT_ENB/INT_STA/INT_CLR */ #define USBA_HIGH_SPEED (1 << 0) @@ -95,7 +95,7 @@ #define USBA_BK_NUMBER_SIZE 2 #define USBA_NB_TRANS_OFFSET 8 #define USBA_NB_TRANS_SIZE 2 -#define USBA_EPT_MAPPED (1 << 31) +#define USBA_EPT_MAPPED BIT(31) /* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */ #define USBA_EPT_ENABLE (1 << 0) @@ -105,7 +105,7 @@ #define USBA_DATAX_RX (1 << 6) #define USBA_MDATA_RX (1 << 7) /* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */ -#define USBA_BUSY_BANK_IE (1 << 18) +#define USBA_BUSY_BANK_IE BIT(18) /* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */ #define USBA_FORCE_STALL (1 << 5) @@ -115,24 +115,24 @@ #define USBA_ERR_OVFLW (1 << 8) #define USBA_RX_BK_RDY (1 << 9) #define USBA_KILL_BANK (1 << 9) -#define USBA_TX_COMPLETE (1 << 10) -#define USBA_TX_PK_RDY (1 << 11) -#define USBA_ISO_ERR_TRANS (1 << 11) -#define USBA_RX_SETUP (1 << 12) -#define USBA_ISO_ERR_FLOW (1 << 12) -#define USBA_STALL_SENT (1 << 13) -#define USBA_ISO_ERR_CRC (1 << 13) -#define USBA_ISO_ERR_NBTRANS (1 << 13) -#define USBA_NAK_IN (1 << 14) -#define USBA_ISO_ERR_FLUSH (1 << 14) -#define USBA_NAK_OUT (1 << 15) +#define USBA_TX_COMPLETE BIT(10) +#define USBA_TX_PK_RDY BIT(11) +#define USBA_ISO_ERR_TRANS BIT(11) +#define USBA_RX_SETUP BIT(12) +#define USBA_ISO_ERR_FLOW BIT(12) +#define USBA_STALL_SENT BIT(13) +#define USBA_ISO_ERR_CRC BIT(13) +#define USBA_ISO_ERR_NBTRANS BIT(13) +#define USBA_NAK_IN BIT(14) +#define USBA_ISO_ERR_FLUSH BIT(14) +#define USBA_NAK_OUT BIT(15) #define USBA_CURRENT_BANK_OFFSET 16 #define USBA_CURRENT_BANK_SIZE 2 #define USBA_BUSY_BANKS_OFFSET 18 #define USBA_BUSY_BANKS_SIZE 2 #define USBA_BYTE_COUNT_OFFSET 20 #define USBA_BYTE_COUNT_SIZE 11 -#define USBA_SHORT_PACKET (1 << 31) +#define USBA_SHORT_PACKET BIT(31) /* Bitfields in DMA_CONTROL */ #define USBA_DMA_CH_EN (1 << 0) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 22d288c..80e41f1 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -618,7 +618,7 @@ static void handle_setup(void) * write address delayed (will take effect * after the next IN txn) */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + writel((r.wValue << 25) | BIT(24), &udc->devaddr); req->length = 0; usb_ep_queue(controller.gadget.ep0, req, 0); return; @@ -641,7 +641,7 @@ static void handle_setup(void) return; DBG("STALL reqname %s type %x value %x, index %x\n", reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); - writel((1<<16) | (1 << 0), &udc->epctrl[0]); + writel((1<<16) | BIT(0), &udc->epctrl[0]); } static void stop_activity(void) diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 346164a..be3c76c 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -50,30 +50,30 @@ struct ci_udc { #define PTS_ENABLE 2 #define PTS(x) (((x) & 0x3) << 30) -#define PFSC (1 << 24) +#define PFSC BIT(24) #endif #define MICRO_8FRAME 0x8 #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) -#define USBCMD_FS2 (1 << 15) -#define USBCMD_RST (1 << 1) +#define USBCMD_FS2 BIT(15) +#define USBCMD_RST BIT(1) #define USBCMD_RUN (1) -#define STS_SLI (1 << 8) -#define STS_URI (1 << 6) -#define STS_PCI (1 << 2) -#define STS_UEI (1 << 1) -#define STS_UI (1 << 0) +#define STS_SLI BIT(8) +#define STS_URI BIT(6) +#define STS_PCI BIT(2) +#define STS_UEI BIT(1) +#define STS_UI BIT(0) #define USBMODE_DEVICE 2 #define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) #define EPT_RX(x) (1 << ((x) & 0xffff)) -#define CTRL_TXE (1 << 23) -#define CTRL_TXR (1 << 22) -#define CTRL_RXE (1 << 7) -#define CTRL_RXR (1 << 6) +#define CTRL_TXE BIT(23) +#define CTRL_TXR BIT(22) +#define CTRL_RXE BIT(7) +#define CTRL_RXR BIT(6) #define CTRL_TXT_BULK (2 << 18) #define CTRL_RXT_BULK (2 << 2) @@ -128,8 +128,8 @@ struct ept_queue_head { }; #define CONFIG_MAX_PKT(n) ((n) << 16) -#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ -#define CONFIG_IOS (1 << 15) /* IRQ on setup */ +#define CONFIG_ZLT BIT(29) /* stop on zero-len xfer */ +#define CONFIG_IOS BIT(15) /* IRQ on setup */ struct ept_queue_item { unsigned next; @@ -144,9 +144,9 @@ struct ept_queue_item { #define TERMINATE 1 #define INFO_BYTES(n) ((n) << 16) -#define INFO_IOC (1 << 15) -#define INFO_ACTIVE (1 << 7) -#define INFO_HALTED (1 << 6) -#define INFO_BUFFER_ERROR (1 << 5) -#define INFO_TX_ERROR (1 << 3) +#define INFO_IOC BIT(15) +#define INFO_ACTIVE BIT(7) +#define INFO_HALTED BIT(6) +#define INFO_BUFFER_ERROR BIT(5) +#define INFO_TX_ERROR BIT(3) #endif diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index 0db7a3b..5706de2 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -671,20 +671,20 @@ void udc_setup_ep(struct usb_device_instance *device, if (ep_type == ENDP_EPTYPE_INT) { /* Conf no. 1 Interface no. 0 */ writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | + ENDP_EPDIR_IN | BIT(7) | (0 << 11) | (ep_type << 5) | ep_num, &udc_regs_p->udc_endp_reg[ep_num]); } else { /* Conf no. 1 Interface no. 1 */ writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | - (1 << 11) | (ep_type << 5) | ep_num, + ENDP_EPDIR_IN | BIT(7) | + BIT(11) | (ep_type << 5) | ep_num, &udc_regs_p->udc_endp_reg[ep_num]); } } else { /* Conf no. 1 Interface no. 0 */ writel((packet_size << 19) | - ENDP_EPDIR_IN | (1 << 7) | + ENDP_EPDIR_IN | BIT(7) | (0 << 11) | (ep_type << 5) | ep_num, &udc_regs_p->udc_endp_reg[ep_num]); } @@ -698,12 +698,12 @@ void udc_setup_ep(struct usb_device_instance *device, if (!strcmp(tt, "cdc_acm")) { writel((packet_size << 19) | - ENDP_EPDIR_OUT | (1 << 7) | - (1 << 11) | (ep_type << 5) | ep_num, + ENDP_EPDIR_OUT | BIT(7) | + BIT(11) | (ep_type << 5) | ep_num, &udc_regs_p->udc_endp_reg[ep_num]); } else { writel((packet_size << 19) | - ENDP_EPDIR_OUT | (1 << 7) | + ENDP_EPDIR_OUT | BIT(7) | (0 << 11) | (ep_type << 5) | ep_num, &udc_regs_p->udc_endp_reg[ep_num]); } @@ -935,7 +935,7 @@ static void dw_udc_endpoint_irq(void) epnum++; } - writel((1 << 16) << epnum, &udc_regs_p->endp_int); + writel(BIT(16) << epnum, &udc_regs_p->endp_int); if ((readl(&outep_regs_p[epnum].endp_status) & ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index 9423555..7471a86 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -472,7 +472,7 @@ void udc_irq(void) /* The UDCCR reg contains mask and interrupt status bits, * so using '|=' isn't safe as it may ack an interrupt. */ -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +#define UDCCR_OEN BIT(31) /* On-the-Go Enable */ #define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE) static inline void udc_set_mask_UDCCR(int mask) diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 45408c6..c5eb6c1 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -65,264 +65,264 @@ struct dwc2_core_regs { u32 pcgcctl; /* 0xe00 */ }; -#define DWC2_GOTGCTL_SESREQSCS (1 << 0) +#define DWC2_GOTGCTL_SESREQSCS BIT(0) #define DWC2_GOTGCTL_SESREQSCS_OFFSET 0 -#define DWC2_GOTGCTL_SESREQ (1 << 1) +#define DWC2_GOTGCTL_SESREQ BIT(1) #define DWC2_GOTGCTL_SESREQ_OFFSET 1 -#define DWC2_GOTGCTL_HSTNEGSCS (1 << 8) +#define DWC2_GOTGCTL_HSTNEGSCS BIT(8) #define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8 -#define DWC2_GOTGCTL_HNPREQ (1 << 9) +#define DWC2_GOTGCTL_HNPREQ BIT(9) #define DWC2_GOTGCTL_HNPREQ_OFFSET 9 -#define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10) +#define DWC2_GOTGCTL_HSTSETHNPEN BIT(10) #define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10 -#define DWC2_GOTGCTL_DEVHNPEN (1 << 11) +#define DWC2_GOTGCTL_DEVHNPEN BIT(11) #define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11 -#define DWC2_GOTGCTL_CONIDSTS (1 << 16) +#define DWC2_GOTGCTL_CONIDSTS BIT(16) #define DWC2_GOTGCTL_CONIDSTS_OFFSET 16 -#define DWC2_GOTGCTL_DBNCTIME (1 << 17) +#define DWC2_GOTGCTL_DBNCTIME BIT(17) #define DWC2_GOTGCTL_DBNCTIME_OFFSET 17 -#define DWC2_GOTGCTL_ASESVLD (1 << 18) +#define DWC2_GOTGCTL_ASESVLD BIT(18) #define DWC2_GOTGCTL_ASESVLD_OFFSET 18 -#define DWC2_GOTGCTL_BSESVLD (1 << 19) +#define DWC2_GOTGCTL_BSESVLD BIT(19) #define DWC2_GOTGCTL_BSESVLD_OFFSET 19 -#define DWC2_GOTGCTL_OTGVER (1 << 20) +#define DWC2_GOTGCTL_OTGVER BIT(20) #define DWC2_GOTGCTL_OTGVER_OFFSET 20 -#define DWC2_GOTGINT_SESENDDET (1 << 2) +#define DWC2_GOTGINT_SESENDDET BIT(2) #define DWC2_GOTGINT_SESENDDET_OFFSET 2 -#define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8) +#define DWC2_GOTGINT_SESREQSUCSTSCHNG BIT(8) #define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8 -#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9) +#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG BIT(9) #define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9 #define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10) #define DWC2_GOTGINT_RESERVER10_16_OFFSET 10 -#define DWC2_GOTGINT_HSTNEGDET (1 << 17) +#define DWC2_GOTGINT_HSTNEGDET BIT(17) #define DWC2_GOTGINT_HSTNEGDET_OFFSET 17 -#define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18) +#define DWC2_GOTGINT_ADEVTOUTCHNG BIT(18) #define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18 -#define DWC2_GOTGINT_DEBDONE (1 << 19) +#define DWC2_GOTGINT_DEBDONE BIT(19) #define DWC2_GOTGINT_DEBDONE_OFFSET 19 -#define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0) +#define DWC2_GAHBCFG_GLBLINTRMSK BIT(0) #define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0 #define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1) +#define DWC2_GAHBCFG_HBURSTLEN_INCR BIT(1) #define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1) #define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1) #define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1) #define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1) #define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1 -#define DWC2_GAHBCFG_DMAENABLE (1 << 5) +#define DWC2_GAHBCFG_DMAENABLE BIT(5) #define DWC2_GAHBCFG_DMAENABLE_OFFSET 5 -#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7) +#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL BIT(7) #define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7 -#define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8) +#define DWC2_GAHBCFG_PTXFEMPLVL BIT(8) #define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8 #define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0) #define DWC2_GUSBCFG_TOUTCAL_OFFSET 0 -#define DWC2_GUSBCFG_PHYIF (1 << 3) +#define DWC2_GUSBCFG_PHYIF BIT(3) #define DWC2_GUSBCFG_PHYIF_OFFSET 3 -#define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4) +#define DWC2_GUSBCFG_ULPI_UTMI_SEL BIT(4) #define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4 -#define DWC2_GUSBCFG_FSINTF (1 << 5) +#define DWC2_GUSBCFG_FSINTF BIT(5) #define DWC2_GUSBCFG_FSINTF_OFFSET 5 -#define DWC2_GUSBCFG_PHYSEL (1 << 6) +#define DWC2_GUSBCFG_PHYSEL BIT(6) #define DWC2_GUSBCFG_PHYSEL_OFFSET 6 -#define DWC2_GUSBCFG_DDRSEL (1 << 7) +#define DWC2_GUSBCFG_DDRSEL BIT(7) #define DWC2_GUSBCFG_DDRSEL_OFFSET 7 -#define DWC2_GUSBCFG_SRPCAP (1 << 8) +#define DWC2_GUSBCFG_SRPCAP BIT(8) #define DWC2_GUSBCFG_SRPCAP_OFFSET 8 -#define DWC2_GUSBCFG_HNPCAP (1 << 9) +#define DWC2_GUSBCFG_HNPCAP BIT(9) #define DWC2_GUSBCFG_HNPCAP_OFFSET 9 #define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10) #define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10 -#define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14) +#define DWC2_GUSBCFG_NPTXFRWNDEN BIT(14) #define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14 -#define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15) +#define DWC2_GUSBCFG_PHYLPWRCLKSEL BIT(15) #define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15 -#define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16) +#define DWC2_GUSBCFG_OTGUTMIFSSEL BIT(16) #define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16 -#define DWC2_GUSBCFG_ULPI_FSLS (1 << 17) +#define DWC2_GUSBCFG_ULPI_FSLS BIT(17) #define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17 -#define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18) +#define DWC2_GUSBCFG_ULPI_AUTO_RES BIT(18) #define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18 -#define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19) +#define DWC2_GUSBCFG_ULPI_CLK_SUS_M BIT(19) #define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19 -#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) +#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) #define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20 -#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21) +#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR BIT(21) #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21 -#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22) +#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE BIT(22) #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22 -#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26) +#define DWC2_GUSBCFG_IC_USB_CAP BIT(26) #define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26 -#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27) +#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE BIT(27) #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27 -#define DWC2_GUSBCFG_TX_END_DELAY (1 << 28) +#define DWC2_GUSBCFG_TX_END_DELAY BIT(28) #define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28 -#define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29) +#define DWC2_GUSBCFG_FORCEHOSTMODE BIT(29) #define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29 -#define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30) +#define DWC2_GUSBCFG_FORCEDEVMODE BIT(30) #define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30 -#define DWC2_GLPMCTL_LPM_CAP_EN (1 << 0) +#define DWC2_GLPMCTL_LPM_CAP_EN BIT(0) #define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET 0 -#define DWC2_GLPMCTL_APPL_RESP (1 << 1) +#define DWC2_GLPMCTL_APPL_RESP BIT(1) #define DWC2_GLPMCTL_APPL_RESP_OFFSET 1 #define DWC2_GLPMCTL_HIRD_MASK (0xF << 2) #define DWC2_GLPMCTL_HIRD_OFFSET 2 -#define DWC2_GLPMCTL_REM_WKUP_EN (1 << 6) +#define DWC2_GLPMCTL_REM_WKUP_EN BIT(6) #define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET 6 -#define DWC2_GLPMCTL_EN_UTMI_SLEEP (1 << 7) +#define DWC2_GLPMCTL_EN_UTMI_SLEEP BIT(7) #define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET 7 #define DWC2_GLPMCTL_HIRD_THRES_MASK (0x1F << 8) #define DWC2_GLPMCTL_HIRD_THRES_OFFSET 8 #define DWC2_GLPMCTL_LPM_RESP_MASK (0x3 << 13) #define DWC2_GLPMCTL_LPM_RESP_OFFSET 13 -#define DWC2_GLPMCTL_PRT_SLEEP_STS (1 << 15) +#define DWC2_GLPMCTL_PRT_SLEEP_STS BIT(15) #define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET 15 -#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK (1 << 16) +#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK BIT(16) #define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET 16 #define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK (0xF << 17) #define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET 17 #define DWC2_GLPMCTL_RETRY_COUNT_MASK (0x7 << 21) #define DWC2_GLPMCTL_RETRY_COUNT_OFFSET 21 -#define DWC2_GLPMCTL_SEND_LPM (1 << 24) +#define DWC2_GLPMCTL_SEND_LPM BIT(24) #define DWC2_GLPMCTL_SEND_LPM_OFFSET 24 #define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK (0x7 << 25) #define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET 25 -#define DWC2_GLPMCTL_HSIC_CONNECT (1 << 30) +#define DWC2_GLPMCTL_HSIC_CONNECT BIT(30) #define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET 30 -#define DWC2_GLPMCTL_INV_SEL_HSIC (1 << 31) +#define DWC2_GLPMCTL_INV_SEL_HSIC BIT(31) #define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET 31 -#define DWC2_GRSTCTL_CSFTRST (1 << 0) +#define DWC2_GRSTCTL_CSFTRST BIT(0) #define DWC2_GRSTCTL_CSFTRST_OFFSET 0 -#define DWC2_GRSTCTL_HSFTRST (1 << 1) +#define DWC2_GRSTCTL_HSFTRST BIT(1) #define DWC2_GRSTCTL_HSFTRST_OFFSET 1 -#define DWC2_GRSTCTL_HSTFRM (1 << 2) +#define DWC2_GRSTCTL_HSTFRM BIT(2) #define DWC2_GRSTCTL_HSTFRM_OFFSET 2 -#define DWC2_GRSTCTL_INTKNQFLSH (1 << 3) +#define DWC2_GRSTCTL_INTKNQFLSH BIT(3) #define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3 -#define DWC2_GRSTCTL_RXFFLSH (1 << 4) +#define DWC2_GRSTCTL_RXFFLSH BIT(4) #define DWC2_GRSTCTL_RXFFLSH_OFFSET 4 -#define DWC2_GRSTCTL_TXFFLSH (1 << 5) +#define DWC2_GRSTCTL_TXFFLSH BIT(5) #define DWC2_GRSTCTL_TXFFLSH_OFFSET 5 #define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6) #define DWC2_GRSTCTL_TXFNUM_OFFSET 6 -#define DWC2_GRSTCTL_DMAREQ (1 << 30) +#define DWC2_GRSTCTL_DMAREQ BIT(30) #define DWC2_GRSTCTL_DMAREQ_OFFSET 30 -#define DWC2_GRSTCTL_AHBIDLE (1 << 31) +#define DWC2_GRSTCTL_AHBIDLE BIT(31) #define DWC2_GRSTCTL_AHBIDLE_OFFSET 31 -#define DWC2_GINTMSK_MODEMISMATCH (1 << 1) +#define DWC2_GINTMSK_MODEMISMATCH BIT(1) #define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1 -#define DWC2_GINTMSK_OTGINTR (1 << 2) +#define DWC2_GINTMSK_OTGINTR BIT(2) #define DWC2_GINTMSK_OTGINTR_OFFSET 2 -#define DWC2_GINTMSK_SOFINTR (1 << 3) +#define DWC2_GINTMSK_SOFINTR BIT(3) #define DWC2_GINTMSK_SOFINTR_OFFSET 3 -#define DWC2_GINTMSK_RXSTSQLVL (1 << 4) +#define DWC2_GINTMSK_RXSTSQLVL BIT(4) #define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4 -#define DWC2_GINTMSK_NPTXFEMPTY (1 << 5) +#define DWC2_GINTMSK_NPTXFEMPTY BIT(5) #define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5 -#define DWC2_GINTMSK_GINNAKEFF (1 << 6) +#define DWC2_GINTMSK_GINNAKEFF BIT(6) #define DWC2_GINTMSK_GINNAKEFF_OFFSET 6 -#define DWC2_GINTMSK_GOUTNAKEFF (1 << 7) +#define DWC2_GINTMSK_GOUTNAKEFF BIT(7) #define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7 -#define DWC2_GINTMSK_I2CINTR (1 << 9) +#define DWC2_GINTMSK_I2CINTR BIT(9) #define DWC2_GINTMSK_I2CINTR_OFFSET 9 -#define DWC2_GINTMSK_ERLYSUSPEND (1 << 10) +#define DWC2_GINTMSK_ERLYSUSPEND BIT(10) #define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10 -#define DWC2_GINTMSK_USBSUSPEND (1 << 11) +#define DWC2_GINTMSK_USBSUSPEND BIT(11) #define DWC2_GINTMSK_USBSUSPEND_OFFSET 11 -#define DWC2_GINTMSK_USBRESET (1 << 12) +#define DWC2_GINTMSK_USBRESET BIT(12) #define DWC2_GINTMSK_USBRESET_OFFSET 12 -#define DWC2_GINTMSK_ENUMDONE (1 << 13) +#define DWC2_GINTMSK_ENUMDONE BIT(13) #define DWC2_GINTMSK_ENUMDONE_OFFSET 13 -#define DWC2_GINTMSK_ISOOUTDROP (1 << 14) +#define DWC2_GINTMSK_ISOOUTDROP BIT(14) #define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14 -#define DWC2_GINTMSK_EOPFRAME (1 << 15) +#define DWC2_GINTMSK_EOPFRAME BIT(15) #define DWC2_GINTMSK_EOPFRAME_OFFSET 15 -#define DWC2_GINTMSK_EPMISMATCH (1 << 17) +#define DWC2_GINTMSK_EPMISMATCH BIT(17) #define DWC2_GINTMSK_EPMISMATCH_OFFSET 17 -#define DWC2_GINTMSK_INEPINTR (1 << 18) +#define DWC2_GINTMSK_INEPINTR BIT(18) #define DWC2_GINTMSK_INEPINTR_OFFSET 18 -#define DWC2_GINTMSK_OUTEPINTR (1 << 19) +#define DWC2_GINTMSK_OUTEPINTR BIT(19) #define DWC2_GINTMSK_OUTEPINTR_OFFSET 19 -#define DWC2_GINTMSK_INCOMPLISOIN (1 << 20) +#define DWC2_GINTMSK_INCOMPLISOIN BIT(20) #define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20 -#define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21) +#define DWC2_GINTMSK_INCOMPLISOOUT BIT(21) #define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21 -#define DWC2_GINTMSK_PORTINTR (1 << 24) +#define DWC2_GINTMSK_PORTINTR BIT(24) #define DWC2_GINTMSK_PORTINTR_OFFSET 24 -#define DWC2_GINTMSK_HCINTR (1 << 25) +#define DWC2_GINTMSK_HCINTR BIT(25) #define DWC2_GINTMSK_HCINTR_OFFSET 25 -#define DWC2_GINTMSK_PTXFEMPTY (1 << 26) +#define DWC2_GINTMSK_PTXFEMPTY BIT(26) #define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26 -#define DWC2_GINTMSK_LPMTRANRCVD (1 << 27) +#define DWC2_GINTMSK_LPMTRANRCVD BIT(27) #define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27 -#define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28) +#define DWC2_GINTMSK_CONIDSTSCHNG BIT(28) #define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28 -#define DWC2_GINTMSK_DISCONNECT (1 << 29) +#define DWC2_GINTMSK_DISCONNECT BIT(29) #define DWC2_GINTMSK_DISCONNECT_OFFSET 29 -#define DWC2_GINTMSK_SESSREQINTR (1 << 30) +#define DWC2_GINTMSK_SESSREQINTR BIT(30) #define DWC2_GINTMSK_SESSREQINTR_OFFSET 30 -#define DWC2_GINTMSK_WKUPINTR (1 << 31) +#define DWC2_GINTMSK_WKUPINTR BIT(31) #define DWC2_GINTMSK_WKUPINTR_OFFSET 31 #define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0) -#define DWC2_GINTSTS_CURMODE_HOST (1 << 0) -#define DWC2_GINTSTS_CURMODE (1 << 0) +#define DWC2_GINTSTS_CURMODE_HOST BIT(0) +#define DWC2_GINTSTS_CURMODE BIT(0) #define DWC2_GINTSTS_CURMODE_OFFSET 0 -#define DWC2_GINTSTS_MODEMISMATCH (1 << 1) +#define DWC2_GINTSTS_MODEMISMATCH BIT(1) #define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1 -#define DWC2_GINTSTS_OTGINTR (1 << 2) +#define DWC2_GINTSTS_OTGINTR BIT(2) #define DWC2_GINTSTS_OTGINTR_OFFSET 2 -#define DWC2_GINTSTS_SOFINTR (1 << 3) +#define DWC2_GINTSTS_SOFINTR BIT(3) #define DWC2_GINTSTS_SOFINTR_OFFSET 3 -#define DWC2_GINTSTS_RXSTSQLVL (1 << 4) +#define DWC2_GINTSTS_RXSTSQLVL BIT(4) #define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4 -#define DWC2_GINTSTS_NPTXFEMPTY (1 << 5) +#define DWC2_GINTSTS_NPTXFEMPTY BIT(5) #define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5 -#define DWC2_GINTSTS_GINNAKEFF (1 << 6) +#define DWC2_GINTSTS_GINNAKEFF BIT(6) #define DWC2_GINTSTS_GINNAKEFF_OFFSET 6 -#define DWC2_GINTSTS_GOUTNAKEFF (1 << 7) +#define DWC2_GINTSTS_GOUTNAKEFF BIT(7) #define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7 -#define DWC2_GINTSTS_I2CINTR (1 << 9) +#define DWC2_GINTSTS_I2CINTR BIT(9) #define DWC2_GINTSTS_I2CINTR_OFFSET 9 -#define DWC2_GINTSTS_ERLYSUSPEND (1 << 10) +#define DWC2_GINTSTS_ERLYSUSPEND BIT(10) #define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10 -#define DWC2_GINTSTS_USBSUSPEND (1 << 11) +#define DWC2_GINTSTS_USBSUSPEND BIT(11) #define DWC2_GINTSTS_USBSUSPEND_OFFSET 11 -#define DWC2_GINTSTS_USBRESET (1 << 12) +#define DWC2_GINTSTS_USBRESET BIT(12) #define DWC2_GINTSTS_USBRESET_OFFSET 12 -#define DWC2_GINTSTS_ENUMDONE (1 << 13) +#define DWC2_GINTSTS_ENUMDONE BIT(13) #define DWC2_GINTSTS_ENUMDONE_OFFSET 13 -#define DWC2_GINTSTS_ISOOUTDROP (1 << 14) +#define DWC2_GINTSTS_ISOOUTDROP BIT(14) #define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14 -#define DWC2_GINTSTS_EOPFRAME (1 << 15) +#define DWC2_GINTSTS_EOPFRAME BIT(15) #define DWC2_GINTSTS_EOPFRAME_OFFSET 15 -#define DWC2_GINTSTS_INTOKENRX (1 << 16) +#define DWC2_GINTSTS_INTOKENRX BIT(16) #define DWC2_GINTSTS_INTOKENRX_OFFSET 16 -#define DWC2_GINTSTS_EPMISMATCH (1 << 17) +#define DWC2_GINTSTS_EPMISMATCH BIT(17) #define DWC2_GINTSTS_EPMISMATCH_OFFSET 17 -#define DWC2_GINTSTS_INEPINT (1 << 18) +#define DWC2_GINTSTS_INEPINT BIT(18) #define DWC2_GINTSTS_INEPINT_OFFSET 18 -#define DWC2_GINTSTS_OUTEPINTR (1 << 19) +#define DWC2_GINTSTS_OUTEPINTR BIT(19) #define DWC2_GINTSTS_OUTEPINTR_OFFSET 19 -#define DWC2_GINTSTS_INCOMPLISOIN (1 << 20) +#define DWC2_GINTSTS_INCOMPLISOIN BIT(20) #define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20 -#define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21) +#define DWC2_GINTSTS_INCOMPLISOOUT BIT(21) #define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21 -#define DWC2_GINTSTS_PORTINTR (1 << 24) +#define DWC2_GINTSTS_PORTINTR BIT(24) #define DWC2_GINTSTS_PORTINTR_OFFSET 24 -#define DWC2_GINTSTS_HCINTR (1 << 25) +#define DWC2_GINTSTS_HCINTR BIT(25) #define DWC2_GINTSTS_HCINTR_OFFSET 25 -#define DWC2_GINTSTS_PTXFEMPTY (1 << 26) +#define DWC2_GINTSTS_PTXFEMPTY BIT(26) #define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26 -#define DWC2_GINTSTS_LPMTRANRCVD (1 << 27) +#define DWC2_GINTSTS_LPMTRANRCVD BIT(27) #define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27 -#define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28) +#define DWC2_GINTSTS_CONIDSTSCHNG BIT(28) #define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28 -#define DWC2_GINTSTS_DISCONNECT (1 << 29) +#define DWC2_GINTSTS_DISCONNECT BIT(29) #define DWC2_GINTSTS_DISCONNECT_OFFSET 29 -#define DWC2_GINTSTS_SESSREQINTR (1 << 30) +#define DWC2_GINTSTS_SESSREQINTR BIT(30) #define DWC2_GINTSTS_SESSREQINTR_OFFSET 30 -#define DWC2_GINTSTS_WKUPINTR (1 << 31) +#define DWC2_GINTSTS_WKUPINTR BIT(31) #define DWC2_GINTSTS_WKUPINTR_OFFSET 31 #define DWC2_GRXSTS_EPNUM_MASK (0xF << 0) #define DWC2_GRXSTS_EPNUM_OFFSET 0 @@ -342,7 +342,7 @@ struct dwc2_core_regs { #define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0 #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16) #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16 -#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24) +#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE BIT(24) #define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24 #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25) #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25 @@ -356,17 +356,17 @@ struct dwc2_core_regs { #define DWC2_GI2CCTL_REGADDR_OFFSET 8 #define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16) #define DWC2_GI2CCTL_ADDR_OFFSET 16 -#define DWC2_GI2CCTL_I2CEN (1 << 23) +#define DWC2_GI2CCTL_I2CEN BIT(23) #define DWC2_GI2CCTL_I2CEN_OFFSET 23 -#define DWC2_GI2CCTL_ACK (1 << 24) +#define DWC2_GI2CCTL_ACK BIT(24) #define DWC2_GI2CCTL_ACK_OFFSET 24 -#define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25) +#define DWC2_GI2CCTL_I2CSUSPCTL BIT(25) #define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25 #define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) #define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26 -#define DWC2_GI2CCTL_RW (1 << 30) +#define DWC2_GI2CCTL_RW BIT(30) #define DWC2_GI2CCTL_RW_OFFSET 30 -#define DWC2_GI2CCTL_BSYDNE (1 << 31) +#define DWC2_GI2CCTL_BSYDNE BIT(31) #define DWC2_GI2CCTL_BSYDNE_OFFSET 31 #define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0) #define DWC2_HWCFG1_EP_DIR0_OFFSET 0 @@ -407,7 +407,7 @@ struct dwc2_core_regs { #define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3) #define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3) #define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3 -#define DWC2_HWCFG2_POINT2POINT (1 << 5) +#define DWC2_HWCFG2_POINT2POINT BIT(5) #define DWC2_HWCFG2_POINT2POINT_OFFSET 5 #define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) #define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6 @@ -417,11 +417,11 @@ struct dwc2_core_regs { #define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10 #define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14) #define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14 -#define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18) +#define DWC2_HWCFG2_PERIO_EP_SUPPORTED BIT(18) #define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18 -#define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19) +#define DWC2_HWCFG2_DYNAMIC_FIFO BIT(19) #define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19 -#define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20) +#define DWC2_HWCFG2_MULTI_PROC_INT BIT(20) #define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20 #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22 @@ -433,27 +433,27 @@ struct dwc2_core_regs { #define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0 #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4 -#define DWC2_HWCFG3_OTG_FUNC (1 << 7) +#define DWC2_HWCFG3_OTG_FUNC BIT(7) #define DWC2_HWCFG3_OTG_FUNC_OFFSET 7 -#define DWC2_HWCFG3_I2C (1 << 8) +#define DWC2_HWCFG3_I2C BIT(8) #define DWC2_HWCFG3_I2C_OFFSET 8 -#define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9) +#define DWC2_HWCFG3_VENDOR_CTRL_IF BIT(9) #define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9 -#define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10) +#define DWC2_HWCFG3_OPTIONAL_FEATURES BIT(10) #define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10 -#define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11) +#define DWC2_HWCFG3_SYNCH_RESET_TYPE BIT(11) #define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11 -#define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12) +#define DWC2_HWCFG3_OTG_ENABLE_IC_USB BIT(12) #define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12 -#define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13) +#define DWC2_HWCFG3_OTG_ENABLE_HSIC BIT(13) #define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13 -#define DWC2_HWCFG3_OTG_LPM_EN (1 << 15) +#define DWC2_HWCFG3_OTG_LPM_EN BIT(15) #define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15 #define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16) #define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16 #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0) #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0 -#define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4) +#define DWC2_HWCFG4_POWER_OPTIMIZ BIT(4) #define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4 #define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5) #define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5 @@ -461,38 +461,38 @@ struct dwc2_core_regs { #define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14 #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16) #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16 -#define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20) +#define DWC2_HWCFG4_IDDIG_FILT_EN BIT(20) #define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20 -#define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21) +#define DWC2_HWCFG4_VBUS_VALID_FILT_EN BIT(21) #define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21 -#define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22) +#define DWC2_HWCFG4_A_VALID_FILT_EN BIT(22) #define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22 -#define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23) +#define DWC2_HWCFG4_B_VALID_FILT_EN BIT(23) #define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23 -#define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24) +#define DWC2_HWCFG4_SESSION_END_FILT_EN BIT(24) #define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24 -#define DWC2_HWCFG4_DED_FIFO_EN (1 << 25) +#define DWC2_HWCFG4_DED_FIFO_EN BIT(25) #define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25 #define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26) #define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26 -#define DWC2_HWCFG4_DESC_DMA (1 << 30) +#define DWC2_HWCFG4_DESC_DMA BIT(30) #define DWC2_HWCFG4_DESC_DMA_OFFSET 30 -#define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31) +#define DWC2_HWCFG4_DESC_DMA_DYN BIT(31) #define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31 #define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0 #define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1 #define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2 #define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0) #define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0 -#define DWC2_HCFG_FSLSSUPP (1 << 2) +#define DWC2_HCFG_FSLSSUPP BIT(2) #define DWC2_HCFG_FSLSSUPP_OFFSET 2 -#define DWC2_HCFG_DESCDMA (1 << 23) +#define DWC2_HCFG_DESCDMA BIT(23) #define DWC2_HCFG_DESCDMA_OFFSET 23 #define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24) #define DWC2_HCFG_FRLISTEN_OFFSET 24 -#define DWC2_HCFG_PERSCHEDENA (1 << 26) +#define DWC2_HCFG_PERSCHEDENA BIT(26) #define DWC2_HCFG_PERSCHEDENA_OFFSET 26 -#define DWC2_HCFG_PERSCHEDSTAT (1 << 27) +#define DWC2_HCFG_PERSCHEDSTAT BIT(27) #define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27 #define DWC2_HFIR_FRINT_MASK (0xFFFF << 0) #define DWC2_HFIR_FRINT_OFFSET 0 @@ -504,108 +504,108 @@ struct dwc2_core_regs { #define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0 #define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16) #define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16 -#define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24) +#define DWC2_HPTXSTS_PTXQTOP_TERMINATE BIT(24) #define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24 #define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25) #define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25 #define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27) #define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27 -#define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31) +#define DWC2_HPTXSTS_PTXQTOP_ODD BIT(31) #define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31 -#define DWC2_HPRT0_PRTCONNSTS (1 << 0) +#define DWC2_HPRT0_PRTCONNSTS BIT(0) #define DWC2_HPRT0_PRTCONNSTS_OFFSET 0 -#define DWC2_HPRT0_PRTCONNDET (1 << 1) +#define DWC2_HPRT0_PRTCONNDET BIT(1) #define DWC2_HPRT0_PRTCONNDET_OFFSET 1 -#define DWC2_HPRT0_PRTENA (1 << 2) +#define DWC2_HPRT0_PRTENA BIT(2) #define DWC2_HPRT0_PRTENA_OFFSET 2 -#define DWC2_HPRT0_PRTENCHNG (1 << 3) +#define DWC2_HPRT0_PRTENCHNG BIT(3) #define DWC2_HPRT0_PRTENCHNG_OFFSET 3 -#define DWC2_HPRT0_PRTOVRCURRACT (1 << 4) +#define DWC2_HPRT0_PRTOVRCURRACT BIT(4) #define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4 -#define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5) +#define DWC2_HPRT0_PRTOVRCURRCHNG BIT(5) #define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5 -#define DWC2_HPRT0_PRTRES (1 << 6) +#define DWC2_HPRT0_PRTRES BIT(6) #define DWC2_HPRT0_PRTRES_OFFSET 6 -#define DWC2_HPRT0_PRTSUSP (1 << 7) +#define DWC2_HPRT0_PRTSUSP BIT(7) #define DWC2_HPRT0_PRTSUSP_OFFSET 7 -#define DWC2_HPRT0_PRTRST (1 << 8) +#define DWC2_HPRT0_PRTRST BIT(8) #define DWC2_HPRT0_PRTRST_OFFSET 8 #define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10) #define DWC2_HPRT0_PRTLNSTS_OFFSET 10 -#define DWC2_HPRT0_PRTPWR (1 << 12) +#define DWC2_HPRT0_PRTPWR BIT(12) #define DWC2_HPRT0_PRTPWR_OFFSET 12 #define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13) #define DWC2_HPRT0_PRTTSTCTL_OFFSET 13 #define DWC2_HPRT0_PRTSPD_HIGH (0 << 17) -#define DWC2_HPRT0_PRTSPD_FULL (1 << 17) +#define DWC2_HPRT0_PRTSPD_FULL BIT(17) #define DWC2_HPRT0_PRTSPD_LOW (2 << 17) #define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17) #define DWC2_HPRT0_PRTSPD_OFFSET 17 -#define DWC2_HAINT_CH0 (1 << 0) +#define DWC2_HAINT_CH0 BIT(0) #define DWC2_HAINT_CH0_OFFSET 0 -#define DWC2_HAINT_CH1 (1 << 1) +#define DWC2_HAINT_CH1 BIT(1) #define DWC2_HAINT_CH1_OFFSET 1 -#define DWC2_HAINT_CH2 (1 << 2) +#define DWC2_HAINT_CH2 BIT(2) #define DWC2_HAINT_CH2_OFFSET 2 -#define DWC2_HAINT_CH3 (1 << 3) +#define DWC2_HAINT_CH3 BIT(3) #define DWC2_HAINT_CH3_OFFSET 3 -#define DWC2_HAINT_CH4 (1 << 4) +#define DWC2_HAINT_CH4 BIT(4) #define DWC2_HAINT_CH4_OFFSET 4 -#define DWC2_HAINT_CH5 (1 << 5) +#define DWC2_HAINT_CH5 BIT(5) #define DWC2_HAINT_CH5_OFFSET 5 -#define DWC2_HAINT_CH6 (1 << 6) +#define DWC2_HAINT_CH6 BIT(6) #define DWC2_HAINT_CH6_OFFSET 6 -#define DWC2_HAINT_CH7 (1 << 7) +#define DWC2_HAINT_CH7 BIT(7) #define DWC2_HAINT_CH7_OFFSET 7 -#define DWC2_HAINT_CH8 (1 << 8) +#define DWC2_HAINT_CH8 BIT(8) #define DWC2_HAINT_CH8_OFFSET 8 -#define DWC2_HAINT_CH9 (1 << 9) +#define DWC2_HAINT_CH9 BIT(9) #define DWC2_HAINT_CH9_OFFSET 9 -#define DWC2_HAINT_CH10 (1 << 10) +#define DWC2_HAINT_CH10 BIT(10) #define DWC2_HAINT_CH10_OFFSET 10 -#define DWC2_HAINT_CH11 (1 << 11) +#define DWC2_HAINT_CH11 BIT(11) #define DWC2_HAINT_CH11_OFFSET 11 -#define DWC2_HAINT_CH12 (1 << 12) +#define DWC2_HAINT_CH12 BIT(12) #define DWC2_HAINT_CH12_OFFSET 12 -#define DWC2_HAINT_CH13 (1 << 13) +#define DWC2_HAINT_CH13 BIT(13) #define DWC2_HAINT_CH13_OFFSET 13 -#define DWC2_HAINT_CH14 (1 << 14) +#define DWC2_HAINT_CH14 BIT(14) #define DWC2_HAINT_CH14_OFFSET 14 -#define DWC2_HAINT_CH15 (1 << 15) +#define DWC2_HAINT_CH15 BIT(15) #define DWC2_HAINT_CH15_OFFSET 15 #define DWC2_HAINT_CHINT_MASK 0xffff #define DWC2_HAINT_CHINT_OFFSET 0 -#define DWC2_HAINTMSK_CH0 (1 << 0) +#define DWC2_HAINTMSK_CH0 BIT(0) #define DWC2_HAINTMSK_CH0_OFFSET 0 -#define DWC2_HAINTMSK_CH1 (1 << 1) +#define DWC2_HAINTMSK_CH1 BIT(1) #define DWC2_HAINTMSK_CH1_OFFSET 1 -#define DWC2_HAINTMSK_CH2 (1 << 2) +#define DWC2_HAINTMSK_CH2 BIT(2) #define DWC2_HAINTMSK_CH2_OFFSET 2 -#define DWC2_HAINTMSK_CH3 (1 << 3) +#define DWC2_HAINTMSK_CH3 BIT(3) #define DWC2_HAINTMSK_CH3_OFFSET 3 -#define DWC2_HAINTMSK_CH4 (1 << 4) +#define DWC2_HAINTMSK_CH4 BIT(4) #define DWC2_HAINTMSK_CH4_OFFSET 4 -#define DWC2_HAINTMSK_CH5 (1 << 5) +#define DWC2_HAINTMSK_CH5 BIT(5) #define DWC2_HAINTMSK_CH5_OFFSET 5 -#define DWC2_HAINTMSK_CH6 (1 << 6) +#define DWC2_HAINTMSK_CH6 BIT(6) #define DWC2_HAINTMSK_CH6_OFFSET 6 -#define DWC2_HAINTMSK_CH7 (1 << 7) +#define DWC2_HAINTMSK_CH7 BIT(7) #define DWC2_HAINTMSK_CH7_OFFSET 7 -#define DWC2_HAINTMSK_CH8 (1 << 8) +#define DWC2_HAINTMSK_CH8 BIT(8) #define DWC2_HAINTMSK_CH8_OFFSET 8 -#define DWC2_HAINTMSK_CH9 (1 << 9) +#define DWC2_HAINTMSK_CH9 BIT(9) #define DWC2_HAINTMSK_CH9_OFFSET 9 -#define DWC2_HAINTMSK_CH10 (1 << 10) +#define DWC2_HAINTMSK_CH10 BIT(10) #define DWC2_HAINTMSK_CH10_OFFSET 10 -#define DWC2_HAINTMSK_CH11 (1 << 11) +#define DWC2_HAINTMSK_CH11 BIT(11) #define DWC2_HAINTMSK_CH11_OFFSET 11 -#define DWC2_HAINTMSK_CH12 (1 << 12) +#define DWC2_HAINTMSK_CH12 BIT(12) #define DWC2_HAINTMSK_CH12_OFFSET 12 -#define DWC2_HAINTMSK_CH13 (1 << 13) +#define DWC2_HAINTMSK_CH13 BIT(13) #define DWC2_HAINTMSK_CH13_OFFSET 13 -#define DWC2_HAINTMSK_CH14 (1 << 14) +#define DWC2_HAINTMSK_CH14 BIT(14) #define DWC2_HAINTMSK_CH14_OFFSET 14 -#define DWC2_HAINTMSK_CH15 (1 << 15) +#define DWC2_HAINTMSK_CH15 BIT(15) #define DWC2_HAINTMSK_CH15_OFFSET 15 #define DWC2_HAINTMSK_CHINT_MASK 0xffff #define DWC2_HAINTMSK_CHINT_OFFSET 0 @@ -613,9 +613,9 @@ struct dwc2_core_regs { #define DWC2_HCCHAR_MPS_OFFSET 0 #define DWC2_HCCHAR_EPNUM_MASK (0xF << 11) #define DWC2_HCCHAR_EPNUM_OFFSET 11 -#define DWC2_HCCHAR_EPDIR (1 << 15) +#define DWC2_HCCHAR_EPDIR BIT(15) #define DWC2_HCCHAR_EPDIR_OFFSET 15 -#define DWC2_HCCHAR_LSPDDEV (1 << 17) +#define DWC2_HCCHAR_LSPDDEV BIT(17) #define DWC2_HCCHAR_LSPDDEV_OFFSET 17 #define DWC2_HCCHAR_EPTYPE_CONTROL 0 #define DWC2_HCCHAR_EPTYPE_ISOC 1 @@ -627,11 +627,11 @@ struct dwc2_core_regs { #define DWC2_HCCHAR_MULTICNT_OFFSET 20 #define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22) #define DWC2_HCCHAR_DEVADDR_OFFSET 22 -#define DWC2_HCCHAR_ODDFRM (1 << 29) +#define DWC2_HCCHAR_ODDFRM BIT(29) #define DWC2_HCCHAR_ODDFRM_OFFSET 29 -#define DWC2_HCCHAR_CHDIS (1 << 30) +#define DWC2_HCCHAR_CHDIS BIT(30) #define DWC2_HCCHAR_CHDIS_OFFSET 30 -#define DWC2_HCCHAR_CHEN (1 << 31) +#define DWC2_HCCHAR_CHEN BIT(31) #define DWC2_HCCHAR_CHEN_OFFSET 31 #define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0) #define DWC2_HCSPLT_PRTADDR_OFFSET 0 @@ -639,65 +639,65 @@ struct dwc2_core_regs { #define DWC2_HCSPLT_HUBADDR_OFFSET 7 #define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14) #define DWC2_HCSPLT_XACTPOS_OFFSET 14 -#define DWC2_HCSPLT_COMPSPLT (1 << 16) +#define DWC2_HCSPLT_COMPSPLT BIT(16) #define DWC2_HCSPLT_COMPSPLT_OFFSET 16 -#define DWC2_HCSPLT_SPLTENA (1 << 31) +#define DWC2_HCSPLT_SPLTENA BIT(31) #define DWC2_HCSPLT_SPLTENA_OFFSET 31 -#define DWC2_HCINT_XFERCOMP (1 << 0) +#define DWC2_HCINT_XFERCOMP BIT(0) #define DWC2_HCINT_XFERCOMP_OFFSET 0 -#define DWC2_HCINT_CHHLTD (1 << 1) +#define DWC2_HCINT_CHHLTD BIT(1) #define DWC2_HCINT_CHHLTD_OFFSET 1 -#define DWC2_HCINT_AHBERR (1 << 2) +#define DWC2_HCINT_AHBERR BIT(2) #define DWC2_HCINT_AHBERR_OFFSET 2 -#define DWC2_HCINT_STALL (1 << 3) +#define DWC2_HCINT_STALL BIT(3) #define DWC2_HCINT_STALL_OFFSET 3 -#define DWC2_HCINT_NAK (1 << 4) +#define DWC2_HCINT_NAK BIT(4) #define DWC2_HCINT_NAK_OFFSET 4 -#define DWC2_HCINT_ACK (1 << 5) +#define DWC2_HCINT_ACK BIT(5) #define DWC2_HCINT_ACK_OFFSET 5 -#define DWC2_HCINT_NYET (1 << 6) +#define DWC2_HCINT_NYET BIT(6) #define DWC2_HCINT_NYET_OFFSET 6 -#define DWC2_HCINT_XACTERR (1 << 7) +#define DWC2_HCINT_XACTERR BIT(7) #define DWC2_HCINT_XACTERR_OFFSET 7 -#define DWC2_HCINT_BBLERR (1 << 8) +#define DWC2_HCINT_BBLERR BIT(8) #define DWC2_HCINT_BBLERR_OFFSET 8 -#define DWC2_HCINT_FRMOVRUN (1 << 9) +#define DWC2_HCINT_FRMOVRUN BIT(9) #define DWC2_HCINT_FRMOVRUN_OFFSET 9 -#define DWC2_HCINT_DATATGLERR (1 << 10) +#define DWC2_HCINT_DATATGLERR BIT(10) #define DWC2_HCINT_DATATGLERR_OFFSET 10 -#define DWC2_HCINT_BNA (1 << 11) +#define DWC2_HCINT_BNA BIT(11) #define DWC2_HCINT_BNA_OFFSET 11 -#define DWC2_HCINT_XCS_XACT (1 << 12) +#define DWC2_HCINT_XCS_XACT BIT(12) #define DWC2_HCINT_XCS_XACT_OFFSET 12 -#define DWC2_HCINT_FRM_LIST_ROLL (1 << 13) +#define DWC2_HCINT_FRM_LIST_ROLL BIT(13) #define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13 -#define DWC2_HCINTMSK_XFERCOMPL (1 << 0) +#define DWC2_HCINTMSK_XFERCOMPL BIT(0) #define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0 -#define DWC2_HCINTMSK_CHHLTD (1 << 1) +#define DWC2_HCINTMSK_CHHLTD BIT(1) #define DWC2_HCINTMSK_CHHLTD_OFFSET 1 -#define DWC2_HCINTMSK_AHBERR (1 << 2) +#define DWC2_HCINTMSK_AHBERR BIT(2) #define DWC2_HCINTMSK_AHBERR_OFFSET 2 -#define DWC2_HCINTMSK_STALL (1 << 3) +#define DWC2_HCINTMSK_STALL BIT(3) #define DWC2_HCINTMSK_STALL_OFFSET 3 -#define DWC2_HCINTMSK_NAK (1 << 4) +#define DWC2_HCINTMSK_NAK BIT(4) #define DWC2_HCINTMSK_NAK_OFFSET 4 -#define DWC2_HCINTMSK_ACK (1 << 5) +#define DWC2_HCINTMSK_ACK BIT(5) #define DWC2_HCINTMSK_ACK_OFFSET 5 -#define DWC2_HCINTMSK_NYET (1 << 6) +#define DWC2_HCINTMSK_NYET BIT(6) #define DWC2_HCINTMSK_NYET_OFFSET 6 -#define DWC2_HCINTMSK_XACTERR (1 << 7) +#define DWC2_HCINTMSK_XACTERR BIT(7) #define DWC2_HCINTMSK_XACTERR_OFFSET 7 -#define DWC2_HCINTMSK_BBLERR (1 << 8) +#define DWC2_HCINTMSK_BBLERR BIT(8) #define DWC2_HCINTMSK_BBLERR_OFFSET 8 -#define DWC2_HCINTMSK_FRMOVRUN (1 << 9) +#define DWC2_HCINTMSK_FRMOVRUN BIT(9) #define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9 -#define DWC2_HCINTMSK_DATATGLERR (1 << 10) +#define DWC2_HCINTMSK_DATATGLERR BIT(10) #define DWC2_HCINTMSK_DATATGLERR_OFFSET 10 -#define DWC2_HCINTMSK_BNA (1 << 11) +#define DWC2_HCINTMSK_BNA BIT(11) #define DWC2_HCINTMSK_BNA_OFFSET 11 -#define DWC2_HCINTMSK_XCS_XACT (1 << 12) +#define DWC2_HCINTMSK_XCS_XACT BIT(12) #define DWC2_HCINTMSK_XCS_XACT_OFFSET 12 -#define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13) +#define DWC2_HCINTMSK_FRM_LIST_ROLL BIT(13) #define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13 #define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff #define DWC2_HCTSIZ_XFERSIZE_OFFSET 0 @@ -709,27 +709,27 @@ struct dwc2_core_regs { #define DWC2_HCTSIZ_PKTCNT_OFFSET 19 #define DWC2_HCTSIZ_PID_MASK (0x3 << 29) #define DWC2_HCTSIZ_PID_OFFSET 29 -#define DWC2_HCTSIZ_DOPNG (1 << 31) +#define DWC2_HCTSIZ_DOPNG BIT(31) #define DWC2_HCTSIZ_DOPNG_OFFSET 31 #define DWC2_HCDMA_CTD_MASK (0xFF << 3) #define DWC2_HCDMA_CTD_OFFSET 3 #define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11) #define DWC2_HCDMA_DMA_ADDR_OFFSET 11 -#define DWC2_PCGCCTL_STOPPCLK (1 << 0) +#define DWC2_PCGCCTL_STOPPCLK BIT(0) #define DWC2_PCGCCTL_STOPPCLK_OFFSET 0 -#define DWC2_PCGCCTL_GATEHCLK (1 << 1) +#define DWC2_PCGCCTL_GATEHCLK BIT(1) #define DWC2_PCGCCTL_GATEHCLK_OFFSET 1 -#define DWC2_PCGCCTL_PWRCLMP (1 << 2) +#define DWC2_PCGCCTL_PWRCLMP BIT(2) #define DWC2_PCGCCTL_PWRCLMP_OFFSET 2 -#define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3) +#define DWC2_PCGCCTL_RSTPDWNMODULE BIT(3) #define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3 -#define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4) +#define DWC2_PCGCCTL_PHYSUSPENDED BIT(4) #define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4 -#define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5) +#define DWC2_PCGCCTL_ENBL_SLEEP_GATING BIT(5) #define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5 -#define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6) +#define DWC2_PCGCCTL_PHY_IN_SLEEP BIT(6) #define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6 -#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7) +#define DWC2_PCGCCTL_DEEP_SLEEP BIT(7) #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7 #define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) #define DWC2_SNPSID_DEVID_MASK (0xfffff << 12) @@ -744,11 +744,11 @@ struct dwc2_core_regs { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* roothub.b masks */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index bd9861d..82eb194 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1326,12 +1326,12 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, qh->qh_endpt1 = cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ - (1 << 14) | + BIT(14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ (usb_pipedevice(pipe) << 0)); - qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ - (1 << 0)); /* S-mask: microframe 0 */ + qh->qh_endpt2 = cpu_to_hc32(BIT(30) | /* 1 Tx per mframe */ + BIT(0)); /* S-mask: microframe 0 */ if (dev->speed == USB_SPEED_LOW || dev->speed == USB_SPEED_FULL) { /* C-mask: microframes 2-4 */ diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index d319962..24f3abd 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -33,49 +33,49 @@ /* USB_CTRL */ /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) +#define MXC_OTG_UCTRL_OWIE_BIT BIT(27) /* OTG power mask */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) +#define MXC_OTG_UCTRL_OPM_BIT BIT(24) /* OTG power pin polarity */ -#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) +#define MXC_OTG_UCTRL_O_PWR_POL_BIT BIT(24) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) +#define MXC_H1_UCTRL_H1UIE_BIT BIT(12) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) +#define MXC_H1_UCTRL_H1WIE_BIT BIT(11) /* HOST1 power mask */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) +#define MXC_H1_UCTRL_H1PM_BIT BIT(8) /* HOST1 power pin polarity */ -#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) +#define MXC_H1_UCTRL_H1_PWR_POL_BIT BIT(8) /* USB_PHY_CTRL_FUNC */ /* OTG Polarity of Overcurrent */ -#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) +#define MXC_OTG_PHYCTRL_OC_POL_BIT BIT(9) /* OTG Disable Overcurrent Event */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) +#define MXC_OTG_PHYCTRL_OC_DIS_BIT BIT(8) /* UH1 Polarity of Overcurrent */ -#define MXC_H1_OC_POL_BIT (1 << 6) +#define MXC_H1_OC_POL_BIT BIT(6) /* UH1 Disable Overcurrent Event */ -#define MXC_H1_OC_DIS_BIT (1 << 5) +#define MXC_H1_OC_DIS_BIT BIT(5) /* OTG Power Pin Polarity */ -#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) +#define MXC_OTG_PHYCTRL_PWR_POL_BIT BIT(3) /* USBH2CTRL */ -#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) -#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) -#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) +#define MXC_H2_UCTRL_H2_OC_POL_BIT BIT(31) +#define MXC_H2_UCTRL_H2_OC_DIS_BIT BIT(30) +#define MXC_H2_UCTRL_H2UIE_BIT BIT(8) +#define MXC_H2_UCTRL_H2WIE_BIT BIT(7) +#define MXC_H2_UCTRL_H2PM_BIT BIT(4) +#define MXC_H2_UCTRL_H2_PWR_POL_BIT BIT(4) /* USBH3CTRL */ -#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) -#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) -#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) -#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) -#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) +#define MXC_H3_UCTRL_H3_OC_POL_BIT BIT(31) +#define MXC_H3_UCTRL_H3_OC_DIS_BIT BIT(30) +#define MXC_H3_UCTRL_H3UIE_BIT BIT(8) +#define MXC_H3_UCTRL_H3WIE_BIT BIT(7) +#define MXC_H3_UCTRL_H3_PWR_POL_BIT BIT(4) /* USB_CTRL_1 */ -#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define MXC_USB_CTRL_UH1_EXT_CLK_EN BIT(25) int mxc_set_usbcontrol(int port, unsigned int flags) { diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 951dd3b..2519e9d 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -46,12 +46,12 @@ #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ -#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ +#define UCTRL_OVER_CUR_POL BIT(8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS BIT(7) /* Disable OTG Overcurrent Detection */ /* USBCMD */ -#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ -#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_RUN_STOP BIT(0) /* controller run/stop */ +#define UCMD_RESET BIT(1) /* controller reset */ static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index f09c75a..64d906c 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -18,49 +18,49 @@ #define MX25_OTG_SIC_SHIFT 29 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) +#define MX25_OTG_PM_BIT BIT(24) +#define MX25_OTG_PP_BIT BIT(11) +#define MX25_OTG_OCPOL_BIT BIT(3) #define MX25_H1_SIC_SHIFT 21 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) +#define MX25_H1_PP_BIT BIT(18) +#define MX25_H1_PM_BIT BIT(16) +#define MX25_H1_IPPUE_UP_BIT BIT(7) +#define MX25_H1_IPPUE_DOWN_BIT BIT(6) +#define MX25_H1_TLL_BIT BIT(5) +#define MX25_H1_USBTE_BIT BIT(4) +#define MX25_H1_OCPOL_BIT BIT(2) #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) +#define MX31_OTG_PM_BIT BIT(24) #define MX31_H2_SIC_SHIFT 21 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) +#define MX31_H2_PM_BIT BIT(16) +#define MX31_H2_DT_BIT BIT(5) #define MX31_H1_SIC_SHIFT 13 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) +#define MX31_H1_PM_BIT BIT(8) +#define MX31_H1_DT_BIT BIT(4) #define MX35_OTG_SIC_SHIFT 29 #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) +#define MX35_OTG_PM_BIT BIT(24) +#define MX35_OTG_PP_BIT BIT(11) +#define MX35_OTG_OCPOL_BIT BIT(3) #define MX35_H1_SIC_SHIFT 21 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) +#define MX35_H1_PP_BIT BIT(18) +#define MX35_H1_PM_BIT BIT(16) +#define MX35_H1_IPPUE_UP_BIT BIT(7) +#define MX35_H1_IPPUE_DOWN_BIT BIT(6) +#define MX35_H1_TLL_BIT BIT(5) +#define MX35_H1_USBTE_BIT BIT(4) +#define MX35_H1_OCPOL_BIT BIT(2) static int mxc_set_usbcontrol(int port, unsigned int flags) { @@ -217,7 +217,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, (struct clock_control_regs *)CCM_BASE; __raw_readl(&sc_regs->ccmr); - __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; + __raw_writel(__raw_readl(&sc_regs->ccmr) | BIT(9), &sc_regs->ccmr) ; #endif udelay(80); diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 6b8d969..9478e40 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -16,8 +16,8 @@ /* This DIGCTL register ungates clock to USB */ #define HW_DIGCTL_CTRL 0x8001c000 -#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) -#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) +#define HW_DIGCTL_CTRL_USB0_CLKGATE BIT(2) +#define HW_DIGCTL_CTRL_USB1_CLKGATE BIT(16) struct ehci_mxs_port { uint32_t usb_regs; diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 5454855..39dc0fe 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -23,14 +23,14 @@ #define USB_NC_REG_OFFSET 0x00000800 -#define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6) +#define ANADIG_PLL_CTRL_EN_USB_CLKS BIT(6) -#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ -#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ +#define UCTRL_OVER_CUR_POL BIT(8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS BIT(7) /* Disable OTG Overcurrent Detection */ /* USBCMD */ -#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ -#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_RUN_STOP BIT(0) /* controller run/stop */ +#define UCMD_RESET BIT(1) /* controller reset */ static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 774282d..561d0e3 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -36,8 +36,8 @@ struct ehci_hccr { #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) #define HC_VERSION(p) (((p) >> 16) & 0xffff) uint32_t cr_hcsparams; -#define HCS_PPC(p) ((p) & (1 << 4)) -#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ +#define HCS_PPC(p) ((p) & BIT(4)) +#define HCS_INDICATOR(p) ((p) & BIT(16)) /* Port indicators */ #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) uint32_t cr_hccparams; uint8_t cr_hcsp_portrt[8]; @@ -45,24 +45,24 @@ struct ehci_hccr { struct ehci_hcor { uint32_t or_usbcmd; -#define CMD_PARK (1 << 11) /* enable "park" */ +#define CMD_PARK BIT(11) /* enable "park" */ #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ -#define CMD_LRESET (1 << 7) /* partial reset */ -#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ -#define CMD_ASE (1 << 5) /* async schedule enable */ -#define CMD_PSE (1 << 4) /* periodic schedule enable */ -#define CMD_RESET (1 << 1) /* reset HC not bus */ -#define CMD_RUN (1 << 0) /* start/stop HC */ +#define CMD_LRESET BIT(7) /* partial reset */ +#define CMD_IAAD BIT(6) /* "doorbell" interrupt */ +#define CMD_ASE BIT(5) /* async schedule enable */ +#define CMD_PSE BIT(4) /* periodic schedule enable */ +#define CMD_RESET BIT(1) /* reset HC not bus */ +#define CMD_RUN BIT(0) /* start/stop HC */ uint32_t or_usbsts; -#define STS_ASS (1 << 15) -#define STS_PSS (1 << 14) -#define STS_HALT (1 << 12) +#define STS_ASS BIT(15) +#define STS_PSS BIT(14) +#define STS_HALT BIT(12) uint32_t or_usbintr; -#define INTR_UE (1 << 0) /* USB interrupt enable */ -#define INTR_UEE (1 << 1) /* USB error interrupt enable */ -#define INTR_PCE (1 << 2) /* Port change detect enable */ -#define INTR_SEE (1 << 4) /* system error enable */ -#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ +#define INTR_UE BIT(0) /* USB interrupt enable */ +#define INTR_UEE BIT(1) /* USB error interrupt enable */ +#define INTR_PCE BIT(2) /* Port change detect enable */ +#define INTR_SEE BIT(4) /* system error enable */ +#define INTR_AAE BIT(5) /* Interrupt on async adavance enable */ uint32_t or_frindex; uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; @@ -74,7 +74,7 @@ struct ehci_hcor { #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) uint32_t _reserved_1_[6]; uint32_t or_configflag; -#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ +#define FLAG_CF BIT(0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; #define PORTSC_PSPD(x) (((x) >> 26) & 0x3) #define PORTSC_PSPD_FS 0x0 @@ -84,8 +84,8 @@ struct ehci_hcor { } __attribute__ ((packed, aligned(4))); #define USBMODE 0x68 /* USB Device mode */ -#define USBMODE_SDIS (1 << 3) /* Stream disable */ -#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ +#define USBMODE_SDIS BIT(3) /* Stream disable */ +#define USBMODE_BE BIT(2) /* BE/LE endiannes select */ #define USBMODE_CM_HC (3 << 0) /* host controller mode */ #define USBMODE_CM_IDLE (0 << 0) /* idle state */ @@ -131,24 +131,24 @@ struct usb_linux_config_descriptor { #define cpu_to_hc32(x) cpu_to_le32((x)) #endif -#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ -#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ -#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ -#define EHCI_PS_PO (1 << 13) /* RW port owner */ -#define EHCI_PS_PP (1 << 12) /* RW,RO port power */ +#define EHCI_PS_WKOC_E BIT(22) /* RW wake on over current */ +#define EHCI_PS_WKDSCNNT_E BIT(21) /* RW wake on disconnect */ +#define EHCI_PS_WKCNNT_E BIT(20) /* RW wake on connect */ +#define EHCI_PS_PO BIT(13) /* RW port owner */ +#define EHCI_PS_PP BIT(12) /* RW,RO port power */ #define EHCI_PS_LS (3 << 10) /* RO line status */ -#define EHCI_PS_PR (1 << 8) /* RW port reset */ -#define EHCI_PS_SUSP (1 << 7) /* RW suspend */ -#define EHCI_PS_FPR (1 << 6) /* RW force port resume */ -#define EHCI_PS_OCC (1 << 5) /* RWC over current change */ -#define EHCI_PS_OCA (1 << 4) /* RO over current active */ -#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ -#define EHCI_PS_PE (1 << 2) /* RW port enable */ -#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ -#define EHCI_PS_CS (1 << 0) /* RO connect status */ +#define EHCI_PS_PR BIT(8) /* RW port reset */ +#define EHCI_PS_SUSP BIT(7) /* RW suspend */ +#define EHCI_PS_FPR BIT(6) /* RW force port resume */ +#define EHCI_PS_OCC BIT(5) /* RWC over current change */ +#define EHCI_PS_OCA BIT(4) /* RO over current active */ +#define EHCI_PS_PEC BIT(3) /* RWC port enable change */ +#define EHCI_PS_PE BIT(2) /* RW port enable */ +#define EHCI_PS_CSC BIT(1) /* RWC connect status change */ +#define EHCI_PS_CS BIT(0) /* RO connect status */ #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) -#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) +#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == BIT(10)) /* * Schedule Interface Space. diff --git a/drivers/usb/host/isp116x.h b/drivers/usb/host/isp116x.h index 5b7afaf..e29e496 100644 --- a/drivers/usb/host/isp116x.h +++ b/drivers/usb/host/isp116x.h @@ -66,24 +66,24 @@ #define HCCONTROL_HCFS (3 << 6) /* host controller functional state */ #define HCCONTROL_USB_RESET (0 << 6) -#define HCCONTROL_USB_RESUME (1 << 6) +#define HCCONTROL_USB_RESUME BIT(6) #define HCCONTROL_USB_OPER (2 << 6) #define HCCONTROL_USB_SUSPEND (3 << 6) -#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */ -#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */ +#define HCCONTROL_RWC BIT(9) /* remote wakeup connected */ +#define HCCONTROL_RWE BIT(10) /* remote wakeup enable */ #define HCCMDSTAT 0x02 -#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */ +#define HCCMDSTAT_HCR BIT(0) /* host controller reset */ #define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */ #define HCINTSTAT 0x03 -#define HCINT_SO (1 << 0) /* scheduling overrun */ -#define HCINT_WDH (1 << 1) /* writeback of done_head */ -#define HCINT_SF (1 << 2) /* start frame */ -#define HCINT_RD (1 << 3) /* resume detect */ -#define HCINT_UE (1 << 4) /* unrecoverable error */ -#define HCINT_FNO (1 << 5) /* frame number overflow */ -#define HCINT_RHSC (1 << 6) /* root hub status change */ -#define HCINT_OC (1 << 30) /* ownership change */ -#define HCINT_MIE (1 << 31) /* master interrupt enable */ +#define HCINT_SO BIT(0) /* scheduling overrun */ +#define HCINT_WDH BIT(1) /* writeback of done_head */ +#define HCINT_SF BIT(2) /* start frame */ +#define HCINT_RD BIT(3) /* resume detect */ +#define HCINT_UE BIT(4) /* unrecoverable error */ +#define HCINT_FNO BIT(5) /* frame number overflow */ +#define HCINT_RHSC BIT(6) /* root hub status change */ +#define HCINT_OC BIT(30) /* ownership change */ +#define HCINT_MIE BIT(31) /* master interrupt enable */ #define HCINTENB 0x04 #define HCINTDIS 0x05 #define HCFMINTVL 0x0d @@ -92,77 +92,77 @@ #define HCLSTHRESH 0x11 #define HCRHDESCA 0x12 #define RH_A_NDP (0x3 << 0) /* # downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* overcurrent protection +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* overcurrent protection mode */ -#define RH_A_NOCP (1 << 12) /* no overcurrent protection */ +#define RH_A_NOCP BIT(12) /* no overcurrent protection */ #define RH_A_POTPGT (0xff << 24) /* power on -> power good time */ #define HCRHDESCB 0x13 #define RH_B_DR (0xffff << 0) /* device removable flags */ #define RH_B_PPCM (0xffff << 16) /* port power control mask */ #define HCRHSTATUS 0x14 -#define RH_HS_LPS (1 << 0) /* local power status */ -#define RH_HS_OCI (1 << 1) /* over current indicator */ -#define RH_HS_DRWE (1 << 15) /* device remote wakeup +#define RH_HS_LPS BIT(0) /* local power status */ +#define RH_HS_OCI BIT(1) /* over current indicator */ +#define RH_HS_DRWE BIT(15) /* device remote wakeup enable */ -#define RH_HS_LPSC (1 << 16) /* local power status change */ -#define RH_HS_OCIC (1 << 17) /* over current indicator +#define RH_HS_LPSC BIT(16) /* local power status change */ +#define RH_HS_OCIC BIT(17) /* over current indicator change */ -#define RH_HS_CRWE (1 << 31) /* clear remote wakeup +#define RH_HS_CRWE BIT(31) /* clear remote wakeup enable */ #define HCRHPORT1 0x15 -#define RH_PS_CCS (1 << 0) /* current connect status */ -#define RH_PS_PES (1 << 1) /* port enable status */ -#define RH_PS_PSS (1 << 2) /* port suspend status */ -#define RH_PS_POCI (1 << 3) /* port over current +#define RH_PS_CCS BIT(0) /* current connect status */ +#define RH_PS_PES BIT(1) /* port enable status */ +#define RH_PS_PSS BIT(2) /* port suspend status */ +#define RH_PS_POCI BIT(3) /* port over current indicator */ -#define RH_PS_PRS (1 << 4) /* port reset status */ -#define RH_PS_PPS (1 << 8) /* port power status */ -#define RH_PS_LSDA (1 << 9) /* low speed device attached */ -#define RH_PS_CSC (1 << 16) /* connect status change */ -#define RH_PS_PESC (1 << 17) /* port enable status change */ -#define RH_PS_PSSC (1 << 18) /* port suspend status +#define RH_PS_PRS BIT(4) /* port reset status */ +#define RH_PS_PPS BIT(8) /* port power status */ +#define RH_PS_LSDA BIT(9) /* low speed device attached */ +#define RH_PS_CSC BIT(16) /* connect status change */ +#define RH_PS_PESC BIT(17) /* port enable status change */ +#define RH_PS_PSSC BIT(18) /* port suspend status change */ -#define RH_PS_OCIC (1 << 19) /* over current indicator +#define RH_PS_OCIC BIT(19) /* over current indicator change */ -#define RH_PS_PRSC (1 << 20) /* port reset status change */ +#define RH_PS_PRSC BIT(20) /* port reset status change */ #define HCRHPORT_CLRMASK (0x1f << 16) #define HCRHPORT2 0x16 #define HCHWCFG 0x20 -#define HCHWCFG_15KRSEL (1 << 12) -#define HCHWCFG_CLKNOTSTOP (1 << 11) -#define HCHWCFG_ANALOG_OC (1 << 10) -#define HCHWCFG_DACK_MODE (1 << 8) -#define HCHWCFG_EOT_POL (1 << 7) -#define HCHWCFG_DACK_POL (1 << 6) -#define HCHWCFG_DREQ_POL (1 << 5) +#define HCHWCFG_15KRSEL BIT(12) +#define HCHWCFG_CLKNOTSTOP BIT(11) +#define HCHWCFG_ANALOG_OC BIT(10) +#define HCHWCFG_DACK_MODE BIT(8) +#define HCHWCFG_EOT_POL BIT(7) +#define HCHWCFG_DACK_POL BIT(6) +#define HCHWCFG_DREQ_POL BIT(5) #define HCHWCFG_DBWIDTH_MASK (0x03 << 3) #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) -#define HCHWCFG_INT_POL (1 << 2) -#define HCHWCFG_INT_TRIGGER (1 << 1) -#define HCHWCFG_INT_ENABLE (1 << 0) +#define HCHWCFG_INT_POL BIT(2) +#define HCHWCFG_INT_TRIGGER BIT(1) +#define HCHWCFG_INT_ENABLE BIT(0) #define HCDMACFG 0x21 #define HCDMACFG_BURST_LEN_MASK (0x03 << 5) #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) -#define HCDMACFG_DMA_ENABLE (1 << 4) +#define HCDMACFG_DMA_ENABLE BIT(4) #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) -#define HCDMACFG_CTR_SEL (1 << 2) -#define HCDMACFG_ITLATL_SEL (1 << 1) -#define HCDMACFG_DMA_RW_SELECT (1 << 0) +#define HCDMACFG_CTR_SEL BIT(2) +#define HCDMACFG_ITLATL_SEL BIT(1) +#define HCDMACFG_DMA_RW_SELECT BIT(0) #define HCXFERCTR 0x22 #define HCuPINT 0x24 -#define HCuPINT_SOF (1 << 0) -#define HCuPINT_ATL (1 << 1) -#define HCuPINT_AIIEOT (1 << 2) -#define HCuPINT_OPR (1 << 4) -#define HCuPINT_SUSP (1 << 5) -#define HCuPINT_CLKRDY (1 << 6) +#define HCuPINT_SOF BIT(0) +#define HCuPINT_ATL BIT(1) +#define HCuPINT_AIIEOT BIT(2) +#define HCuPINT_OPR BIT(4) +#define HCuPINT_SUSP BIT(5) +#define HCuPINT_CLKRDY BIT(6) #define HCuPINTENB 0x25 #define HCCHIPID 0x27 #define HCCHIPID_MASK 0xff00 @@ -173,12 +173,12 @@ #define HCITLBUFLEN 0x2a #define HCATLBUFLEN 0x2b #define HCBUFSTAT 0x2c -#define HCBUFSTAT_ITL0_FULL (1 << 0) -#define HCBUFSTAT_ITL1_FULL (1 << 1) -#define HCBUFSTAT_ATL_FULL (1 << 2) -#define HCBUFSTAT_ITL0_DONE (1 << 3) -#define HCBUFSTAT_ITL1_DONE (1 << 4) -#define HCBUFSTAT_ATL_DONE (1 << 5) +#define HCBUFSTAT_ITL0_FULL BIT(0) +#define HCBUFSTAT_ITL1_FULL BIT(1) +#define HCBUFSTAT_ATL_FULL BIT(2) +#define HCBUFSTAT_ITL0_DONE BIT(3) +#define HCBUFSTAT_ITL1_DONE BIT(4) +#define HCBUFSTAT_ATL_DONE BIT(5) #define HCRDITL0LEN 0x2d #define HCRDITL1LEN 0x2e #define HCITLPORT 0x40 @@ -238,13 +238,13 @@ struct ptd { u16 count; #define PTD_COUNT_MSK (0x3ff << 0) -#define PTD_TOGGLE_MSK (1 << 10) -#define PTD_ACTIVE_MSK (1 << 11) +#define PTD_TOGGLE_MSK BIT(10) +#define PTD_ACTIVE_MSK BIT(11) #define PTD_CC_MSK (0xf << 12) u16 mps; #define PTD_MPS_MSK (0x3ff << 0) -#define PTD_SPD_MSK (1 << 10) -#define PTD_LAST_MSK (1 << 11) +#define PTD_SPD_MSK BIT(10) +#define PTD_LAST_MSK BIT(11) #define PTD_EP_MSK (0xf << 12) u16 len; #define PTD_LEN_MSK (0x3ff << 0) @@ -252,10 +252,10 @@ struct ptd { #define PTD_DIR_SETUP (0) #define PTD_DIR_OUT (1) #define PTD_DIR_IN (2) -#define PTD_B5_5_MSK (1 << 13) +#define PTD_B5_5_MSK BIT(13) u16 faddr; #define PTD_FA_MSK (0x7f << 0) -#define PTD_FMT_MSK (1 << 7) +#define PTD_FMT_MSK BIT(7) } __attribute__ ((packed, aligned(2))); struct isp116x_ep { diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c index 8bb2275..1d9ab09 100644 --- a/drivers/usb/host/ohci-s3c24xx.c +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -1555,13 +1555,13 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); + clk_power->upllcon = ((40 << 12) + BIT(4) + 2); gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ /* * Enable USB host clock. */ - clk_power->clkcon |= (1 << 4); + clk_power->clkcon |= BIT(4); memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1598,7 +1598,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); + clk_power->clkcon &= ~BIT(4); return -1; } @@ -1611,7 +1611,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); + clk_power->clkcon &= ~BIT(4); return -1; } #ifdef DEBUG @@ -1637,7 +1637,7 @@ int usb_lowlevel_stop(int index) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->clkcon &= ~(1 << 4); + clk_power->clkcon &= ~BIT(4); return 0; } @@ -1656,14 +1656,14 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + writel((40 << 12) + BIT(4) + 2, &clk_power->upllcon); /* 1 = use pads related USB for USB host */ writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); + writel(readl(&clk_power->clkcon) | BIT(4), &clk_power->clkcon); return 0; } @@ -1672,14 +1672,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + writel(readl(&clk_power->clkcon) & ~BIT(4), &clk_power->clkcon); return 0; } int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + writel(readl(&clk_power->clkcon) & ~BIT(4), &clk_power->clkcon); return 0; } diff --git a/drivers/usb/host/ohci-s3c24xx.h b/drivers/usb/host/ohci-s3c24xx.h index f272d78..3d55f98 100644 --- a/drivers/usb/host/ohci-s3c24xx.h +++ b/drivers/usb/host/ohci-s3c24xx.h @@ -113,7 +113,7 @@ struct td { __u32 unused2[2]; } __attribute__ ((aligned(32))); -#define OHCI_ED_SKIP (1 << 14) +#define OHCI_ED_SKIP BIT(14) /* * The HCCA (Host Controller Communications Area) is a 256 byte @@ -177,28 +177,28 @@ struct ohci_regs { * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_PLE BIT(2) /* periodic list enable */ +#define OHCI_CTRL_IE BIT(3) /* isochronous enable */ +#define OHCI_CTRL_CLE BIT(4) /* control list enable */ +#define OHCI_CTRL_BLE BIT(5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ +#define OHCI_CTRL_IR BIT(8) /* interrupt routing */ +#define OHCI_CTRL_RWC BIT(9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE BIT(10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_RESUME BIT(6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_HCR BIT(0) /* host controller reset */ +#define OHCI_CLF BIT(1) /* control list filled */ +#define OHCI_BLF BIT(2) /* bulk list filled */ +#define OHCI_OCR BIT(3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* @@ -207,15 +207,15 @@ struct ohci_regs { * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ +#define OHCI_INTR_SO BIT(0) /* scheduling overrun */ +#define OHCI_INTR_WDH BIT(1) /* writeback of done_head */ +#define OHCI_INTR_SF BIT(2) /* start frame */ +#define OHCI_INTR_RD BIT(3) /* resume detect */ +#define OHCI_INTR_UE BIT(4) /* unrecoverable error */ +#define OHCI_INTR_FNO BIT(5) /* frame number overflow */ +#define OHCI_INTR_RHSC BIT(6) /* root hub status change */ +#define OHCI_INTR_OC BIT(30) /* ownership change */ +#define OHCI_INTR_MIE BIT(31) /* master interrupt enable */ /* Virtual Root HUB */ struct virt_root_hub { @@ -310,11 +310,11 @@ struct virt_root_hub { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index 9a4a2c2..bde8742 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -172,7 +172,7 @@ struct td { } __attribute__((aligned(32))); typedef struct td td_t; -#define OHCI_ED_SKIP (1 << 14) +#define OHCI_ED_SKIP BIT(14) /* * The HCCA (Host Controller Communications Area) is a 256 byte @@ -240,7 +240,7 @@ struct ohci_regs { /* Some EHCI controls */ #define EHCI_USBCMD_OFF 0x20 -#define EHCI_USBCMD_HCRESET (1 << 1) +#define EHCI_USBCMD_HCRESET BIT(1) /* OHCI CONTROL AND STATUS REGISTER MASKS */ @@ -248,28 +248,28 @@ struct ohci_regs { * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_PLE BIT(2) /* periodic list enable */ +#define OHCI_CTRL_IE BIT(3) /* isochronous enable */ +#define OHCI_CTRL_CLE BIT(4) /* control list enable */ +#define OHCI_CTRL_BLE BIT(5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ +#define OHCI_CTRL_IR BIT(8) /* interrupt routing */ +#define OHCI_CTRL_RWC BIT(9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE BIT(10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_RESUME BIT(6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_HCR BIT(0) /* host controller reset */ +#define OHCI_CLF BIT(1) /* control list filled */ +#define OHCI_BLF BIT(2) /* bulk list filled */ +#define OHCI_OCR BIT(3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* @@ -278,15 +278,15 @@ struct ohci_regs { * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ +#define OHCI_INTR_SO BIT(0) /* scheduling overrun */ +#define OHCI_INTR_WDH BIT(1) /* writeback of done_head */ +#define OHCI_INTR_SF BIT(2) /* start frame */ +#define OHCI_INTR_RD BIT(3) /* resume detect */ +#define OHCI_INTR_UE BIT(4) /* unrecoverable error */ +#define OHCI_INTR_FNO BIT(5) /* frame number overflow */ +#define OHCI_INTR_RHSC BIT(6) /* root hub status change */ +#define OHCI_INTR_OC BIT(30) /* ownership change */ +#define OHCI_INTR_MIE BIT(31) /* master interrupt enable */ /* Virtual Root HUB */ @@ -382,11 +382,11 @@ struct virt_root_hub { /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index ca1b671..2c06d8e 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -649,11 +649,11 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ #endif /* __R8A66597_H__ */ diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c index e0ef322..e71922e 100644 --- a/drivers/usb/host/xhci-uniphier.c +++ b/drivers/usb/host/xhci-uniphier.c @@ -36,8 +36,8 @@ static int get_uniphier_xhci_base(int index, struct xhci_hccr **base) } #define USB3_RST_CTRL 0x00100040 -#define IOMMU_RST_N (1 << 5) -#define LINK_RST_N (1 << 4) +#define IOMMU_RST_N BIT(5) +#define LINK_RST_N BIT(4) static void uniphier_xhci_reset(void __iomem *base, int on) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2afa386..886acbc 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -44,18 +44,18 @@ * connect status and port speed are also sticky - meaning they're in * the AUX well and they aren't changed by a hot, warm, or cold reset. */ -#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) +#define XHCI_PORT_RO (BIT(0) | BIT(3) | (0xf << 10) | BIT(30)) /* * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: * bits 5:8, 9, 14:15, 25:27 * link state, port power, port indicator state, "wake on" enable state */ -#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) +#define XHCI_PORT_RWS ((0xf << 5) | BIT(9) | (0x3 << 14) | (0x7 << 25)) /* * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: * bit 4 (port reset) */ -#define XHCI_PORT_RW1S ((1 << 4)) +#define XHCI_PORT_RW1S (BIT(4)) /* * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: * bits 1, 17, 18, 19, 20, 21, 22, 23 @@ -64,17 +64,17 @@ * warm port reset changed (reserved zero for USB 2.0 ports), * over-current, reset, link state, and L1 change */ -#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) +#define XHCI_PORT_RW1CS (BIT(1) | (0x7f << 17)) /* * Bit 16 is RW, and writing a '1' to it causes the link state control to be * latched in */ -#define XHCI_PORT_RW ((1 << 16)) +#define XHCI_PORT_RW (BIT(16)) /* * These bits are Reserved Zero (RsvdZ) and zero should be written to them: * bits 2, 24, 28:31 */ -#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) +#define XHCI_PORT_RZ (BIT(2) | BIT(24) | (0xf << 28)) /* * XHCI Register Space. @@ -123,23 +123,23 @@ struct xhci_hccr { /* HCCPARAMS - hcc_params - bitmasks */ /* true: HC can use 64-bit address pointers */ -#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) +#define HCC_64BIT_ADDR(p) ((p) & BIT(0)) /* true: HC can do bandwidth negotiation */ -#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) +#define HCC_BANDWIDTH_NEG(p) ((p) & BIT(1)) /* true: HC uses 64-byte Device Context structures * FIXME 64-byte context structures aren't supported yet. */ -#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) +#define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2)) /* true: HC has port power switches */ -#define HCC_PPC(p) ((p) & (1 << 3)) +#define HCC_PPC(p) ((p) & BIT(3)) /* true: HC has port indicators */ -#define HCS_INDICATOR(p) ((p) & (1 << 4)) +#define HCS_INDICATOR(p) ((p) & BIT(4)) /* true: HC has Light HC Reset Capability */ -#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) +#define HCC_LIGHT_RESET(p) ((p) & BIT(5)) /* true: HC supports latency tolerance messaging */ -#define HCC_LTC(p) ((p) & (1 << 6)) +#define HCC_LTC(p) ((p) & BIT(6)) /* true: no secondary Stream ID Support */ -#define HCC_NSS(p) ((p) & (1 << 7)) +#define HCC_NSS(p) ((p) & BIT(7)) /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) /* Extended Capabilities pointer from PCI base - section 5.3.6 */ @@ -183,17 +183,17 @@ struct xhci_hcor { * PCI config regs). HC does NOT drive a USB reset on the downstream ports. * The xHCI driver must reinitialize the xHC after setting this bit. */ -#define CMD_RESET (1 << 1) +#define CMD_RESET BIT(1) /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ #define CMD_EIE XHCI_CMD_EIE /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ #define CMD_HSEIE XHCI_CMD_HSEIE /* bits 4:6 are reserved (and should be preserved on writes). */ /* light reset (port status stays unchanged) - reset completed when this is 0 */ -#define CMD_LRESET (1 << 7) +#define CMD_LRESET BIT(7) /* host controller save/restore state. */ -#define CMD_CSS (1 << 8) -#define CMD_CRS (1 << 9) +#define CMD_CSS BIT(8) +#define CMD_CRS BIT(9) /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ #define CMD_EWE XHCI_CMD_EWE /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root @@ -201,29 +201,29 @@ struct xhci_hcor { * '0' means the xHC can power it off if all ports are in the disconnect, * disabled, or powered-off state. */ -#define CMD_PM_INDEX (1 << 11) +#define CMD_PM_INDEX BIT(11) /* bits 12:31 are reserved (and should be preserved on writes). */ /* USBSTS - USB status - status bitmasks */ /* HC not running - set to 1 when run/stop bit is cleared. */ #define STS_HALT XHCI_STS_HALT /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ -#define STS_FATAL (1 << 2) +#define STS_FATAL BIT(2) /* event interrupt - clear this prior to clearing any IP flags in IR set*/ -#define STS_EINT (1 << 3) +#define STS_EINT BIT(3) /* port change detect */ -#define STS_PORT (1 << 4) +#define STS_PORT BIT(4) /* bits 5:7 reserved and zeroed */ /* save state status - '1' means xHC is saving state */ -#define STS_SAVE (1 << 8) +#define STS_SAVE BIT(8) /* restore state status - '1' means xHC is restoring state */ -#define STS_RESTORE (1 << 9) +#define STS_RESTORE BIT(9) /* true: save or restore error */ -#define STS_SRE (1 << 10) +#define STS_SRE BIT(10) /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ #define STS_CNR XHCI_STS_CNR /* true: internal Host Controller Error - SW needs to reset and reinitialize */ -#define STS_HCE (1 << 12) +#define STS_HCE BIT(12) /* bits 13:31 reserved and should be preserved */ /* @@ -241,11 +241,11 @@ struct xhci_hcor { /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ /* bit 0 is the command ring cycle state */ /* stop ring operation after completion of the currently executing command */ -#define CMD_RING_PAUSE (1 << 1) +#define CMD_RING_PAUSE BIT(1) /* stop ring immediately - abort the currently executing command */ -#define CMD_RING_ABORT (1 << 2) +#define CMD_RING_ABORT BIT(2) /* true: command ring is running */ -#define CMD_RING_RUNNING (1 << 3) +#define CMD_RING_RUNNING BIT(3) /* bits 4:5 reserved and should be preserved */ /* Command Ring pointer - bit mask for the lower 32 bits. */ #define CMD_RING_RSVD_BITS (0x3f) @@ -257,14 +257,14 @@ struct xhci_hcor { /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ /* true: device connected */ -#define PORT_CONNECT (1 << 0) +#define PORT_CONNECT BIT(0) /* true: port enabled */ -#define PORT_PE (1 << 1) +#define PORT_PE BIT(1) /* bit 2 reserved and zeroed */ /* true: port has an over-current condition */ -#define PORT_OC (1 << 3) +#define PORT_OC BIT(3) /* true: port reset signaling asserted */ -#define PORT_RESET (1 << 4) +#define PORT_RESET BIT(4) /* Port Link State - bits 5:8 * A read gives the current link PM state of the port, * a write with Link State Write Strobe set sets the link state. @@ -275,7 +275,7 @@ struct xhci_hcor { #define XDEV_U3 (0x3 << 5) #define XDEV_RESUME (0xf << 5) /* true: port has power (see HCC_PPC) */ -#define PORT_POWER (1 << 9) +#define PORT_POWER BIT(9) /* bits 10:13 indicate device speed: * 0 - undefined speed - port hasn't be initialized by a reset yet * 1 - full speed @@ -301,25 +301,25 @@ struct xhci_hcor { #define SLOT_SPEED_SS (XDEV_SS << 10) /* Port Indicator Control */ #define PORT_LED_OFF (0 << 14) -#define PORT_LED_AMBER (1 << 14) +#define PORT_LED_AMBER BIT(14) #define PORT_LED_GREEN (2 << 14) #define PORT_LED_MASK (3 << 14) /* Port Link State Write Strobe - set this when changing link state */ -#define PORT_LINK_STROBE (1 << 16) +#define PORT_LINK_STROBE BIT(16) /* true: connect status change */ -#define PORT_CSC (1 << 17) +#define PORT_CSC BIT(17) /* true: port enable change */ -#define PORT_PEC (1 << 18) +#define PORT_PEC BIT(18) /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port * into an enabled state, and the device into the default state. A "warm" reset * also resets the link, forcing the device through the link training sequence. * SW can also look at the Port Reset register to see when warm reset is done. */ -#define PORT_WRC (1 << 19) +#define PORT_WRC BIT(19) /* true: over-current change */ -#define PORT_OCC (1 << 20) +#define PORT_OCC BIT(20) /* true: reset change - 1 to 0 transition of PORT_RESET */ -#define PORT_RC (1 << 21) +#define PORT_RC BIT(21) /* port link status change - set on some port link state transitions: * Transition Reason * -------------------------------------------------------------------------- @@ -333,21 +333,21 @@ struct xhci_hcor { * - U0 to disabled L1 entry error with USB 2.1 device * - Any state to inactive Error on USB 3.0 port */ -#define PORT_PLC (1 << 22) +#define PORT_PLC BIT(22) /* port configure error change - port failed to configure its link partner */ -#define PORT_CEC (1 << 23) +#define PORT_CEC BIT(23) /* bit 24 reserved */ /* wake on connect (enable) */ -#define PORT_WKCONN_E (1 << 25) +#define PORT_WKCONN_E BIT(25) /* wake on disconnect (enable) */ -#define PORT_WKDISC_E (1 << 26) +#define PORT_WKDISC_E BIT(26) /* wake on over-current (enable) */ -#define PORT_WKOC_E (1 << 27) +#define PORT_WKOC_E BIT(27) /* bits 28:29 reserved */ /* true: device is removable - for USB 3.0 roothub emulation */ -#define PORT_DEV_REMOVE (1 << 30) +#define PORT_DEV_REMOVE BIT(30) /* Initiate a warm port reset - complete when PORT_WRC is '1' */ -#define PORT_WR (1 << 31) +#define PORT_WR BIT(31) /* We mark duplicate entries with -1 */ #define DUPLICATE_ENTRY ((u8)(-1)) @@ -364,11 +364,11 @@ struct xhci_hcor { /* USB2 Protocol PORTSPMSC */ #define PORT_L1S_MASK 7 #define PORT_L1S_SUCCESS 1 -#define PORT_RWE (1 << 3) +#define PORT_RWE BIT(3) #define PORT_HIRD(p) (((p) & 0xf) << 4) #define PORT_HIRD_MASK (0xf << 4) #define PORT_L1DS(p) (((p) & 0xff) << 8) -#define PORT_HLE (1 << 16) +#define PORT_HLE BIT(16) /** * struct xhci_intr_reg - Interrupt Register Set @@ -426,7 +426,7 @@ struct xhci_intr_reg { /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by * a work queue (or delayed service routine)? */ -#define ERST_EHB (1 << 3) +#define ERST_EHB BIT(3) #define ERST_PTR_MASK (0xf) /** @@ -530,8 +530,8 @@ struct xhci_slot_ctx { #define LAST_CTX_MASK (0x1f << 27) #define LAST_CTX(p) ((p) << 27) #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) -#define SLOT_FLAG (1 << 0) -#define EP0_FLAG (1 << 1) +#define SLOT_FLAG BIT(0) +#define EP0_FLAG BIT(1) /* dev_info2 bitmasks */ /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ @@ -627,7 +627,7 @@ struct xhci_ep_ctx { #define EP_MAXPSTREAMS_MASK (0x1f << 10) #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ -#define EP_HAS_LSA (1 << 15) +#define EP_HAS_LSA BIT(15) /* ep_info2 bitmasks */ /* @@ -670,7 +670,7 @@ struct xhci_ep_ctx { #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) /* deq bitmasks */ -#define EP_CTX_CYCLE_MASK (1 << 0) +#define EP_CTX_CYCLE_MASK BIT(0) /** @@ -830,7 +830,7 @@ struct xhci_event_cmd { #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) -#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) +#define TRB_TO_SUSPEND_PORT(p) (((p) & BIT(23)) >> 23) #define LAST_EP_INDEX 30 /* Set TR Dequeue Pointer command TRB fields */ @@ -885,7 +885,7 @@ struct xhci_event_cmd { #define TRB_DATA_IN 3 /* Isochronous TRB specific fields */ -#define TRB_SIA (1 << 31) +#define TRB_SIA BIT(31) struct xhci_generic_trb { volatile __le32 field[4]; @@ -1057,14 +1057,14 @@ struct xhci_erst { struct xhci_virt_ep { struct xhci_ring *ring; unsigned int ep_state; -#define SET_DEQ_PENDING (1 << 0) -#define EP_HALTED (1 << 1) /* For stall handling */ -#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ +#define SET_DEQ_PENDING BIT(0) +#define EP_HALTED BIT(1) /* For stall handling */ +#define EP_HALT_PENDING BIT(2) /* For URB cancellation */ /* Transitioning the endpoint to using streams, don't enqueue URBs */ -#define EP_GETTING_STREAMS (1 << 3) -#define EP_HAS_STREAMS (1 << 4) +#define EP_GETTING_STREAMS BIT(3) +#define EP_HAS_STREAMS BIT(4) /* Transitioning the endpoint to not using streams, don't enqueue URBs */ -#define EP_GETTING_NO_STREAMS (1 << 5) +#define EP_GETTING_NO_STREAMS BIT(5) }; #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) @@ -1144,7 +1144,7 @@ void xhci_hcd_stop(int index); /* Up to 16 ms to halt an HC */ #define XHCI_MAX_HALT_USEC (16*1000) /* HC not running - set to 1 when run/stop bit is cleared. */ -#define XHCI_STS_HALT (1 << 0) +#define XHCI_STS_HALT BIT(0) /* HCCPARAMS offset from PCI base address */ #define XHCI_HCC_PARAMS_OFFSET 0x10 @@ -1174,8 +1174,8 @@ void xhci_hcd_stop(int index); /* IDs 6-9 reserved */ #define XHCI_EXT_CAPS_DEBUG 10 /* USB Legacy Support Capability - section 7.1.1 */ -#define XHCI_HC_BIOS_OWNED (1 << 16) -#define XHCI_HC_OS_OWNED (1 << 24) +#define XHCI_HC_BIOS_OWNED BIT(16) +#define XHCI_HC_OS_OWNED BIT(24) /* USB Legacy Support Capability - section 7.1.1 */ /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ @@ -1188,25 +1188,25 @@ void xhci_hcd_stop(int index); #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ -#define XHCI_L1C (1 << 16) +#define XHCI_L1C BIT(16) /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ -#define XHCI_HLC (1 << 19) +#define XHCI_HLC BIT(19) /* command register values to disable interrupts and halt the HC */ /* start/stop HC execution - do not write unless HC is halted*/ -#define XHCI_CMD_RUN (1 << 0) +#define XHCI_CMD_RUN BIT(0) /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ -#define XHCI_CMD_EIE (1 << 2) +#define XHCI_CMD_EIE BIT(2) /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ -#define XHCI_CMD_HSEIE (1 << 3) +#define XHCI_CMD_HSEIE BIT(3) /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ -#define XHCI_CMD_EWE (1 << 10) +#define XHCI_CMD_EWE BIT(10) #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ -#define XHCI_STS_CNR (1 << 11) +#define XHCI_STS_CNR BIT(11) struct xhci_ctrl { #ifdef CONFIG_DM_USB diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h index 2695742..389d53e 100644 --- a/drivers/usb/musb-new/musb_core.h +++ b/drivers/usb/musb-new/musb_core.h @@ -344,7 +344,7 @@ struct musb { u16 hwvers; /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */ -#define MUSB_PORT_STAT_RESUME (1 << 31) +#define MUSB_PORT_STAT_RESUME BIT(31) u32 port1_status; diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 27e4ed4..36a4c20 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -76,9 +76,9 @@ #define MUSB_ULPI_USE_EXTVBUS 0x01 #define MUSB_ULPI_USE_EXTVBUSIND 0x02 /* ULPI_REG_CONTROL */ -#define MUSB_ULPI_REG_REQ (1 << 0) -#define MUSB_ULPI_REG_CMPLT (1 << 1) -#define MUSB_ULPI_RDN_WR (1 << 2) +#define MUSB_ULPI_REG_REQ BIT(0) +#define MUSB_ULPI_REG_CMPLT BIT(1) +#define MUSB_ULPI_RDN_WR BIT(2) /* TESTMODE */ #define MUSB_TEST_FORCE_HOST 0x80 diff --git a/drivers/usb/musb-new/omap2430.h b/drivers/usb/musb-new/omap2430.h index 3b795c2..beda587 100644 --- a/drivers/usb/musb-new/omap2430.h +++ b/drivers/usb/musb-new/omap2430.h @@ -33,24 +33,24 @@ # define NOIDLE (1 << SIDLEMODE) # define SMARTIDLE (2 << SIDLEMODE) -# define ENABLEWAKEUP (1 << 2) -# define SOFTRST (1 << 1) -# define AUTOIDLE (1 << 0) +# define ENABLEWAKEUP BIT(2) +# define SOFTRST BIT(1) +# define AUTOIDLE BIT(0) #define OTG_SYSSTATUS 0x408 -# define RESETDONE (1 << 0) +# define RESETDONE BIT(0) #define OTG_INTERFSEL 0x40c -# define EXTCP (1 << 2) +# define EXTCP BIT(2) # define PHYSEL 0 /* bit position */ # define UTMI_8BIT (0 << PHYSEL) # define ULPI_12PIN (1 << PHYSEL) # define ULPI_8PIN (2 << PHYSEL) #define OTG_SIMENABLE 0x410 -# define TM1 (1 << 0) +# define TM1 BIT(0) #define OTG_FORCESTDBY 0x414 -# define ENABLEFORCE (1 << 0) +# define ENABLEFORCE BIT(0) #endif /* __MUSB_OMAP243X_H__ */ diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index c9a6a16..1557109 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -174,7 +174,7 @@ static void USBC_ConfigFIFO_Base(void) /* config usb fifo, 8kb mode */ reg_value = readl(SUNXI_SRAMC_BASE + 0x04); reg_value &= ~(0x03 << 0); - reg_value |= (1 << 0); + reg_value |= BIT(0); writel(reg_value, SUNXI_SRAMC_BASE + 0x04); } diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index 62c3a6f..963abfe 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -76,9 +76,9 @@ int musb_platform_init(void) /* global usb reset */ sw_reset = readl(&am35x_scm_general_regs->ip_sw_reset); - sw_reset |= (1 << 0); + sw_reset |= BIT(0); writel(sw_reset, &am35x_scm_general_regs->ip_sw_reset); - sw_reset &= ~(1 << 0); + sw_reset &= ~BIT(0); writel(sw_reset, &am35x_scm_general_regs->ip_sw_reset); /* reset the controller */ diff --git a/drivers/usb/musb/am35x.h b/drivers/usb/musb/am35x.h index bebe38d..eb270f6 100644 --- a/drivers/usb/musb/am35x.h +++ b/drivers/usb/musb/am35x.h @@ -63,20 +63,20 @@ struct am35x_usb_regs { #define am35x_usb_regs ((struct am35x_usb_regs *)AM35X_USB_OTG_BASE) /* USB 2.0 PHY Control */ -#define DEVCONF2_PHY_GPIOMODE (1 << 23) +#define DEVCONF2_PHY_GPIOMODE BIT(23) #define DEVCONF2_OTGMODE (3 << 14) -#define DEVCONF2_SESENDEN (1 << 13) /* Vsess_end comparator */ -#define DEVCONF2_VBDTCTEN (1 << 12) /* Vbus comparator */ +#define DEVCONF2_SESENDEN BIT(13) /* Vsess_end comparator */ +#define DEVCONF2_VBDTCTEN BIT(12) /* Vbus comparator */ #define DEVCONF2_REFFREQ_24MHZ (2 << 8) #define DEVCONF2_REFFREQ_26MHZ (7 << 8) #define DEVCONF2_REFFREQ_13MHZ (6 << 8) #define DEVCONF2_REFFREQ (0xf << 8) -#define DEVCONF2_PHYCKGD (1 << 7) -#define DEVCONF2_VBUSSENSE (1 << 6) -#define DEVCONF2_PHY_PLLON (1 << 5) /* override PLL suspend */ -#define DEVCONF2_RESET (1 << 4) -#define DEVCONF2_PHYPWRDN (1 << 3) -#define DEVCONF2_OTGPWRDN (1 << 2) -#define DEVCONF2_DATPOL (1 << 1) +#define DEVCONF2_PHYCKGD BIT(7) +#define DEVCONF2_VBUSSENSE BIT(6) +#define DEVCONF2_PHY_PLLON BIT(5) /* override PLL suspend */ +#define DEVCONF2_RESET BIT(4) +#define DEVCONF2_PHYPWRDN BIT(3) +#define DEVCONF2_OTGPWRDN BIT(2) +#define DEVCONF2_DATPOL BIT(1) #endif /* __AM35X_USB_H__ */ diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h index 9efefe8..389c601 100644 --- a/drivers/usb/musb/davinci.h +++ b/drivers/usb/musb/davinci.h @@ -50,14 +50,14 @@ struct davinci_usb_regs { /* Integrated highspeed/otg PHY */ #define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34) -#define USBPHY_PHY24MHZ (1 << 13) -#define USBPHY_PHYCLKGD (1 << 8) -#define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */ -#define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */ -#define USBPHY_PHYPLLON (1 << 4) /* override pll suspend */ -#define USBPHY_CLKO1SEL (1 << 3) -#define USBPHY_OSCPDWN (1 << 2) -#define USBPHY_PHYPDWN (1 << 0) +#define USBPHY_PHY24MHZ BIT(13) +#define USBPHY_PHYCLKGD BIT(8) +#define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */ +#define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */ +#define USBPHY_PHYPLLON BIT(4) /* override pll suspend */ +#define USBPHY_CLKO1SEL BIT(3) +#define USBPHY_OSCPDWN BIT(2) +#define USBPHY_PHYPDWN BIT(0) /* Timeout for Davinci USB module */ #define DAVINCI_USB_TIMEOUT 0x3FFFFFF diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index 6dcb336..1319548 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -29,13 +29,13 @@ /* Defines for bits in registers */ #define OPMODE_MASK (3 << 3) #define XCVRSELECT_MASK (3 << 0) -#define CARKITMODE (1 << 2) -#define OTG_ENAB (1 << 5) -#define PHYPWD (1 << 0) -#define CLOCKGATING_EN (1 << 2) -#define CLK32K_EN (1 << 1) -#define REQ_PHY_DPLL_CLK (1 << 0) -#define PHY_DPLL_CLK (1 << 0) +#define CARKITMODE BIT(2) +#define OTG_ENAB BIT(5) +#define PHYPWD BIT(0) +#define CLOCKGATING_EN BIT(2) +#define CLK32K_EN BIT(1) +#define REQ_PHY_DPLL_CLK BIT(0) +#define PHY_DPLL_CLK BIT(0) static int twl4030_usb_write(u8 address, u8 data) { diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c index 4db7fa4..22f8d4d 100644 --- a/drivers/usb/ulpi/omap-ulpi-viewport.c +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c @@ -24,7 +24,7 @@ #define OMAP_ULPI_WR_OPSEL (2 << 22) #define OMAP_ULPI_RD_OPSEL (3 << 22) -#define OMAP_ULPI_START (1 << 31) +#define OMAP_ULPI_START BIT(31) /* * Wait for having ulpi in done state diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c index b4974ed..ac95f49 100644 --- a/drivers/usb/ulpi/ulpi-viewport.c +++ b/drivers/usb/ulpi/ulpi-viewport.c @@ -27,10 +27,10 @@ #include /* ULPI viewport control bits */ -#define ULPI_SS (1 << 27) -#define ULPI_RWCTRL (1 << 29) -#define ULPI_RWRUN (1 << 30) -#define ULPI_WU (1 << 31) +#define ULPI_SS BIT(27) +#define ULPI_RWCTRL BIT(29) +#define ULPI_RWRUN BIT(30) +#define ULPI_WU BIT(31) /* * Wait for the ULPI request to complete diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 6f95649..47f61f6 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -53,8 +53,8 @@ #define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8) #define LCD_INVMASK(x) ((x) & 0x3F00000) /* LCD Raster Ctrl Register */ -#define LCD_TFT_24BPP_MODE (1 << 25) -#define LCD_TFT_24BPP_UNPACK (1 << 26) +#define LCD_TFT_24BPP_MODE BIT(25) +#define LCD_TFT_24BPP_UNPACK BIT(26) #define LCD_PALMODE_RAWDATA (0x10 << 20) #define LCD_TFT_MODE (0x01 << 7) #define LCD_RASTER_ENABLE (0x01 << 0) diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 3a5f325..5d278f2 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -36,11 +36,11 @@ #define LCD_VERSION_2 2 /* LCD Status Register */ -#define LCD_END_OF_FRAME1 (1 << 9) -#define LCD_END_OF_FRAME0 (1 << 8) -#define LCD_PL_LOAD_DONE (1 << 6) -#define LCD_FIFO_UNDERFLOW (1 << 5) -#define LCD_SYNC_LOST (1 << 2) +#define LCD_END_OF_FRAME1 BIT(9) +#define LCD_END_OF_FRAME0 BIT(8) +#define LCD_PL_LOAD_DONE BIT(6) +#define LCD_FIFO_UNDERFLOW BIT(5) +#define LCD_SYNC_LOST BIT(2) /* LCD DMA Control Register */ #define LCD_DMA_BURST_SIZE(x) ((x) << 4) @@ -49,13 +49,13 @@ #define LCD_DMA_BURST_4 0x2 #define LCD_DMA_BURST_8 0x3 #define LCD_DMA_BURST_16 0x4 -#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2) -#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8) -#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9) -#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) +#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) +#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) +#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) +#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) -#define LCD_V2_TFT_24BPP_MODE (1 << 25) -#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) +#define LCD_V2_TFT_24BPP_MODE BIT(25) +#define LCD_V2_TFT_24BPP_UNPACK BIT(26) /* LCD Control Register */ #define LCD_CLK_DIVISOR(x) ((x) << 8) @@ -67,35 +67,35 @@ #define PALETTE_ONLY 0x01 #define DATA_ONLY 0x02 -#define LCD_MONO_8BIT_MODE (1 << 9) -#define LCD_RASTER_ORDER (1 << 8) -#define LCD_TFT_MODE (1 << 7) -#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6) -#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5) -#define LCD_V1_PL_INT_ENA (1 << 4) -#define LCD_V2_PL_INT_ENA (1 << 6) -#define LCD_MONOCHROME_MODE (1 << 1) -#define LCD_RASTER_ENABLE (1 << 0) -#define LCD_TFT_ALT_ENABLE (1 << 23) -#define LCD_STN_565_ENABLE (1 << 24) -#define LCD_V2_DMA_CLK_EN (1 << 2) -#define LCD_V2_LIDD_CLK_EN (1 << 1) -#define LCD_V2_CORE_CLK_EN (1 << 0) +#define LCD_MONO_8BIT_MODE BIT(9) +#define LCD_RASTER_ORDER BIT(8) +#define LCD_TFT_MODE BIT(7) +#define LCD_V1_UNDERFLOW_INT_ENA BIT(6) +#define LCD_V2_UNDERFLOW_INT_ENA BIT(5) +#define LCD_V1_PL_INT_ENA BIT(4) +#define LCD_V2_PL_INT_ENA BIT(6) +#define LCD_MONOCHROME_MODE BIT(1) +#define LCD_RASTER_ENABLE BIT(0) +#define LCD_TFT_ALT_ENABLE BIT(23) +#define LCD_STN_565_ENABLE BIT(24) +#define LCD_V2_DMA_CLK_EN BIT(2) +#define LCD_V2_LIDD_CLK_EN BIT(1) +#define LCD_V2_CORE_CLK_EN BIT(0) #define LCD_V2_LPP_B10 26 -#define LCD_V2_TFT_24BPP_MODE (1 << 25) -#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) +#define LCD_V2_TFT_24BPP_MODE BIT(25) +#define LCD_V2_TFT_24BPP_UNPACK BIT(26) /* LCD Raster Timing 2 Register */ #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) -#define LCD_SYNC_CTRL (1 << 25) -#define LCD_SYNC_EDGE (1 << 24) -#define LCD_INVERT_PIXEL_CLOCK (1 << 22) -#define LCD_INVERT_LINE_CLOCK (1 << 21) -#define LCD_INVERT_FRAME_CLOCK (1 << 20) +#define LCD_SYNC_CTRL BIT(25) +#define LCD_SYNC_EDGE BIT(24) +#define LCD_INVERT_PIXEL_CLOCK BIT(22) +#define LCD_INVERT_LINE_CLOCK BIT(21) +#define LCD_INVERT_FRAME_CLOCK BIT(20) /* Clock registers available only on Version 2 */ -#define LCD_CLK_MAIN_RESET (1 << 3) +#define LCD_CLK_MAIN_RESET BIT(3) /* LCD Block */ struct da8xx_lcd_regs { u32 revid; @@ -522,7 +522,7 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, } /* Set the Raster Order of the Frame Buffer */ - reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~BIT(8); if (raster_order) reg |= LCD_RASTER_ORDER; diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c index 925d515..668d08f 100644 --- a/drivers/video/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos_mipi_dsi_common.c @@ -36,11 +36,11 @@ enum { /* define DSI lane types. */ enum { - DSIM_LANE_CLOCK = (1 << 0), - DSIM_LANE_DATA0 = (1 << 1), - DSIM_LANE_DATA1 = (1 << 2), - DSIM_LANE_DATA2 = (1 << 3), - DSIM_LANE_DATA3 = (1 << 4) + DSIM_LANE_CLOCK = BIT(0), + DSIM_LANE_DATA0 = BIT(1), + DSIM_LANE_DATA1 = BIT(2), + DSIM_LANE_DATA2 = BIT(3), + DSIM_LANE_DATA3 = BIT(4) }; static unsigned int dpll_table[15] = { diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index d4cd382..f513fe5 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -26,7 +26,7 @@ #endif #define DCU_MODE_BLEND_ITER(x) ((x) << 20) -#define DCU_MODE_RASTER_EN (1 << 14) +#define DCU_MODE_RASTER_EN BIT(14) #define DCU_MODE_NORMAL 1 #define DCU_MODE_COLORBAR 3 #define DCU_BGND_R(x) ((x) << 16) @@ -42,27 +42,27 @@ #define DCU_VSYN_PARA_FP(x) (x) #define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) #define DCU_SYN_POL_NEG_REMAIN (0 << 5) -#define DCU_SYN_POL_INV_VS_LOW (1 << 1) +#define DCU_SYN_POL_INV_VS_LOW BIT(1) #define DCU_SYN_POL_INV_HS_LOW (1) #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) -#define DCU_UPDATE_MODE_MODE (1 << 31) -#define DCU_UPDATE_MODE_READREG (1 << 30) +#define DCU_UPDATE_MODE_MODE BIT(31) +#define DCU_UPDATE_MODE_READREG BIT(30) #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) #define DCU_CTRLDESCLN_1_WIDTH(x) (x) #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) #define DCU_CTRLDESCLN_2_POSX(x) (x) -#define DCU_CTRLDESCLN_4_EN (1 << 31) -#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) -#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) -#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) +#define DCU_CTRLDESCLN_4_EN BIT(31) +#define DCU_CTRLDESCLN_4_TILE_EN BIT(30) +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT BIT(29) +#define DCU_CTRLDESCLN_4_SAFETY_EN BIT(28) #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) -#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) +#define DCU_CTRLDESCLN_4_RLE_EN BIT(15) #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) -#define DCU_CTRLDESCLN_4_BB_ON (1 << 2) +#define DCU_CTRLDESCLN_4_BB_ON BIT(2) #define DCU_CTRLDESCLN_4_AB(x) (x) #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c index ef5767b..357f25c 100644 --- a/drivers/video/imx25lcdc.c +++ b/drivers/video/imx25lcdc.c @@ -86,12 +86,12 @@ void *video_hw_init(void) lsr = ((var_mode.xres / 16) << 20) | var_mode.yres; - lpcr = (1 << 31) | - (1 << 30) | + lpcr = BIT(31) | + BIT(30) | (5 << 25) | - (1 << 23) | - (1 << 22) | - (1 << 19) | + BIT(23) | + BIT(22) | + BIT(19) | (1 << 7) | div; lhcr = (var_mode.right_margin << 0) | diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index aa4cc43..f23ffda 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c @@ -221,16 +221,16 @@ enum ipu_panel { #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) /* DI_DISP_SIG_POL bits */ -#define DI_D3_VSYNC_POL (1 << 28) -#define DI_D3_HSYNC_POL (1 << 27) -#define DI_D3_DRDY_SHARP_POL (1 << 26) -#define DI_D3_CLK_POL (1 << 25) -#define DI_D3_DATA_POL (1 << 24) +#define DI_D3_VSYNC_POL BIT(28) +#define DI_D3_HSYNC_POL BIT(27) +#define DI_D3_DRDY_SHARP_POL BIT(26) +#define DI_D3_CLK_POL BIT(25) +#define DI_D3_DATA_POL BIT(24) /* DI_DISP_IF_CONF bits */ -#define DI_D3_CLK_IDLE (1 << 26) -#define DI_D3_CLK_SEL (1 << 25) -#define DI_D3_DATAMSK (1 << 24) +#define DI_D3_CLK_IDLE BIT(26) +#define DI_D3_CLK_SEL BIT(25) +#define DI_D3_DATAMSK BIT(24) #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_GPIONUM_SHIFT 9 diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 8b09082..8b25811 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -85,21 +85,21 @@ #define SSD2828_ACR5 0xF7 #define SSD2828_RR 0xFF -#define SSD2828_CFGR_HS (1 << 0) -#define SSD2828_CFGR_CKE (1 << 1) -#define SSD2828_CFGR_SLP (1 << 2) -#define SSD2828_CFGR_VEN (1 << 3) -#define SSD2828_CFGR_HCLK (1 << 4) -#define SSD2828_CFGR_CSS (1 << 5) -#define SSD2828_CFGR_DCS (1 << 6) -#define SSD2828_CFGR_REN (1 << 7) -#define SSD2828_CFGR_ECD (1 << 8) -#define SSD2828_CFGR_EOT (1 << 9) -#define SSD2828_CFGR_LPE (1 << 10) -#define SSD2828_CFGR_TXD (1 << 11) +#define SSD2828_CFGR_HS BIT(0) +#define SSD2828_CFGR_CKE BIT(1) +#define SSD2828_CFGR_SLP BIT(2) +#define SSD2828_CFGR_VEN BIT(3) +#define SSD2828_CFGR_HCLK BIT(4) +#define SSD2828_CFGR_CSS BIT(5) +#define SSD2828_CFGR_DCS BIT(6) +#define SSD2828_CFGR_REN BIT(7) +#define SSD2828_CFGR_ECD BIT(8) +#define SSD2828_CFGR_EOT BIT(9) +#define SSD2828_CFGR_LPE BIT(10) +#define SSD2828_CFGR_TXD BIT(11) #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2) -#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2) +#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS BIT(2) #define SSD2828_VIDEO_MODE_BURST (2 << 2) #define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0 diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index cab5465..8461d57 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -207,7 +207,7 @@ int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index) } else { if (remainder == 0) { ptr = ptr + i - 1; - operand = (1 << 7); + operand = BIT(7); } else { ptr = ptr + i; operand = (1 << (remainder - 1)); @@ -240,7 +240,7 @@ void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, int index) } else { if (remainder == 0) { ptr = ptr + i - 1; - operand = (1 << 7); + operand = BIT(7); } else { ptr = ptr + i; operand = (1 << (remainder - 1)); @@ -262,7 +262,7 @@ int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index) remainder = inode_no % 8; if (remainder == 0) { ptr = ptr + i - 1; - operand = (1 << 7); + operand = BIT(7); } else { ptr = ptr + i; operand = (1 << (remainder - 1)); @@ -287,7 +287,7 @@ void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index) remainder = inode_no % 8; if (remainder == 0) { ptr = ptr + i - 1; - operand = (1 << 7); + operand = BIT(7); } else { ptr = ptr + i; operand = (1 << (remainder - 1)); diff --git a/fs/reiserfs/reiserfs_private.h b/fs/reiserfs/reiserfs_private.h index 9d14c71..a72c380 100644 --- a/fs/reiserfs/reiserfs_private.h +++ b/fs/reiserfs/reiserfs_private.h @@ -371,8 +371,8 @@ struct reiserfs_de_head #define deh_state(p_deh) (__le16_to_cpu((p_deh)->deh_state)) -#define DEH_Statdata (1 << 0) /* not used now */ -#define DEH_Visible (1 << 2) +#define DEH_Statdata BIT(0) /* not used now */ +#define DEH_Visible BIT(2) #define SD_OFFSET 0 #define SD_UNIQUENESS 0 diff --git a/include/SA-1100.h b/include/SA-1100.h index 7589df2..3b3a96a 100644 --- a/include/SA-1100.h +++ b/include/SA-1100.h @@ -2047,17 +2047,17 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define MDREFR_TRASR Fld (4, 0) #define MDREFR_DRI Fld (12, 4) -#define MDREFR_E0PIN (1 << 16) -#define MDREFR_K0RUN (1 << 17) -#define MDREFR_K0DB2 (1 << 18) -#define MDREFR_E1PIN (1 << 20) -#define MDREFR_K1RUN (1 << 21) -#define MDREFR_K1DB2 (1 << 22) -#define MDREFR_K2RUN (1 << 25) -#define MDREFR_K2DB2 (1 << 26) -#define MDREFR_EAPD (1 << 28) -#define MDREFR_KAPD (1 << 29) -#define MDREFR_SLFRSH (1 << 31) +#define MDREFR_E0PIN BIT(16) +#define MDREFR_K0RUN BIT(17) +#define MDREFR_K0DB2 BIT(18) +#define MDREFR_E1PIN BIT(20) +#define MDREFR_K1RUN BIT(21) +#define MDREFR_K1DB2 BIT(22) +#define MDREFR_K2RUN BIT(25) +#define MDREFR_K2DB2 BIT(26) +#define MDREFR_EAPD BIT(28) +#define MDREFR_KAPD BIT(29) +#define MDREFR_SLFRSH BIT(31) /* diff --git a/include/ahci.h b/include/ahci.h index 6d91712..01e33a7 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -20,11 +20,11 @@ #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) -#define AHCI_CMD_ATAPI (1 << 5) -#define AHCI_CMD_WRITE (1 << 6) -#define AHCI_CMD_PREFETCH (1 << 7) -#define AHCI_CMD_RESET (1 << 8) -#define AHCI_CMD_CLR_BUSY (1 << 10) +#define AHCI_CMD_ATAPI BIT(5) +#define AHCI_CMD_WRITE BIT(6) +#define AHCI_CMD_PREFETCH BIT(7) +#define AHCI_CMD_RESET BIT(8) +#define AHCI_CMD_CLR_BUSY BIT(10) #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ @@ -37,9 +37,9 @@ #define HOST_CAP2 0x24 /* host capabilities, extended */ /* HOST_CTL bits */ -#define HOST_RESET (1 << 0) /* reset controller; self-clear */ -#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ -#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ +#define HOST_RESET BIT(0) /* reset controller; self-clear */ +#define HOST_IRQ_EN BIT(1) /* global IRQ enable */ +#define HOST_AHCI_EN BIT(31) /* AHCI enabled */ /* Registers for each SATA port */ #define PORT_LST_ADDR 0x00 /* command list DMA addr */ @@ -63,24 +63,24 @@ #endif /* PORT_IRQ_{STAT,MASK} bits */ -#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ -#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ -#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ -#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ -#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ -#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ -#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ -#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ - -#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ -#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ -#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ -#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ -#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ -#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ -#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ -#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ -#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ +#define PORT_IRQ_COLD_PRES BIT(31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR BIT(30) /* task file error */ +#define PORT_IRQ_HBUS_ERR BIT(29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR BIT(28) /* host bus data error */ +#define PORT_IRQ_IF_ERR BIT(27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL BIT(26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW BIT(24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP BIT(23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY BIT(22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK BIT(7) /* device interlock */ +#define PORT_IRQ_CONNECT BIT(6) /* port connect change status */ +#define PORT_IRQ_SG_DONE BIT(5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS BIT(4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS BIT(3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS BIT(2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS BIT(1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS BIT(0) /* D2H Register FIS rx'd */ #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR @@ -97,14 +97,14 @@ #define PORT_SCR_STAT_DET_PHYRDY 0x3 /* PORT_CMD bits */ -#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ -#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ -#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ -#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ -#define PORT_CMD_CLO (1 << 3) /* Command list override */ -#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ -#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ -#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ +#define PORT_CMD_ATAPI BIT(24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON BIT(15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON BIT(14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX BIT(4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO BIT(3) /* Command list override */ +#define PORT_CMD_POWER_ON BIT(2) /* Power up device */ +#define PORT_CMD_SPIN_UP BIT(1) /* Spin up device */ +#define PORT_CMD_START BIT(0) /* Enable port DMA engine */ #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ @@ -112,12 +112,12 @@ #define AHCI_MAX_PORTS 32 -#define ATA_FLAG_SATA (1 << 3) -#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ -#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ -#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ -#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ -#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ +#define ATA_FLAG_SATA BIT(3) +#define ATA_FLAG_NO_LEGACY BIT(4) /* no legacy mode check */ +#define ATA_FLAG_MMIO BIT(6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET BIT(7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA BIT(8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI BIT(11) /* No ATAPI support */ struct ahci_cmd_hdr { u32 opts; diff --git a/include/ambapp.h b/include/ambapp.h index 405637d..de64677 100644 --- a/include/ambapp.h +++ b/include/ambapp.h @@ -19,7 +19,7 @@ */ #define LEON3_IO_AREA 0xfff00000 #define LEON3_CONF_AREA 0xff000 -#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11) +#define LEON3_AHB_SLAVE_CONF_AREA BIT(11) /* Max devices this software will support */ #define LEON3_AHB_MASTERS 16 diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 3b96b82..c8b057d 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -113,11 +113,11 @@ struct udevice; struct gpio_desc { struct udevice *dev; /* Device, NULL for invalid GPIO */ unsigned long flags; -#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ -#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ -#define GPIOD_IS_IN (1 << 2) /* GPIO is an output */ -#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ -#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ +#define GPIOD_REQUESTED BIT(0) /* Requested/claimed */ +#define GPIOD_IS_OUT BIT(1) /* GPIO is an output */ +#define GPIOD_IS_IN BIT(2) /* GPIO is an output */ +#define GPIOD_ACTIVE_LOW BIT(3) /* value has active low */ +#define GPIOD_IS_OUT_ACTIVE BIT(4) /* set output active */ uint offset; /* GPIO offset within the device */ /* diff --git a/include/atmel_lcdc.h b/include/atmel_lcdc.h index ba62180..fc7351d 100644 --- a/include/atmel_lcdc.h +++ b/include/atmel_lcdc.h @@ -44,44 +44,44 @@ #define ATMEL_LCDC_LCDCON2 0x0804 #define ATMEL_LCDC_DISTYPE (3 << 0) #define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) -#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define ATMEL_LCDC_DISTYPE_STNCOLOR BIT(0) #define ATMEL_LCDC_DISTYPE_TFT (2 << 0) -#define ATMEL_LCDC_SCANMOD (1 << 2) +#define ATMEL_LCDC_SCANMOD BIT(2) #define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) -#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) +#define ATMEL_LCDC_SCANMOD_DUAL BIT(2) #define ATMEL_LCDC_IFWIDTH (3 << 3) #define ATMEL_LCDC_IFWIDTH_4 (0 << 3) -#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) +#define ATMEL_LCDC_IFWIDTH_8 BIT(3) #define ATMEL_LCDC_IFWIDTH_16 (2 << 3) #define ATMEL_LCDC_PIXELSIZE (7 << 5) #define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) -#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) +#define ATMEL_LCDC_PIXELSIZE_2 BIT(5) #define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) #define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) #define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) #define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) #define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) -#define ATMEL_LCDC_INVVD (1 << 8) +#define ATMEL_LCDC_INVVD BIT(8) #define ATMEL_LCDC_INVVD_NORMAL (0 << 8) -#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) +#define ATMEL_LCDC_INVVD_INVERTED BIT(8) #define ATMEL_LCDC_INVFRAME (1 << 9 ) #define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) -#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) -#define ATMEL_LCDC_INVLINE (1 << 10) +#define ATMEL_LCDC_INVFRAME_INVERTED BIT(9) +#define ATMEL_LCDC_INVLINE BIT(10) #define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) -#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) -#define ATMEL_LCDC_INVCLK (1 << 11) +#define ATMEL_LCDC_INVLINE_INVERTED BIT(10) +#define ATMEL_LCDC_INVCLK BIT(11) #define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) -#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) -#define ATMEL_LCDC_INVDVAL (1 << 12) +#define ATMEL_LCDC_INVCLK_INVERTED BIT(11) +#define ATMEL_LCDC_INVDVAL BIT(12) #define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) -#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) -#define ATMEL_LCDC_CLKMOD (1 << 15) +#define ATMEL_LCDC_INVDVAL_INVERTED BIT(12) +#define ATMEL_LCDC_CLKMOD BIT(15) #define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) -#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) -#define ATMEL_LCDC_MEMOR (1 << 31) +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE BIT(15) +#define ATMEL_LCDC_MEMOR BIT(31) #define ATMEL_LCDC_MEMOR_BIG (0 << 31) -#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) +#define ATMEL_LCDC_MEMOR_LITTLE BIT(31) #define ATMEL_LCDC_TIM1 0x0808 #define ATMEL_LCDC_VFP (0xffU << 0) @@ -135,15 +135,15 @@ #define ATMEL_LCDC_CONTRAST_CTR 0x0840 #define ATMEL_LCDC_PS (3 << 0) #define ATMEL_LCDC_PS_DIV1 (0 << 0) -#define ATMEL_LCDC_PS_DIV2 (1 << 0) +#define ATMEL_LCDC_PS_DIV2 BIT(0) #define ATMEL_LCDC_PS_DIV4 (2 << 0) #define ATMEL_LCDC_PS_DIV8 (3 << 0) -#define ATMEL_LCDC_POL (1 << 2) +#define ATMEL_LCDC_POL BIT(2) #define ATMEL_LCDC_POL_NEGATIVE (0 << 2) -#define ATMEL_LCDC_POL_POSITIVE (1 << 2) -#define ATMEL_LCDC_ENA (1 << 3) +#define ATMEL_LCDC_POL_POSITIVE BIT(2) +#define ATMEL_LCDC_ENA BIT(3) #define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) -#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) +#define ATMEL_LCDC_ENA_PWMENABLE BIT(3) #define ATMEL_LCDC_CONTRAST_VAL 0x0844 #define ATMEL_LCDC_CVAL (0xff) @@ -153,12 +153,12 @@ #define ATMEL_LCDC_IMR 0x0850 #define ATMEL_LCDC_ISR 0x0854 #define ATMEL_LCDC_ICR 0x0858 -#define ATMEL_LCDC_LNI (1 << 0) -#define ATMEL_LCDC_LSTLNI (1 << 1) -#define ATMEL_LCDC_EOFI (1 << 2) -#define ATMEL_LCDC_UFLWI (1 << 4) -#define ATMEL_LCDC_OWRI (1 << 5) -#define ATMEL_LCDC_MERI (1 << 6) +#define ATMEL_LCDC_LNI BIT(0) +#define ATMEL_LCDC_LSTLNI BIT(1) +#define ATMEL_LCDC_EOFI BIT(2) +#define ATMEL_LCDC_UFLWI BIT(4) +#define ATMEL_LCDC_OWRI BIT(5) +#define ATMEL_LCDC_MERI BIT(6) #define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) diff --git a/include/axp152.h b/include/axp152.h index 9d205f8..d963cb9 100644 --- a/include/axp152.h +++ b/include/axp152.h @@ -13,7 +13,7 @@ enum axp152_reg { AXP152_SHUTDOWN = 0x32, }; -#define AXP152_POWEROFF (1 << 7) +#define AXP152_POWEROFF BIT(7) int axp152_set_dcdc2(int mvolt); int axp152_set_dcdc3(int mvolt); diff --git a/include/axp209.h b/include/axp209.h index d36da41..3a8723c 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -25,13 +25,13 @@ enum axp209_reg { AXP209_GPIO3_CTRL = 0x95, }; -#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) -#define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4) +#define AXP209_POWER_STATUS_ON_BY_DC BIT(0) +#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4) -#define AXP209_IRQ5_PEK_UP (1 << 6) -#define AXP209_IRQ5_PEK_DOWN (1 << 5) +#define AXP209_IRQ5_PEK_UP BIT(6) +#define AXP209_IRQ5_PEK_DOWN BIT(5) -#define AXP209_POWEROFF (1 << 7) +#define AXP209_POWEROFF BIT(7) #define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */ #define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */ diff --git a/include/axp221.h b/include/axp221.h index 0aac04d..95c9af3 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -15,29 +15,29 @@ /* Page 0 addresses */ #define AXP221_POWER_STATUS 0x00 -#define AXP221_POWER_STATUS_VBUS_AVAIL (1 << 5) -#define AXP221_POWER_STATUS_VBUS_USABLE (1 << 4) +#define AXP221_POWER_STATUS_VBUS_AVAIL BIT(5) +#define AXP221_POWER_STATUS_VBUS_USABLE BIT(4) #define AXP221_CHIP_ID 0x03 #define AXP221_OUTPUT_CTRL1 0x10 -#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0) -#define AXP221_OUTPUT_CTRL1_DCDC1_EN (1 << 1) -#define AXP221_OUTPUT_CTRL1_DCDC2_EN (1 << 2) -#define AXP221_OUTPUT_CTRL1_DCDC3_EN (1 << 3) -#define AXP221_OUTPUT_CTRL1_DCDC4_EN (1 << 4) -#define AXP221_OUTPUT_CTRL1_DCDC5_EN (1 << 5) -#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) -#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) +#define AXP221_OUTPUT_CTRL1_DCDC0_EN BIT(0) +#define AXP221_OUTPUT_CTRL1_DCDC1_EN BIT(1) +#define AXP221_OUTPUT_CTRL1_DCDC2_EN BIT(2) +#define AXP221_OUTPUT_CTRL1_DCDC3_EN BIT(3) +#define AXP221_OUTPUT_CTRL1_DCDC4_EN BIT(4) +#define AXP221_OUTPUT_CTRL1_DCDC5_EN BIT(5) +#define AXP221_OUTPUT_CTRL1_ALDO1_EN BIT(6) +#define AXP221_OUTPUT_CTRL1_ALDO2_EN BIT(7) #define AXP221_OUTPUT_CTRL2 0x12 -#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0) -#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1) -#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2) -#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) -#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) -#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) -#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6) -#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN (1 << 7) +#define AXP221_OUTPUT_CTRL2_ELDO1_EN BIT(0) +#define AXP221_OUTPUT_CTRL2_ELDO2_EN BIT(1) +#define AXP221_OUTPUT_CTRL2_ELDO3_EN BIT(2) +#define AXP221_OUTPUT_CTRL2_DLDO1_EN BIT(3) +#define AXP221_OUTPUT_CTRL2_DLDO2_EN BIT(4) +#define AXP221_OUTPUT_CTRL2_DLDO3_EN BIT(5) +#define AXP221_OUTPUT_CTRL2_DLDO4_EN BIT(6) +#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN BIT(7) #define AXP221_OUTPUT_CTRL3 0x13 -#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7) +#define AXP221_OUTPUT_CTRL3_ALDO3_EN BIT(7) #define AXP221_DLDO1_CTRL 0x15 #define AXP221_DLDO2_CTRL 0x16 #define AXP221_DLDO3_CTRL 0x17 @@ -54,9 +54,9 @@ #define AXP221_ALDO2_CTRL 0x29 #define AXP221_ALDO3_CTRL 0x2a #define AXP221_VBUS_IPSOUT 0x30 -#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP221_VBUS_IPSOUT_DRIVEBUS BIT(2) #define AXP221_MISC_CTRL 0x8f -#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) +#define AXP221_MISC_CTRL_N_VBUSEN_FUNC BIT(4) #define AXP221_PAGE 0xff /* Page 1 addresses */ diff --git a/include/bouncebuf.h b/include/bouncebuf.h index 5ffa99b..d3c4798 100644 --- a/include/bouncebuf.h +++ b/include/bouncebuf.h @@ -18,7 +18,7 @@ * requiring the aligned transfer happens, then the bounce buffer is lost upon * stop() call. */ -#define GEN_BB_READ (1 << 0) +#define GEN_BB_READ BIT(0) /* * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. * The source buffer starts in an undefined state upon start() call, then the @@ -26,7 +26,7 @@ * copied into the destination buffer (if unaligned, otherwise destination * buffer is used directly) upon stop() call. */ -#define GEN_BB_WRITE (1 << 1) +#define GEN_BB_WRITE BIT(1) /* * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. * The source buffer is copied into the bounce buffer (if unaligned, otherwise diff --git a/include/cli_hush.h b/include/cli_hush.h index 57c870d..a1bc8e5 100644 --- a/include/cli_hush.h +++ b/include/cli_hush.h @@ -9,9 +9,9 @@ #define _CLI_HUSH_H_ #define FLAG_EXIT_FROM_LOOP 1 -#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ -#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ -#define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */ +#define FLAG_PARSE_SEMICOLON BIT(1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING BIT(2) /* >=2nd pass */ +#define FLAG_CONT_ON_NEWLINE BIT(3) /* continue when we see \n */ extern int u_boot_hush_start(void); extern int parse_string_outer(const char *, int); diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index 54b7028..76fe3f9 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -117,16 +117,16 @@ #define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) #define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ - | (1 << 31) /* RST_B */ \ - | (1 << 30) /* CKE */ \ - | (1 << 29) /* CLK_ON */ \ + | BIT(31) /* RST_B */ \ + | BIT(30) /* CKE */ \ + | BIT(29) /* CLK_ON */ \ | (0 << 28) /* CMD_MODE */ \ | (5 << 25) /* DRAM_ROW_SELECT */ \ | (5 << 21) /* DRAM_BANK_SELECT */ \ | (0 << 18) /* SELF_REF_EN */ \ | (0 << 17) /* 16BIT_MODE */ \ | (4 << 13) /* RDLY */ \ - | (1 << 12) /* HALF_DQS_DLY */ \ + | BIT(12) /* HALF_DQS_DLY */ \ | (0 << 11) /* QUART_DQS_DLY */ \ | (1 << 8) /* WDLY */ \ | (0 << 7) /* EARLY_ODT */ \ @@ -157,12 +157,12 @@ #define CONFIG_SYS_DDRCMD_NOP 0x01380000 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ +#define CONFIG_SYS_MICRON_EMR (BIT(24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ (0 << 20) | /* DRAM_CAS */ \ (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ + BIT(16) | /* DRAM_BS[2:0] */ \ (0 << 15) | /* */ \ (0 << 12) | /* A12->out */ \ (0 << 11) | /* A11->RDQS */ \ @@ -178,16 +178,16 @@ #define CONFIG_SYS_MICRON_EMR3 0x01030000 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ +#define CONFIG_SYS_MICRON_EMR_OCD (BIT(24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ (0 << 20) | /* DRAM_CAS */ \ (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ + BIT(16) | /* DRAM_BS[2:0] */ \ (0 << 15) | /* */ \ (0 << 12) | /* A12->out */ \ (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ + BIT(10) | /* A10->DQS# */ \ (7 << 7) | /* OCD program */ \ (0 << 6) | /* Rtt1 */ \ (0 << 3) | /* posted CAS# */ \ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 932a309..4c6eca2 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -91,9 +91,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index d5b6e37..c8b6ae1 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* Reserved for malloc */ /* * UART diff --git a/include/configs/aria.h b/include/configs/aria.h index 2f9677c..8f8cf3e 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -112,9 +112,9 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ - (1 << 30) | /* CKE */ \ - (1 << 29) | /* CLK_ON */ \ +#define CONFIG_SYS_MDDRC_SYS_CFG ( BIT(31) | /* RST_B */ \ + BIT(30) | /* CKE */ \ + BIT(29) | /* CLK_ON */ \ (0 << 28) | /* CMD_MODE */ \ (4 << 25) | /* DRAM_ROW_SELECT */ \ (3 << 21) | /* DRAM_BANK_SELECT */ \ @@ -122,7 +122,7 @@ (0 << 17) | /* 16BIT_MODE */ \ (2 << 13) | /* RDLY */ \ (0 << 12) | /* HALF_DQS_DLY */ \ - (1 << 11) | /* QUART_DQS_DLY */ \ + BIT(11) | /* QUART_DQS_DLY */ \ (2 << 8) | /* WDLY */ \ (0 << 7) | /* EARLY_ODT */ \ (1 << 6) | /* ON_DIE_TERMINATE */ \ @@ -138,12 +138,12 @@ #define CONFIG_SYS_DDRCMD_NOP 0x01380000 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ +#define CONFIG_SYS_MICRON_EMR ( BIT(24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ (0 << 20) | /* DRAM_CAS */ \ (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ + BIT(16) | /* DRAM_BS[2:0] */ \ (0 << 15) | /* */ \ (0 << 12) | /* A12->out */ \ (0 << 11) | /* A11->RDQS */ \ @@ -159,16 +159,16 @@ #define CONFIG_SYS_MICRON_EMR3 0x01030000 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ +#define CONFIG_SYS_MICRON_EMR_OCD ( BIT(24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ (0 << 20) | /* DRAM_CAS */ \ (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ + BIT(16) | /* DRAM_BS[2:0] */ \ (0 << 15) | /* */ \ (0 << 12) | /* A12->out */ \ (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ + BIT(10) | /* A10->DQS# */ \ (7 << 7) | /* OCD program */ \ (0 << 6) | /* Rtt1 */ \ (0 << 3) | /* posted CAS# */ \ @@ -264,10 +264,10 @@ #define CONFIG_SYS_CS0_CFG 0x05059150 #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ (5 << 16) | \ - (1 << 15) | \ + BIT(15) | \ (0 << 14) | \ (0 << 13) | \ - (1 << 12) | \ + BIT(12) | \ (0 << 10) | \ (3 << 8) | /* 32 bit */ \ (0 << 7) | \ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index c4b2e16..68c7c05 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -158,8 +158,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 407a53e..4bd3275 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -123,9 +123,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(22) /* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(21) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index fa19e8b..3a8fe07 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -215,7 +215,7 @@ (2 << 16) | /* Row Precharge Delay */ \ (2 << 20) | /* Row to Column Delay */ \ (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ + BIT(28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM @@ -277,9 +277,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index e4c49f4..8acfd53 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -108,9 +108,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index c44da1c..fe3518f 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -109,8 +109,8 @@ #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 6c1bd30..e700487 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -116,9 +116,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 1a481b3..3186e73 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -109,9 +109,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 4f2b2cb..62f11d0 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -126,8 +126,8 @@ #define CONFIG_SYS_NAND_BASE 0x20100000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(1)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 7b5a5a7..b2414f3 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -149,8 +149,8 @@ #define CONFIG_SYS_NAND_BASE 0x20212000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(1)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 6871d8c..f9587db 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -141,8 +141,8 @@ #define CONFIG_SYS_NAND_BASE 0x24000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(3)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/br4.h b/include/configs/br4.h index 48cf184..fd48c8b 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -113,8 +113,8 @@ #define CONFIG_SYS_NAND_BASE 0x20000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(1)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index f8785db..c1ebff3 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -174,7 +174,7 @@ #define CONFIG_TIMESTAMP /* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ #define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index f5b8f9b..5d442a7 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -100,9 +100,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 1feaefd..0d49517 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -281,8 +281,8 @@ #define CONFIG_SYS_NAND_DBW_8 1 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) /* NOR flash */ #if defined(CONFIG_NANDBOOT) diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index df32f2a..9a77a65 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -13,7 +13,7 @@ #include -#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_MONITOR_LEN BIT(20) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 16b901b..3b7d76c 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -154,7 +154,7 @@ #define CONFIG_NET_RETRY_COUNT 10 /* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index 4eed722..2d61b15 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -114,7 +114,7 @@ #define CONFIG_NET_RETRY_COUNT 10 /* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index c50c059..584e1df 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -185,7 +185,7 @@ #define CONFIG_TIMESTAMP /* U-Boot memory configuration */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 2c5a837..08434c3 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -35,7 +35,7 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 /* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 4dd7b11..e0243cb 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -48,7 +48,7 @@ /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_OFFSET BIT(20) /* 1MiB in */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index b79000e..31ebbae 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -44,7 +44,7 @@ #define CONFIG_SYS_SDRAM_SIZE (128 << 20) #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + BIT(20)) #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ - CONFIG_SYS_MALLOC_LEN) @@ -145,9 +145,9 @@ #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_NAND_ATMEL /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #endif diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 288acf3..f626829 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,7 @@ #include -#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_MONITOR_LEN BIT(20) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 836515d..17ed6b1 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -35,16 +35,16 @@ */ #define GOFLEXHOME_OE_LOW (~(0)) #define GOFLEXHOME_OE_HIGH (~(0)) -#define GOFLEXHOME_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define GOFLEXHOME_OE_VAL_HIGH (1 << 17) /* LED pin high */ +#define GOFLEXHOME_OE_VAL_LOW BIT(29) /* USB_PWEN low */ +#define GOFLEXHOME_OE_VAL_HIGH BIT(17) /* LED pin high */ /* PHY related */ #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) /* * Commands configuration diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index c1ca56c..9d520a1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -120,7 +120,7 @@ #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ CSCONFIG_BANK_BIT_3) -#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ +#define CONFIG_SYS_DDR_TIMING_3 BIT(16) /* ext refrec */ #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ (3 << TIMING_CFG0_WRT_SHIFT) |\ (3 << TIMING_CFG0_RRT_SHIFT) |\ diff --git a/include/configs/io64.h b/include/configs/io64.h index 2a9ff37..f450ae0 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -89,7 +89,7 @@ #if defined(CONFIG_SYS_INIT_DCACHE_CS) #define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ + (CONFIG_SYS_SDRAM_BASE + BIT(30)) /* 1 GiB */ #else #define CONFIG_SYS_INIT_RAM_ADDR \ (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 2ee215f..6855450 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -114,8 +114,8 @@ #define CONFIG_SYS_NAND_BASE 0x20000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(1)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 1990b2d..817aaa0 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -496,7 +496,7 @@ * Some Kilauea stuff..., mainly fpga registers */ #define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10)) +#define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | BIT(10)) /* interrupt */ #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index dc26155..7834de7 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -136,7 +136,7 @@ MVGBE_ADV_NO_FLOW_CTRL | \ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ + BIT(9) /* Reserved bit has to be 1 */ | \ MVGBE_DO_NOT_FORCE_LINK_FAIL | \ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ MVGBE_DTE_ADV_0 | \ @@ -166,7 +166,7 @@ MVGBE_ADV_NO_FLOW_CTRL | \ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ + BIT(9) /* Reserved bit has to be 1 */ | \ MVGBE_DO_NOT_FORCE_LINK_FAIL | \ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ MVGBE_DTE_ADV_0 | \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 9a8fd50..8ac49da 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -413,7 +413,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_QSPI_BOOT #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE BIT(24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_CMD_SF diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 729205f..47e7f04 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -233,7 +233,7 @@ #ifdef CONFIG_QSPI_BOOT #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE BIT(24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_CMD_SF diff --git a/include/configs/luan.h b/include/configs/luan.h index 15e4a7e..c7477e8 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ -#define CONFIG_SYS_SRAM_SIZE (1 << 20) +#define CONFIG_SYS_SRAM_SIZE BIT(20) #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index d43db52..eb71b67 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -47,7 +47,7 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ #define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* Reserved for malloc */ #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index e909623..c083c51 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -48,7 +48,7 @@ /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_OFFSET BIT(20) /* 1MiB in */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ @@ -112,6 +112,6 @@ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_MVEBU_DDR -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_DDR_FIXED_SIZE BIT(20) /* 1GiB */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 955d0e2..9de150f 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -140,8 +140,8 @@ # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ # define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +# define CONFIG_SYS_NAND_MASK_ALE BIT(21) +# define CONFIG_SYS_NAND_MASK_CLE BIT(22) # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..e6d06a2 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -13,7 +13,7 @@ #include -#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_MONITOR_LEN BIT(20) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 41ae0a5..1de1073 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -145,11 +145,11 @@ #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define DDRCMD_EMR_OCD(pr, ohm) ( \ - (1 << 24) | /* MDDRC Command Request */ \ - (1 << 16) | /* MODE Reg BA[2:0] */ \ + BIT(24) | /* MDDRC Command Request */ \ + BIT(16) | /* MODE Reg BA[2:0] */ \ (0 << 12) | /* Outputs 0=Enabled */ \ (0 << 11) | /* RDQS */ \ - (1 << 10) | /* DQS# */ \ + BIT(10) | /* DQS# */ \ (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ ((ohm & 0x2) << 5)| /* Rtt1 */ \ @@ -162,7 +162,7 @@ #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) #define DDRCMD_MODE_REG(cas, wr) ( \ - (1 << 24) | /* MDDRC Command Request */ \ + BIT(24) | /* MDDRC Command Request */ \ (0 << 16) | /* MODE Reg BA[2:0] */ \ ((wr-1) << 9)| /* Write Recovery */ \ (cas << 4) | /* CAS */ \ @@ -171,7 +171,7 @@ #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) -#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | BIT(8)) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index fce7ead..d62714e 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -174,7 +174,7 @@ #define CONFIG_USB_ULPI_VIEWPORT #define CONFIG_MXC_USB_PORT 1 #if (CONFIG_MXC_USB_PORT == 0) -#define CONFIG_MXC_USB_PORTSC (1 << 28) +#define CONFIG_MXC_USB_PORTSC BIT(28) #define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY #else #define CONFIG_MXC_USB_PORTSC (2 << 30) diff --git a/include/configs/nas220.h b/include/configs/nas220.h index cfb85bf..e95e9f4 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -28,9 +28,9 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* power-on led, regulator, sata0, sata1 */ -#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) +#define NAS220_GE_OE_VAL_LOW (BIT(12)|BIT(14)|BIT(24)|BIT(28)) #define NAS220_GE_OE_VAL_HIGH (0) -#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) +#define NAS220_GE_OE_LOW (~(BIT(12)|BIT(14)|BIT(24)|BIT(28))) #define NAS220_GE_OE_HIGH (~(0)) /* PHY related */ @@ -38,8 +38,8 @@ #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +#define MV88E1116_RGMII_TXTM_CTRL BIT(4) +#define MV88E1116_RGMII_RXTM_CTRL BIT(5) /* * Commands configuration diff --git a/include/configs/origen.h b/include/configs/origen.h index 8f1e256..df6e010 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -44,7 +44,7 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ +#define CONFIG_SYS_MEM_TOP_HIDE BIT(20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 2390beb..803e163 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -190,8 +190,8 @@ # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ # define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +# define CONFIG_SYS_NAND_MASK_ALE BIT(21) +# define CONFIG_SYS_NAND_MASK_CLE BIT(22) # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 10415d3..d47fc35 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -86,7 +86,7 @@ (3 << 16) | /* Row Precharge Delay */ \ (2 << 20) | /* Row to Column Delay */ \ (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ + BIT(28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM @@ -217,9 +217,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(22) /* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(21) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index f6aebf4..0314c60 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -239,9 +239,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index a8dc0f0..3d29bdb 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -105,9 +105,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 13fb675..f7661fe 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -113,8 +113,8 @@ #define CONFIG_SYS_NAND_BASE 0x20000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(1)) #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ diff --git a/include/configs/qong.h b/include/configs/qong.h index d383fe8..ce51d12 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -212,8 +212,8 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_SYS_NAND_BASE CS3_BASE #define NAND_PLAT_INIT() qong_nand_plat_init(nand) -#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) -#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) +#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(24)) +#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | BIT(23)) #define QONG_NAND_WRITE(addr, cmd) \ do { \ __REG8(addr) = cmd; \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index e7bace4..f1a56a5 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -42,7 +42,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ +#define CONFIG_SYS_MEM_TOP_HIDE BIT(20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 @@ -210,9 +210,9 @@ int universal_spi_read(void); #define KEY_PWR_PMIC_NAME "MAX8998_PMIC" #define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_STATUS_MASK BIT(7) #define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 -#define KEY_PWR_INTERRUPT_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_MASK BIT(7) #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..99763bb 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -51,9 +51,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ONFI_DETECTION /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..e40401c 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -91,9 +91,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ONFI_DETECTION /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 5fb621e..b542974 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -55,9 +55,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ONFI_DETECTION /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 546d7a3..7364278 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -55,9 +55,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ONFI_DETECTION /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index e7c35ec..5541dc7 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -99,9 +99,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index c7affd6..cddf752 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -21,7 +21,7 @@ #include #define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) +#define CONFIG_DMA_COHERENT_SIZE BIT(20) #define CONFIG_ENV_SIZE (0x2000) #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) @@ -262,7 +262,7 @@ #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_NAND #define CONFIG_CMD_DFU -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE BIT(20) #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 080fc3a..f37c578 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -46,7 +46,7 @@ * Size of malloc() pool * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + BIT(20)) /* * select serial console configuration diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 6c68596..cab91de 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -49,8 +49,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) /* AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 @@ -146,7 +146,7 @@ #define CONFIG_SYS_HUSH_PARSER /* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* Command line configuration */ #include diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index 01085dc..ec004b1 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -86,8 +86,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 2cf4558..e18dc5d 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -104,8 +104,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif @@ -142,7 +142,7 @@ #define CONFIG_SPI_FLASH #define CONFIG_ATMEL_SPI #define CONFIG_SPI_FLASH_STMICRO -#define TAURUS_SPI_MASK (1 << 4) +#define TAURUS_SPI_MASK BIT(4) #define TAURUS_SPI_CS_PIN AT91_PIN_PA3 #if defined(CONFIG_SPL_BUILD) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2cf1f68..1625989 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif -#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_NONCACHED_MEMORY BIT(20) /* 1 MiB */ /* * NS16550 Configuration diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 79c7fc5..a9856f6 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -98,9 +98,9 @@ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 diff --git a/include/configs/trats.h b/include/configs/trats.h index 6808e78..e008693 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ +#define CONFIG_SYS_MEM_TOP_HIDE BIT(20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 @@ -236,9 +236,9 @@ #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_STATUS_MASK BIT(0) #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 -#define KEY_PWR_INTERRUPT_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_MASK BIT(0) #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 94c31fb..3f5a6b2 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -53,7 +53,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ +#define CONFIG_SYS_MEM_TOP_HIDE BIT(20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 @@ -216,9 +216,9 @@ int get_soft_i2c_sda_pin(void); #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_STATUS_MASK BIT(0) #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 -#define KEY_PWR_INTERRUPT_MASK (1 << 1) +#define KEY_PWR_INTERRUPT_MASK BIT(1) #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 7426bde..80dbaa0 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -75,13 +75,13 @@ #define CONFIG_STATUS_LED #define CONFIG_BOARD_SPECIFIC_LED #define CONFIG_CMD_LED /* LED command */ -#define STATUS_LED_BIT (1 << 0) +#define STATUS_LED_BIT BIT(0) #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_BIT1 (1 << 1) +#define STATUS_LED_BIT1 BIT(1) #define STATUS_LED_STATE1 STATUS_LED_ON #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -#define STATUS_LED_BIT2 (1 << 2) +#define STATUS_LED_BIT2 BIT(2) #define STATUS_LED_STATE2 STATUS_LED_ON #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 118f5ba..6d60c41 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -64,7 +64,7 @@ * Memory Info */ /* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_MALLOC_LEN BIT(20) /* 1 MiB */ /* * Board has 2 32MB banks of DRAM but there is a bug when using * both so only the first is configured diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 84571f6..6507127 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -100,9 +100,9 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif diff --git a/include/configs/vct.h b/include/configs/vct.h index 88e58ec..d508dcd 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -34,7 +34,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_MALLOC_LEN BIT(20) #define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 900b89c..06db949 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -169,7 +169,7 @@ #define VERSATILE_FLASHCTRL \ (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) /* Enable writing to flash */ -#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) +#define VERSATILE_FLASHPROG_FLVPPEN BIT(0) /* timeout values are in ticks */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 989e755..8cebbe0 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -90,9 +90,9 @@ /* * Configuration */ -#define SYS_CFG_START (1 << 31) -#define SYS_CFG_WRITE (1 << 30) -#define SYS_CFG_OSC (1 << 20) +#define SYS_CFG_START BIT(31) +#define SYS_CFG_WRITE BIT(30) +#define SYS_CFG_OSC BIT(20) #define SYS_CFG_VOLT (2 << 20) #define SYS_CFG_AMP (3 << 20) #define SYS_CFG_TEMP (4 << 20) @@ -104,12 +104,12 @@ #define SYS_CFG_DVIMODE (11 << 20) #define SYS_CFG_POWER (12 << 20) #define SYS_CFG_SITE_MB (0 << 16) -#define SYS_CFG_SITE_DB1 (1 << 16) +#define SYS_CFG_SITE_DB1 BIT(16) #define SYS_CFG_SITE_DB2 (2 << 16) #define SYS_CFG_STACK(n) ((n) << 12) -#define SYS_CFG_ERR (1 << 1) -#define SYS_CFG_COMPLETE (1 << 0) +#define SYS_CFG_ERR BIT(1) +#define SYS_CFG_COMPLETE BIT(0) /* Board info register */ #define SYS_ID V2M_SYSREGS @@ -129,7 +129,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) #define SCTL_BASE V2M_SYSCTL -#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) +#define VEXPRESS_FLASHPROG_FLVPPEN BIT(0) #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 05bc7d0..be4b245 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -108,7 +108,7 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE BIT(24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE #endif diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index bef821f..1c9d270 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -316,8 +316,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) #endif diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b6a76fe..2157f76 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -8,7 +8,7 @@ #ifndef _X86_CHROMEBOOK_H #define _X86_CHROMEBOOK_H -#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_SYS_MONITOR_LEN BIT(20) #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 3414230..9ffaf2d 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -134,8 +134,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 #define CONFIG_NAND_ACTL -#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ -#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_ALE BIT(14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE BIT(15) /* C_LA15 */ #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ #define CONFIG_SYS_NAND_ACTL_DELAY 25 #define CONFIG_SYS_NAND_QUIET_TEST diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index f966a8a..87a9a68 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -102,8 +102,8 @@ #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_NAND_ACTL -#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ -#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ +#define CONFIG_SYS_NAND_ACTL_CLE BIT(3) /* ADDR3 is CLE */ +#define CONFIG_SYS_NAND_ACTL_ALE BIT(4) /* ADDR4 is ALE */ #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ #define CONFIG_SYS_NAND_ACTL_DELAY 25 diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h index 8f36bb6..f6bbac4 100644 --- a/include/dialog_pmic.h +++ b/include/dialog_pmic.h @@ -157,18 +157,18 @@ enum { #define DA_BUCKCORE_VBCORE_1_250V 0x1E /* BUCKCORE REGISTER */ -#define DA9052_BUCKCORE_BCORECONF (1 << 7) -#define DA9052_BUCKCORE_BCOREEN (1 << 6) +#define DA9052_BUCKCORE_BCORECONF BIT(7) +#define DA9052_BUCKCORE_BCOREEN BIT(6) #define DA9052_BUCKCORE_VBCORE 63 /* SUPPLY REGISTER */ -#define DA9052_SUPPLY_VLOCK (1 << 7) -#define DA9052_SUPPLY_VMEMSWEN (1 << 6) -#define DA9052_SUPPLY_VPERISWEN (1 << 5) -#define DA9052_SUPPLY_VLDO3GO (1 << 4) -#define DA9052_SUPPLY_VLDO2GO (1 << 3) -#define DA9052_SUPPLY_VBMEMGO (1 << 2) -#define DA9052_SUPPLY_VBPROGO (1 << 1) -#define DA9052_SUPPLY_VBCOREGO (1 << 0) +#define DA9052_SUPPLY_VLOCK BIT(7) +#define DA9052_SUPPLY_VMEMSWEN BIT(6) +#define DA9052_SUPPLY_VPERISWEN BIT(5) +#define DA9052_SUPPLY_VLDO3GO BIT(4) +#define DA9052_SUPPLY_VLDO2GO BIT(3) +#define DA9052_SUPPLY_VBMEMGO BIT(2) +#define DA9052_SUPPLY_VBPROGO BIT(1) +#define DA9052_SUPPLY_VBCOREGO BIT(0) #endif /* __DIALOG_PMIC_H__ */ diff --git a/include/dm/device.h b/include/dm/device.h index 18296bb..359b968 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -19,22 +19,22 @@ struct driver_info; /* Driver is active (probed). Cleared when it is removed */ -#define DM_FLAG_ACTIVATED (1 << 0) +#define DM_FLAG_ACTIVATED BIT(0) /* DM is responsible for allocating and freeing platdata */ -#define DM_FLAG_ALLOC_PDATA (1 << 1) +#define DM_FLAG_ALLOC_PDATA BIT(1) /* DM should init this device prior to relocation */ -#define DM_FLAG_PRE_RELOC (1 << 2) +#define DM_FLAG_PRE_RELOC BIT(2) /* DM is responsible for allocating and freeing parent_platdata */ -#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3) +#define DM_FLAG_ALLOC_PARENT_PDATA BIT(3) /* DM is responsible for allocating and freeing uclass_platdata */ -#define DM_FLAG_ALLOC_UCLASS_PDATA (1 << 4) +#define DM_FLAG_ALLOC_UCLASS_PDATA BIT(4) /* Allocate driver private data on a DMA boundary */ -#define DM_FLAG_ALLOC_PRIV_DMA (1 << 5) +#define DM_FLAG_ALLOC_PRIV_DMA BIT(5) /** * struct udevice - An instance of a driver diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 4cfc0df..da66af3 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -41,7 +41,7 @@ struct uclass { struct udevice; /* Members of this uclass sequence themselves with aliases */ -#define DM_UC_FLAG_SEQ_ALIAS (1 << 0) +#define DM_UC_FLAG_SEQ_ALIAS BIT(0) /** * struct uclass_driver - Driver for the uclass diff --git a/include/dp83848.h b/include/dp83848.h index c74ce0e..c60a01f 100644 --- a/include/dp83848.h +++ b/include/dp83848.h @@ -22,64 +22,64 @@ #define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ /*--Bit definitions: DP83848_CTL_REG */ -#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ -#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ -#define DP83848_SPEED_SELECT (1 << 13) -#define DP83848_AUTONEG (1 << 12) -#define DP83848_POWER_DOWN (1 << 11) -#define DP83848_ISOLATE (1 << 10) -#define DP83848_RESTART_AUTONEG (1 << 9) -#define DP83848_DUPLEX_MODE (1 << 8) -#define DP83848_COLLISION_TEST (1 << 7) +#define DP83848_RESET BIT(15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK BIT(14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT BIT(13) +#define DP83848_AUTONEG BIT(12) +#define DP83848_POWER_DOWN BIT(11) +#define DP83848_ISOLATE BIT(10) +#define DP83848_RESTART_AUTONEG BIT(9) +#define DP83848_DUPLEX_MODE BIT(8) +#define DP83848_COLLISION_TEST BIT(7) /*--Bit definitions: DP83848_STAT_REG */ -#define DP83848_100BASE_T4 (1 << 15) -#define DP83848_100BASE_TX_FD (1 << 14) -#define DP83848_100BASE_TX_HD (1 << 13) -#define DP83848_10BASE_T_FD (1 << 12) -#define DP83848_10BASE_T_HD (1 << 11) -#define DP83848_MF_PREAMB_SUPPR (1 << 6) -#define DP83848_AUTONEG_COMP (1 << 5) -#define DP83848_RMT_FAULT (1 << 4) -#define DP83848_AUTONEG_ABILITY (1 << 3) -#define DP83848_LINK_STATUS (1 << 2) -#define DP83848_JABBER_DETECT (1 << 1) -#define DP83848_EXTEND_CAPAB (1 << 0) +#define DP83848_100BASE_T4 BIT(15) +#define DP83848_100BASE_TX_FD BIT(14) +#define DP83848_100BASE_TX_HD BIT(13) +#define DP83848_10BASE_T_FD BIT(12) +#define DP83848_10BASE_T_HD BIT(11) +#define DP83848_MF_PREAMB_SUPPR BIT(6) +#define DP83848_AUTONEG_COMP BIT(5) +#define DP83848_RMT_FAULT BIT(4) +#define DP83848_AUTONEG_ABILITY BIT(3) +#define DP83848_LINK_STATUS BIT(2) +#define DP83848_JABBER_DETECT BIT(1) +#define DP83848_EXTEND_CAPAB BIT(0) /*--definitions: DP83848_PHYID1 */ #define DP83848_PHYID1_OUI 0x2000 #define DP83848_PHYID2_OUI 0x5c90 /*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ -#define DP83848_NP (1 << 15) -#define DP83848_ACK (1 << 14) -#define DP83848_RF (1 << 13) -#define DP83848_PAUSE (1 << 10) -#define DP83848_T4 (1 << 9) -#define DP83848_TX_FDX (1 << 8) -#define DP83848_TX_HDX (1 << 7) -#define DP83848_10_FDX (1 << 6) -#define DP83848_10_HDX (1 << 5) +#define DP83848_NP BIT(15) +#define DP83848_ACK BIT(14) +#define DP83848_RF BIT(13) +#define DP83848_PAUSE BIT(10) +#define DP83848_T4 BIT(9) +#define DP83848_TX_FDX BIT(8) +#define DP83848_TX_HDX BIT(7) +#define DP83848_10_FDX BIT(6) +#define DP83848_10_HDX BIT(5) #define DP83848_AN_IEEE_802_3 0x0001 /*--Bit definitions: DP83848_ANER */ -#define DP83848_PDF (1 << 4) -#define DP83848_LP_NP_ABLE (1 << 3) -#define DP83848_NP_ABLE (1 << 2) -#define DP83848_PAGE_RX (1 << 1) -#define DP83848_LP_AN_ABLE (1 << 0) +#define DP83848_PDF BIT(4) +#define DP83848_LP_NP_ABLE BIT(3) +#define DP83848_NP_ABLE BIT(2) +#define DP83848_PAGE_RX BIT(1) +#define DP83848_LP_AN_ABLE BIT(0) /*--Bit definitions: DP83848_PHY_STAT */ -#define DP83848_RX_ERR_LATCH (1 << 13) -#define DP83848_POLARITY_STAT (1 << 12) -#define DP83848_FALSE_CAR_SENSE (1 << 11) -#define DP83848_SIG_DETECT (1 << 10) -#define DP83848_DESCRAM_LOCK (1 << 9) -#define DP83848_PAGE_RCV (1 << 8) -#define DP83848_PHY_RMT_FAULT (1 << 6) -#define DP83848_JABBER (1 << 5) -#define DP83848_AUTONEG_COMPLETE (1 << 4) -#define DP83848_LOOPBACK_STAT (1 << 3) -#define DP83848_DUPLEX (1 << 2) -#define DP83848_SPEED (1 << 1) -#define DP83848_LINK (1 << 0) +#define DP83848_RX_ERR_LATCH BIT(13) +#define DP83848_POLARITY_STAT BIT(12) +#define DP83848_FALSE_CAR_SENSE BIT(11) +#define DP83848_SIG_DETECT BIT(10) +#define DP83848_DESCRAM_LOCK BIT(9) +#define DP83848_PAGE_RCV BIT(8) +#define DP83848_PHY_RMT_FAULT BIT(6) +#define DP83848_JABBER BIT(5) +#define DP83848_AUTONEG_COMPLETE BIT(4) +#define DP83848_LOOPBACK_STAT BIT(3) +#define DP83848_DUPLEX BIT(2) +#define DP83848_SPEED BIT(1) +#define DP83848_LINK BIT(0) diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h index 2fbc804..9799270 100644 --- a/include/dt-bindings/pinctrl/am33xx.h +++ b/include/dt-bindings/pinctrl/am33xx.h @@ -11,9 +11,9 @@ #undef PULL_ENA #undef INPUT_EN -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_FAST (1 << 6) +#define PULL_DISABLE BIT(3) +#define INPUT_EN BIT(5) +#define SLEWCTRL_FAST BIT(6) /* update macro depending on INPUT_EN and PULL_ENA */ #undef PIN_OUTPUT diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index edbd250..2d7a0c9 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -19,21 +19,21 @@ #define MUX_MODE7 7 /* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) +#define PULL_ENA BIT(3) +#define PULL_UP BIT(4) +#define ALTELECTRICALSEL BIT(5) /* 34xx specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) +#define INPUT_EN BIT(8) +#define OFF_EN BIT(9) +#define OFFOUT_EN BIT(10) +#define OFFOUT_VAL BIT(11) +#define OFF_PULL_EN BIT(12) +#define OFF_PULL_UP BIT(13) +#define WAKEUP_EN BIT(14) /* 44xx specific mux bit defines */ -#define WAKEUP_EVENT (1 << 15) +#define WAKEUP_EVENT BIT(15) /* Active pin states */ #define PIN_OUTPUT 0 diff --git a/include/dwmmc.h b/include/dwmmc.h index 86a5491..397da6c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -52,59 +52,59 @@ /* Interrupt Mask register */ #define DWMCI_INTMSK_ALL 0xffffffff -#define DWMCI_INTMSK_RE (1 << 1) -#define DWMCI_INTMSK_CDONE (1 << 2) -#define DWMCI_INTMSK_DTO (1 << 3) -#define DWMCI_INTMSK_TXDR (1 << 4) -#define DWMCI_INTMSK_RXDR (1 << 5) -#define DWMCI_INTMSK_DCRC (1 << 7) -#define DWMCI_INTMSK_RTO (1 << 8) -#define DWMCI_INTMSK_DRTO (1 << 9) -#define DWMCI_INTMSK_HTO (1 << 10) -#define DWMCI_INTMSK_FRUN (1 << 11) -#define DWMCI_INTMSK_HLE (1 << 12) -#define DWMCI_INTMSK_SBE (1 << 13) -#define DWMCI_INTMSK_ACD (1 << 14) -#define DWMCI_INTMSK_EBE (1 << 15) +#define DWMCI_INTMSK_RE BIT(1) +#define DWMCI_INTMSK_CDONE BIT(2) +#define DWMCI_INTMSK_DTO BIT(3) +#define DWMCI_INTMSK_TXDR BIT(4) +#define DWMCI_INTMSK_RXDR BIT(5) +#define DWMCI_INTMSK_DCRC BIT(7) +#define DWMCI_INTMSK_RTO BIT(8) +#define DWMCI_INTMSK_DRTO BIT(9) +#define DWMCI_INTMSK_HTO BIT(10) +#define DWMCI_INTMSK_FRUN BIT(11) +#define DWMCI_INTMSK_HLE BIT(12) +#define DWMCI_INTMSK_SBE BIT(13) +#define DWMCI_INTMSK_ACD BIT(14) +#define DWMCI_INTMSK_EBE BIT(15) /* Raw interrupt Regsiter */ #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) /* CTRL register */ -#define DWMCI_CTRL_RESET (1 << 0) -#define DWMCI_CTRL_FIFO_RESET (1 << 1) -#define DWMCI_CTRL_DMA_RESET (1 << 2) -#define DWMCI_DMA_EN (1 << 5) -#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) -#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_CTRL_RESET BIT(0) +#define DWMCI_CTRL_FIFO_RESET BIT(1) +#define DWMCI_CTRL_DMA_RESET BIT(2) +#define DWMCI_DMA_EN BIT(5) +#define DWMCI_CTRL_SEND_AS_CCSD BIT(10) +#define DWMCI_IDMAC_EN BIT(25) #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ DWMCI_CTRL_DMA_RESET) /* CMD register */ -#define DWMCI_CMD_RESP_EXP (1 << 6) -#define DWMCI_CMD_RESP_LENGTH (1 << 7) -#define DWMCI_CMD_CHECK_CRC (1 << 8) -#define DWMCI_CMD_DATA_EXP (1 << 9) -#define DWMCI_CMD_RW (1 << 10) -#define DWMCI_CMD_SEND_STOP (1 << 12) -#define DWMCI_CMD_ABORT_STOP (1 << 14) -#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) -#define DWMCI_CMD_UPD_CLK (1 << 21) -#define DWMCI_CMD_USE_HOLD_REG (1 << 29) -#define DWMCI_CMD_START (1 << 31) +#define DWMCI_CMD_RESP_EXP BIT(6) +#define DWMCI_CMD_RESP_LENGTH BIT(7) +#define DWMCI_CMD_CHECK_CRC BIT(8) +#define DWMCI_CMD_DATA_EXP BIT(9) +#define DWMCI_CMD_RW BIT(10) +#define DWMCI_CMD_SEND_STOP BIT(12) +#define DWMCI_CMD_ABORT_STOP BIT(14) +#define DWMCI_CMD_PRV_DAT_WAIT BIT(13) +#define DWMCI_CMD_UPD_CLK BIT(21) +#define DWMCI_CMD_USE_HOLD_REG BIT(29) +#define DWMCI_CMD_START BIT(31) /* CLKENA register */ -#define DWMCI_CLKEN_ENABLE (1 << 0) -#define DWMCI_CLKEN_LOW_PWR (1 << 16) +#define DWMCI_CLKEN_ENABLE BIT(0) +#define DWMCI_CLKEN_LOW_PWR BIT(16) /* Card-type registe */ #define DWMCI_CTYPE_1BIT 0 -#define DWMCI_CTYPE_4BIT (1 << 0) -#define DWMCI_CTYPE_8BIT (1 << 16) +#define DWMCI_CTYPE_4BIT BIT(0) +#define DWMCI_CTYPE_8BIT BIT(16) /* Status Register */ -#define DWMCI_BUSY (1 << 9) +#define DWMCI_BUSY BIT(9) /* FIFOTH Register */ #define MSIZE(x) ((x) << 28) @@ -113,21 +113,21 @@ #define RX_WMARK_SHIFT 16 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) -#define DWMCI_IDMAC_OWN (1 << 31) -#define DWMCI_IDMAC_CH (1 << 4) -#define DWMCI_IDMAC_FS (1 << 3) -#define DWMCI_IDMAC_LD (1 << 2) +#define DWMCI_IDMAC_OWN BIT(31) +#define DWMCI_IDMAC_CH BIT(4) +#define DWMCI_IDMAC_FS BIT(3) +#define DWMCI_IDMAC_LD BIT(2) /* Bus Mode Register */ -#define DWMCI_BMOD_IDMAC_RESET (1 << 0) -#define DWMCI_BMOD_IDMAC_FB (1 << 1) -#define DWMCI_BMOD_IDMAC_EN (1 << 7) +#define DWMCI_BMOD_IDMAC_RESET BIT(0) +#define DWMCI_BMOD_IDMAC_FB BIT(1) +#define DWMCI_BMOD_IDMAC_EN BIT(7) /* UHS register */ -#define DWMCI_DDR_MODE (1 << 16) +#define DWMCI_DDR_MODE BIT(16) /* quirks */ -#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +#define DWMCI_QUIRK_DISABLE_SMU BIT(0) struct dwmci_host { char *name; diff --git a/include/ec_commands.h b/include/ec_commands.h index 78baab1..5310de9 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -57,13 +57,13 @@ #define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ #define EC_LPC_ADDR_MEMMAP 0x900 #define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ @@ -545,7 +545,7 @@ struct ec_response_test_protocol { /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) struct ec_response_get_protocol_info { /* Fields which exist if at least protocol version 3 supported */ @@ -637,26 +637,26 @@ struct ec_params_flash_erase { /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by * re-requesting the desired flags, or by a hard reset if that fails. */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entile flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) struct ec_params_flash_protect { uint32_t mask; /* Bits in flags to apply */ @@ -891,8 +891,8 @@ enum ec_led_id { }; /* LED control flags */ -#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { EC_LED_COLOR_RED = 0, @@ -1459,16 +1459,16 @@ struct ec_response_power_info { #define EC_CMD_I2C_PASSTHRU 0x9e /* Slave address is 10 (not 7) bit */ -#define EC_I2C_FLAG_10BIT (1 << 16) +#define EC_I2C_FLAG_10BIT BIT(16) /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ (1 << 15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ #define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) @@ -1576,8 +1576,8 @@ enum ec_reboot_cmd { }; /* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ struct ec_params_reboot_ec { uint8_t cmd; /* enum ec_reboot_cmd */ diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h index ccae390..b6b8476 100644 --- a/include/faraday/ftahbc020s.h +++ b/include/faraday/ftahbc020s.h @@ -39,9 +39,9 @@ struct ftahbc02s { /* * FTAHBC020S_CR - Interrupt Control Register */ -#define FTAHBC020S_CR_INTSTS (1 << 24) +#define FTAHBC020S_CR_INTSTS BIT(24) #define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) +#define FTAHBC020S_CR_INTSMASK BIT(16) +#define FTAHBC020S_CR_REMAP BIT(0) #endif /* __FTAHBC020S_H */ diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h index 43152aa..a94c60f 100644 --- a/include/faraday/ftpci100.h +++ b/include/faraday/ftpci100.h @@ -36,10 +36,10 @@ struct ftpci100_ahbc { /* * PCI_INT_MASK's bit definitions */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) +#define PCI_INTA_ENABLE BIT(22) +#define PCI_INTB_ENABLE BIT(23) +#define PCI_INTC_ENABLE BIT(24) +#define PCI_INTD_ENABLE BIT(25) /* * PCI_MEM_BASE_SIZE1's constant definitions diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h index b1131e5..96e24e6 100644 --- a/include/faraday/ftpmu010.h +++ b/include/faraday/ftpmu010.h @@ -81,14 +81,14 @@ struct ftpmu010 { /* * OSC Control Register */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) +#define FTPMU010_OSCC_OSCH_TRI BIT(11) +#define FTPMU010_OSCC_OSCH_STABLE BIT(9) +#define FTPMU010_OSCC_OSCH_OFF BIT(8) -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) +#define FTPMU010_OSCC_OSCL_TRI BIT(3) +#define FTPMU010_OSCC_OSCL_RTCLSEL BIT(2) +#define FTPMU010_OSCC_OSCL_STABLE BIT(1) +#define FTPMU010_OSCC_OSCL_OFF BIT(0) /* * Power Mode Register @@ -100,37 +100,37 @@ struct ftpmu010 { #define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) #define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) #define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) +#define FTPMU010_PMODE_FCS BIT(2) +#define FTPMU010_PMODE_TURBO BIT(1) +#define FTPMU010_PMODE_SLEEP BIT(0) /* * Power Manager Status Register */ -#define FTPMU010_PMSR_SMR (1 << 10) +#define FTPMU010_PMSR_SMR BIT(10) -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) +#define FTPMU010_PMSR_RDH BIT(2) +#define FTPMU010_PMSR_PH BIT(1) +#define FTPMU010_PMSR_CKEHLOW BIT(0) /* * Multi-Function Port Setting Register */ -#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) -#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) -#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) -#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) -#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) -#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) -#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) -#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) -#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) -#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) -#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) +#define FTPMU010_MFPSR_DEBUGSEL BIT(17) +#define FTPMU010_MFPSR_DMA0PINSEL BIT(16) +#define FTPMU010_MFPSR_DMA1PINSEL BIT(15) +#define FTPMU010_MFPSR_MODEMPINSEL BIT(14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL BIT(13) +#define FTPMU010_MFPSR_PWM1PINSEL BIT(11) +#define FTPMU010_MFPSR_PWM0PINSEL BIT(10) +#define FTPMU010_MFPSR_IRDACLKSEL BIT(9) +#define FTPMU010_MFPSR_UARTCLKSEL BIT(8) +#define FTPMU010_MFPSR_SSPCLKSEL BIT(6) +#define FTPMU010_MFPSR_I2SCLKSEL BIT(5) +#define FTPMU010_MFPSR_AC97CLKSEL BIT(4) +#define FTPMU010_MFPSR_AC97PINSEL BIT(3) +#define FTPMU010_MFPSR_TRIAHBDIS BIT(1) +#define FTPMU010_MFPSR_TRIAHBDBG BIT(0) /* * PLL/DLL Control Register 0 @@ -141,15 +141,15 @@ struct ftpmu010 { * Datasheet indicated it has 2 bit which was wrong. */ #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) -#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) +#define FTPMU010_PDLLCR0_DLLFRAG(cr0) BIT(19) +#define FTPMU010_PDLLCR0_DLLSTSEL BIT(18) +#define FTPMU010_PDLLCR0_DLLSTABLE BIT(17) +#define FTPMU010_PDLLCR0_DLLDIS BIT(16) #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) +#define FTPMU010_PDLLCR0_PLL1STSEL BIT(2) +#define FTPMU010_PDLLCR0_PLL1STABLE BIT(1) +#define FTPMU010_PDLLCR0_PLL1DIS BIT(0) /* * SDRAM Signal Hold Time Control Register @@ -157,13 +157,13 @@ struct ftpmu010 { #define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) #define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) #define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) -#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) -#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) -#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) -#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) -#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) -#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) -#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) +#define FTPMU010_SDRAMHTC_EBICTRL_DCSR BIT(18) +#define FTPMU010_SDRAMHTC_EBIDATA_DCSR BIT(17) +#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR BIT(16) +#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR BIT(15) +#define FTPMU010_SDRAMHTC_CKE_DCSR BIT(14) +#define FTPMU010_SDRAMHTC_DQM_DCSR BIT(13) +#define FTPMU010_SDRAMHTC_SDCLK_DCSR BIT(12) #ifndef __ASSEMBLY__ void ftpmu010_32768osc_enable(void); diff --git a/include/faraday/ftsdc010.h b/include/faraday/ftsdc010.h index 9bfdef9..ce45ff4 100644 --- a/include/faraday/ftsdc010.h +++ b/include/faraday/ftsdc010.h @@ -79,26 +79,26 @@ int ftsdc010_mmc_init(int dev_index); /* 0x00 - command register */ #define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) -#define FTSDC010_CMD_NEED_RSP (1 << 6) -#define FTSDC010_CMD_LONG_RSP (1 << 7) -#define FTSDC010_CMD_APP_CMD (1 << 8) -#define FTSDC010_CMD_CMD_EN (1 << 9) -#define FTSDC010_CMD_SDC_RST (1 << 10) -#define FTSDC010_CMD_MMC_INT_STOP (1 << 11) +#define FTSDC010_CMD_NEED_RSP BIT(6) +#define FTSDC010_CMD_LONG_RSP BIT(7) +#define FTSDC010_CMD_APP_CMD BIT(8) +#define FTSDC010_CMD_CMD_EN BIT(9) +#define FTSDC010_CMD_SDC_RST BIT(10) +#define FTSDC010_CMD_MMC_INT_STOP BIT(11) /* 0x18 - responded command register */ #define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) -#define FTSDC010_RSP_CMD_APP (1 << 6) +#define FTSDC010_RSP_CMD_APP BIT(6) /* 0x1c - data control register */ #define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) -#define FTSDC010_DCR_DATA_WRITE (1 << 4) -#define FTSDC010_DCR_DMA_EN (1 << 5) -#define FTSDC010_DCR_DATA_EN (1 << 6) +#define FTSDC010_DCR_DATA_WRITE BIT(4) +#define FTSDC010_DCR_DMA_EN BIT(5) +#define FTSDC010_DCR_DATA_EN BIT(6) #ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_DCR_FIFOTH (1 << 7) +#define FTSDC010_DCR_FIFOTH BIT(7) #define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) -#define FTSDC010_DCR_FIFO_RST (1 << 10) +#define FTSDC010_DCR_FIFO_RST BIT(10) #endif /* CONFIG_FTSDC010_SDIO */ #define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ @@ -112,25 +112,25 @@ int ftsdc010_mmc_init(int dev_index); #define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 /* 0x28 - status register */ -#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) -#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) -#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) -#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) -#define FTSDC010_STATUS_CMD_SEND (1 << 6) -#define FTSDC010_STATUS_DATA_END (1 << 7) -#define FTSDC010_STATUS_FIFO_URUN (1 << 8) -#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) -#define FTSDC010_STATUS_CARD_CHANGE (1 << 10) -#define FTSDC010_STATUS_CARD_DETECT (1 << 11) -#define FTSDC010_STATUS_WRITE_PROT (1 << 12) +#define FTSDC010_STATUS_RSP_CRC_FAIL BIT(0) +#define FTSDC010_STATUS_DATA_CRC_FAIL BIT(1) +#define FTSDC010_STATUS_RSP_TIMEOUT BIT(2) +#define FTSDC010_STATUS_DATA_TIMEOUT BIT(3) +#define FTSDC010_STATUS_RSP_CRC_OK BIT(4) +#define FTSDC010_STATUS_DATA_CRC_OK BIT(5) +#define FTSDC010_STATUS_CMD_SEND BIT(6) +#define FTSDC010_STATUS_DATA_END BIT(7) +#define FTSDC010_STATUS_FIFO_URUN BIT(8) +#define FTSDC010_STATUS_FIFO_ORUN BIT(9) +#define FTSDC010_STATUS_CARD_CHANGE BIT(10) +#define FTSDC010_STATUS_CARD_DETECT BIT(11) +#define FTSDC010_STATUS_WRITE_PROT BIT(12) #ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ -#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ -#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ -#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ -#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) +#define FTSDC010_STATUS_CP_READY BIT(13) /* reserved ? */ +#define FTSDC010_STATUS_CP_BUF_READY BIT(14) /* reserved ? */ +#define FTSDC010_STATUS_PLAIN_TEXT_READY BIT(15) /* reserved ? */ +#define FTSDC010_STATUS_SDIO_IRPT BIT(16) /* SDIO card intr */ +#define FTSDC010_STATUS_DATA0_STATUS BIT(17) #endif /* CONFIG_FTSDC010_SDIO */ #define FTSDC010_STATUS_RSP_ERROR \ (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT) @@ -143,39 +143,39 @@ int ftsdc010_mmc_init(int dev_index); | FTSDC010_STATUS_DATA_END) /* 0x2c - clear register */ -#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) -#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) -#define FTSDC010_CLR_RSP_CRC_OK (1 << 4) -#define FTSDC010_CLR_DATA_CRC_OK (1 << 5) -#define FTSDC010_CLR_CMD_SEND (1 << 6) -#define FTSDC010_CLR_DATA_END (1 << 7) -#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ -#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ -#define FTSDC010_CLR_CARD_CHANGE (1 << 10) +#define FTSDC010_CLR_RSP_CRC_FAIL BIT(0) +#define FTSDC010_CLR_DATA_CRC_FAIL BIT(1) +#define FTSDC010_CLR_RSP_TIMEOUT BIT(2) +#define FTSDC010_CLR_DATA_TIMEOUT BIT(3) +#define FTSDC010_CLR_RSP_CRC_OK BIT(4) +#define FTSDC010_CLR_DATA_CRC_OK BIT(5) +#define FTSDC010_CLR_CMD_SEND BIT(6) +#define FTSDC010_CLR_DATA_END BIT(7) +#define FTSDC010_STATUS_FIFO_URUN BIT(8) /* reserved ? */ +#define FTSDC010_STATUS_FIFO_ORUN BIT(9) /* reserved ? */ +#define FTSDC010_CLR_CARD_CHANGE BIT(10) #ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_CLR_SDIO_IRPT (1 << 16) +#define FTSDC010_CLR_SDIO_IRPT BIT(16) #endif /* CONFIG_FTSDC010_SDIO */ /* 0x30 - interrupt mask register */ -#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) -#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) -#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) -#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) -#define FTSDC010_INT_MASK_CMD_SEND (1 << 6) -#define FTSDC010_INT_MASK_DATA_END (1 << 7) -#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) -#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) -#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) +#define FTSDC010_INT_MASK_RSP_CRC_FAIL BIT(0) +#define FTSDC010_INT_MASK_DATA_CRC_FAIL BIT(1) +#define FTSDC010_INT_MASK_RSP_TIMEOUT BIT(2) +#define FTSDC010_INT_MASK_DATA_TIMEOUT BIT(3) +#define FTSDC010_INT_MASK_RSP_CRC_OK BIT(4) +#define FTSDC010_INT_MASK_DATA_CRC_OK BIT(5) +#define FTSDC010_INT_MASK_CMD_SEND BIT(6) +#define FTSDC010_INT_MASK_DATA_END BIT(7) +#define FTSDC010_INT_MASK_FIFO_URUN BIT(8) +#define FTSDC010_INT_MASK_FIFO_ORUN BIT(9) +#define FTSDC010_INT_MASK_CARD_CHANGE BIT(10) #ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_INT_MASK_CP_READY (1 << 13) -#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) -#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) -#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) -#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) +#define FTSDC010_INT_MASK_CP_READY BIT(13) +#define FTSDC010_INT_MASK_CP_BUF_READY BIT(14) +#define FTSDC010_INT_MASK_PLAIN_TEXT_READY BIT(15) +#define FTSDC010_INT_MASK_SDIO_IRPT BIT(16) +#define FTSDC010_STATUS_DATA0_STATUS BIT(17) #endif /* CONFIG_FTSDC010_SDIO */ /* ? */ @@ -184,34 +184,34 @@ int ftsdc010_mmc_init(int dev_index); /* 0x34 - power control register */ #define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) -#define FTSDC010_PCR_POWER_ON (1 << 4) +#define FTSDC010_PCR_POWER_ON BIT(4) /* 0x38 - clock control register */ #define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) -#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ -#define FTSDC010_CCR_CLK_DIS (1 << 8) -#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */ +#define FTSDC010_CCR_CLK_SD BIT(7) /* 0: MMC, 1: SD */ +#define FTSDC010_CCR_CLK_DIS BIT(8) +#define FTSDC010_CCR_CLK_HISPD BIT(9) /* high speed */ /* card type */ #define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE #define FTSDC010_CARD_TYPE_MMC 0x0 /* 0x3c - bus width register */ -#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */ -#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */ -#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */ +#define FTSDC010_BWR_MODE_1BIT BIT(0) /* 1 bit mode enabled */ +#define FTSDC010_BWR_MODE_8BIT BIT(1) /* 8 bit mode enabled */ +#define FTSDC010_BWR_MODE_4BIT BIT(2) /* 4 bit mode enabled */ #define FTSDC010_BWR_MODE_MASK (7 << 0) #define FTSDC010_BWR_MODE_SHIFT (0) #define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */ -#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */ +#define FTSDC010_BWR_CAPS_4BIT BIT(3) /* 1,4 bits mode supported */ #define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */ #define FTSDC010_BWR_CAPS_MASK (3 << 3) #define FTSDC010_BWR_CAPS_SHIFT (3) -#define FTSDC010_BWR_CARD_DETECT (1 << 5) +#define FTSDC010_BWR_CARD_DETECT BIT(5) /* 0x44 or 0x9c - feature register */ #define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) -#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) +#define FTSDC010_FEATURE_CPRM_FUNCTION BIT(8) #define FTSDC010_FIFO_DEPTH_4 0x04 #define FTSDC010_FIFO_DEPTH_8 0x08 @@ -228,14 +228,14 @@ int ftsdc010_mmc_init(int dev_index); /* 0x6c - sdio control register 1 */ #define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) -#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) -#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) -#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) +#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE BIT(12) +#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN BIT(13) +#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE BIT(14) #define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) /* 0x70 - sdio control register 2 */ -#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) -#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) +#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT BIT(0) +#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT BIT(1) /* 0x74 - sdio status register */ #define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h index 8e296c0..e266c8c 100644 --- a/include/faraday/ftsdmc020.h +++ b/include/faraday/ftsdmc020.h @@ -44,32 +44,32 @@ /* * Configuration Register */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) +#define FTSDMC020_CR_SREF BIT(0) +#define FTSDMC020_CR_PWDN BIT(1) +#define FTSDMC020_CR_ISMR BIT(2) +#define FTSDMC020_CR_IREF BIT(3) +#define FTSDMC020_CR_IPREC BIT(4) +#define FTSDMC020_CR_REFTYPE BIT(5) /* * SDRAM External Bank Base/Size Register */ -#define FTSDMC020_BANK_ENABLE (1 << 28) +#define FTSDMC020_BANK_ENABLE BIT(28) #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) #define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X8 BIT(12) #define FTSDMC020_BANK_DDW_X16 (2 << 12) #define FTSDMC020_BANK_DDW_X32 (3 << 12) #define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_64M BIT(8) #define FTSDMC020_BANK_DSZ_128M (2 << 8) #define FTSDMC020_BANK_DSZ_256M (3 << 8) #define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_16 BIT(4) #define FTSDMC020_BANK_MBW_32 (2 << 4) #define FTSDMC020_BANK_SIZE_1M 0x0 @@ -86,6 +86,6 @@ * Arbiter Control Register */ #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) +#define FTSDMC020_ACR_TOE BIT(8) #endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h index b893b5e..51f5b8e 100644 --- a/include/faraday/ftsdmc021.h +++ b/include/faraday/ftsdmc021.h @@ -64,24 +64,24 @@ struct ftsdmc021 { #define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ #define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ /* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) +#define FTSDMC021_CR1_MA2T(x) BIT(16) /* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ #define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) /* * Configuration Register 2 */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) +#define FTSDMC021_CR2_SREF BIT(0) /* Self-Refresh Mode */ +#define FTSDMC021_CR2_PWDN BIT(1) /* Power Down Operation Mode */ +#define FTSDMC021_CR2_ISMR BIT(2) /* Start Set-Mode-Register */ +#define FTSDMC021_CR2_IREF BIT(3) /* Init Refresh Start Flag */ +#define FTSDMC021_CR2_IPREC BIT(4) /* Init Pre-Charge Start Flag */ +#define FTSDMC021_CR2_REFTYPE BIT(5) /* * SDRAM External Bank Base/Size Register */ -#define FTSDMC021_BANK_ENABLE (1 << 12) +#define FTSDMC021_BANK_ENABLE BIT(12) /* 12-bit base address of external bank. * Default value is 0x800. @@ -104,15 +104,15 @@ struct ftsdmc021 { * Flush Request Register */ #define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ +#define FTSDMC021_FRR_FLUSHCMPLT BIT(3) /* Flush Req Flag */ /* * External Bus Interface Support Register (EBISR) */ #define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ +#define FTSDMC021_EBISR_PRSMR BIT(12) /* Pre-SMR */ +#define FTSDMC021_EBISR_POPREC BIT(13) +#define FTSDMC021_EBISR_POSMR BIT(14) /* Post-SMR */ /* * Controller Revision Register (CRR, Read Only) diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h index 54120ab..59584f8 100644 --- a/include/faraday/ftsmc020.h +++ b/include/faraday/ftsmc020.h @@ -31,14 +31,14 @@ void ftsmc020_init(void); /* * Memory Bank Configuration Register */ -#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_ENABLE BIT(28) #define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) -#define FTSMC020_BANK_WPROT (1 << 11) +#define FTSMC020_BANK_WPROT BIT(11) -#define FTSMC020_BANK_TYPE1 (1 << 10) -#define FTSMC020_BANK_TYPE2 (1 << 9) -#define FTSMC020_BANK_TYPE3 (1 << 8) +#define FTSMC020_BANK_TYPE1 BIT(10) +#define FTSMC020_BANK_TYPE2 BIT(9) +#define FTSMC020_BANK_TYPE3 BIT(8) #define FTSMC020_BANK_SIZE_32K (0xb << 4) #define FTSMC020_BANK_SIZE_64K (0xc << 4) @@ -62,7 +62,7 @@ void ftsmc020_init(void); */ #define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) #define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_RBE BIT(20) #define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) #define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) #define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h index 2ab68d1..bbb590e 100644 --- a/include/faraday/fttmr010.h +++ b/include/faraday/fttmr010.h @@ -32,30 +32,30 @@ struct fttmr010 { /* * Timer Control Register */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) +#define FTTMR010_TM3_UPDOWN BIT(11) +#define FTTMR010_TM2_UPDOWN BIT(10) +#define FTTMR010_TM1_UPDOWN BIT(9) +#define FTTMR010_TM3_OFENABLE BIT(8) +#define FTTMR010_TM3_CLOCK BIT(7) +#define FTTMR010_TM3_ENABLE BIT(6) +#define FTTMR010_TM2_OFENABLE BIT(5) +#define FTTMR010_TM2_CLOCK BIT(4) +#define FTTMR010_TM2_ENABLE BIT(3) +#define FTTMR010_TM1_OFENABLE BIT(2) +#define FTTMR010_TM1_CLOCK BIT(1) +#define FTTMR010_TM1_ENABLE BIT(0) /* * Timer Interrupt State & Mask Registers */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) +#define FTTMR010_TM3_OVERFLOW BIT(8) +#define FTTMR010_TM3_MATCH2 BIT(7) +#define FTTMR010_TM3_MATCH1 BIT(6) +#define FTTMR010_TM2_OVERFLOW BIT(5) +#define FTTMR010_TM2_MATCH2 BIT(4) +#define FTTMR010_TM2_MATCH1 BIT(3) +#define FTTMR010_TM1_OVERFLOW BIT(2) +#define FTTMR010_TM1_MATCH2 BIT(1) +#define FTTMR010_TM1_MATCH1 BIT(0) #endif /* __FTTMR010_H */ diff --git a/include/faraday/ftwdt010_wdt.h b/include/faraday/ftwdt010_wdt.h index 2c5a366..75e0a43 100644 --- a/include/faraday/ftwdt010_wdt.h +++ b/include/faraday/ftwdt010_wdt.h @@ -43,11 +43,11 @@ struct ftwdt010_wdt { #define FTWDT010_WDRESTART_MAGIC 0x5AB9 /* WDCR - Watch Dog Timer Control Register */ -#define FTWDT010_WDCR_ENABLE (1 << 0) -#define FTWDT010_WDCR_RST (1 << 1) -#define FTWDT010_WDCR_INTR (1 << 2) +#define FTWDT010_WDCR_ENABLE BIT(0) +#define FTWDT010_WDCR_RST BIT(1) +#define FTWDT010_WDCR_INTR BIT(2) /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ -#define FTWDT010_WDCR_EXT (1 << 3) +#define FTWDT010_WDCR_EXT BIT(3) /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. * The clock source PCLK cannot be gated when system sleeps, even if * WDCLOCK bit is turned on. @@ -60,7 +60,7 @@ struct ftwdt010_wdt { * If the system does not need an external clock, * just keep WdCR[WdClock] bit in its default value. */ -#define FTWDT010_WDCR_CLOCK (1 << 4) +#define FTWDT010_WDCR_CLOCK BIT(4) /* * WDSTATUS - Watch Dog Timer Status Register @@ -72,7 +72,7 @@ struct ftwdt010_wdt { * WDCLEAR - Watch Dog Timer Clear Register * Writing one to this register will clear WDSTATUS. */ -#define FTWDT010_WDCLEAR (1 << 0) +#define FTWDT010_WDCLEAR BIT(0) /* * WDINTRLEN - Watch Dog Timer Interrupt Length diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 4099a74..8c271a8 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -77,13 +77,13 @@ typedef struct { } fsl_ddr_info_t; /* Compute steps */ -#define STEP_GET_SPD (1 << 0) -#define STEP_COMPUTE_DIMM_PARMS (1 << 1) -#define STEP_COMPUTE_COMMON_PARMS (1 << 2) -#define STEP_GATHER_OPTS (1 << 3) -#define STEP_ASSIGN_ADDRESSES (1 << 4) -#define STEP_COMPUTE_REGS (1 << 5) -#define STEP_PROGRAM_REGS (1 << 6) +#define STEP_GET_SPD BIT(0) +#define STEP_COMPUTE_DIMM_PARMS BIT(1) +#define STEP_COMPUTE_COMMON_PARMS BIT(2) +#define STEP_GATHER_OPTS BIT(3) +#define STEP_ASSIGN_ADDRESSES BIT(4) +#define STEP_COMPUTE_REGS BIT(5) +#define STEP_PROGRAM_REGS BIT(6) #define STEP_ALL 0xFFF unsigned long long diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e5b6e03..686d29e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -207,7 +207,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR_ODT_120ohm 0x6 #endif -#define DDR_INIT_ADDR_EXT_UIA (1 << 31) +#define DDR_INIT_ADDR_EXT_UIA BIT(31) /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { diff --git a/include/fsl_debug_server.h b/include/fsl_debug_server.h index 28d8adb..de4c852 100644 --- a/include/fsl_debug_server.h +++ b/include/fsl_debug_server.h @@ -22,7 +22,7 @@ */ #define DEBUG_SERVER_VER_MINOR 1 -#define DEBUG_SERVER_INIT_STATUS (1 << 0) +#define DEBUG_SERVER_INIT_STATUS BIT(0) #define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001) int debug_server_init(void); diff --git a/include/fsl_memac.h b/include/fsl_memac.h index bed2a40..60e5f7b 100644 --- a/include/fsl_memac.h +++ b/include/fsl_memac.h @@ -239,22 +239,22 @@ struct memac_mdio_controller { }; #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) -#define MDIO_STAT_BSY (1 << 0) -#define MDIO_STAT_RD_ER (1 << 1) -#define MDIO_STAT_PRE (1 << 5) -#define MDIO_STAT_ENC (1 << 6) +#define MDIO_STAT_BSY BIT(0) +#define MDIO_STAT_RD_ER BIT(1) +#define MDIO_STAT_PRE BIT(5) +#define MDIO_STAT_ENC BIT(6) #define MDIO_STAT_HOLD_15_CLK (7 << 2) -#define MDIO_STAT_NEG (1 << 23) +#define MDIO_STAT_NEG BIT(23) #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) -#define MDIO_CTL_PRE_DIS (1 << 10) -#define MDIO_CTL_SCAN_EN (1 << 11) -#define MDIO_CTL_POST_INC (1 << 14) -#define MDIO_CTL_READ (1 << 15) +#define MDIO_CTL_PRE_DIS BIT(10) +#define MDIO_CTL_SCAN_EN BIT(11) +#define MDIO_CTL_POST_INC BIT(14) +#define MDIO_CTL_READ BIT(15) #define MDIO_DATA(x) (x & 0xffff) -#define MDIO_DATA_BSY (1 << 31) +#define MDIO_DATA_BSY BIT(31) struct fsl_enet_mac; diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h index e8a67d5..87a3ca8 100644 --- a/include/fsl_pmic.h +++ b/include/fsl_pmic.h @@ -87,24 +87,24 @@ enum { }; /* REG_POWER_MISC */ -#define GPO1EN (1 << 6) -#define GPO1STBY (1 << 7) -#define GPO2EN (1 << 8) -#define GPO2STBY (1 << 9) -#define GPO3EN (1 << 10) -#define GPO3STBY (1 << 11) -#define GPO4EN (1 << 12) -#define GPO4STBY (1 << 13) -#define PWGT1SPIEN (1 << 15) -#define PWGT2SPIEN (1 << 16) -#define PWUP (1 << 21) +#define GPO1EN BIT(6) +#define GPO1STBY BIT(7) +#define GPO2EN BIT(8) +#define GPO2STBY BIT(9) +#define GPO3EN BIT(10) +#define GPO3STBY BIT(11) +#define GPO4EN BIT(12) +#define GPO4STBY BIT(13) +#define PWGT1SPIEN BIT(15) +#define PWGT2SPIEN BIT(16) +#define PWUP BIT(21) /* Power Control 0 */ -#define COINCHEN (1 << 23) -#define BATTDETEN (1 << 19) +#define COINCHEN BIT(23) +#define BATTDETEN BIT(19) /* Interrupt status 1 */ -#define RTCRSTI (1 << 7) +#define RTCRSTI BIT(7) /* MC34708 Definitions */ #define SWx_VOLT_MASK_MC34708 0x3F @@ -112,8 +112,8 @@ enum { #define SWx_1_300V_MC34708 0x34 #define TIMER_MASK_MC34708 0x300 #define TIMER_4S_MC34708 0x100 -#define VUSBSEL_MC34708 (1 << 2) -#define VUSBEN_MC34708 (1 << 3) +#define VUSBSEL_MC34708 BIT(2) +#define VUSBEN_MC34708 BIT(3) #define SWBST_CTRL 31 #define SWBST_AUTO 0x8 diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 33d9f03..d49cb18 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -41,27 +41,27 @@ struct ccsr_usb_phy { u8 res_dc[0x334]; }; -#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) +#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN BIT(0) +#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN BIT(1) +#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN BIT(1) +#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV BIT(0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN BIT(0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN BIT(1) +#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN BIT(13) #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) -#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) +#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN BIT(20) #endif -#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV BIT(4) #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) -#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) -#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN BIT(21) +#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID BIT(0) +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN BIT(7) #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4) #define INC_DCNT_THRESHOLD_25MV (0 << 4) -#define INC_DCNT_THRESHOLD_50MV (1 << 4) +#define INC_DCNT_THRESHOLD_50MV BIT(4) #define DEC_DCNT_THRESHOLD_25MV (2 << 4) #define DEC_DCNT_THRESHOLD_50MV (3 << 4) #else @@ -76,7 +76,7 @@ struct ccsr_usb_phy { u8 res[0xe4]; }; #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22) -#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20) +#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL BIT(20) #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0 diff --git a/include/i2s.h b/include/i2s.h index 8dd2cc3..f057295 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -32,7 +32,7 @@ * Specifies whether the DAI can also support inverted clocks for the specified * format. */ -#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ +#define SND_SOC_DAIFMT_NB_NF BIT(8) /* normal bit clock + frame */ #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ @@ -44,7 +44,7 @@ * i.e. if the codec is clk and FRM master then the interface is * clk and frame slave. */ -#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ +#define SND_SOC_DAIFMT_CBM_CFM BIT(12) /* codec clk & FRM master */ #define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ #define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ #define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ diff --git a/include/libata.h b/include/libata.h index 5b7d7b3..61984f4 100644 --- a/include/libata.h +++ b/include/libata.h @@ -35,7 +35,7 @@ enum { ATA_ID_EIDE_DMA_MIN = 65, ATA_ID_EIDE_PIO = 67, ATA_ID_EIDE_PIO_IORDY = 68, - ATA_ID_PIO4 = (1 << 1), + ATA_ID_PIO4 = BIT(1), ATA_ID_QUEUE_DEPTH = 75, ATA_ID_SATA_CAP = 76, ATA_ID_SATA_FEATURES = 78, @@ -51,35 +51,35 @@ enum { ATA_PCI_CTL_OFS = 2, - ATA_PIO0 = (1 << 0), - ATA_PIO1 = ATA_PIO0 | (1 << 1), - ATA_PIO2 = ATA_PIO1 | (1 << 2), - ATA_PIO3 = ATA_PIO2 | (1 << 3), - ATA_PIO4 = ATA_PIO3 | (1 << 4), - ATA_PIO5 = ATA_PIO4 | (1 << 5), - ATA_PIO6 = ATA_PIO5 | (1 << 6), - - ATA_SWDMA0 = (1 << 0), - ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1), - ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2), - - ATA_SWDMA2_ONLY = (1 << 2), - - ATA_MWDMA0 = (1 << 0), - ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1), - ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2), - - ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2), - ATA_MWDMA2_ONLY = (1 << 2), - - ATA_UDMA0 = (1 << 0), - ATA_UDMA1 = ATA_UDMA0 | (1 << 1), - ATA_UDMA2 = ATA_UDMA1 | (1 << 2), - ATA_UDMA3 = ATA_UDMA2 | (1 << 3), - ATA_UDMA4 = ATA_UDMA3 | (1 << 4), - ATA_UDMA5 = ATA_UDMA4 | (1 << 5), - ATA_UDMA6 = ATA_UDMA5 | (1 << 6), - ATA_UDMA7 = ATA_UDMA6 | (1 << 7), + ATA_PIO0 = BIT(0), + ATA_PIO1 = ATA_PIO0 | BIT(1), + ATA_PIO2 = ATA_PIO1 | BIT(2), + ATA_PIO3 = ATA_PIO2 | BIT(3), + ATA_PIO4 = ATA_PIO3 | BIT(4), + ATA_PIO5 = ATA_PIO4 | BIT(5), + ATA_PIO6 = ATA_PIO5 | BIT(6), + + ATA_SWDMA0 = BIT(0), + ATA_SWDMA1 = ATA_SWDMA0 | BIT(1), + ATA_SWDMA2 = ATA_SWDMA1 | BIT(2), + + ATA_SWDMA2_ONLY = BIT(2), + + ATA_MWDMA0 = BIT(0), + ATA_MWDMA1 = ATA_MWDMA0 | BIT(1), + ATA_MWDMA2 = ATA_MWDMA1 | BIT(2), + + ATA_MWDMA12_ONLY = BIT(1) | BIT(2), + ATA_MWDMA2_ONLY = BIT(2), + + ATA_UDMA0 = BIT(0), + ATA_UDMA1 = ATA_UDMA0 | BIT(1), + ATA_UDMA2 = ATA_UDMA1 | BIT(2), + ATA_UDMA3 = ATA_UDMA2 | BIT(3), + ATA_UDMA4 = ATA_UDMA3 | BIT(4), + ATA_UDMA5 = ATA_UDMA4 | BIT(5), + ATA_UDMA6 = ATA_UDMA5 | BIT(6), + ATA_UDMA7 = ATA_UDMA6 | BIT(7), /* ATA_UDMA7 is just for completeness... doesn't exist (yet?). */ ATA_UDMA_MASK_40C = ATA_UDMA2, /* udma0-2 */ @@ -87,34 +87,34 @@ enum { /* DMA-related */ ATA_PRD_SZ = 8, ATA_PRD_TBL_SZ = (ATA_MAX_PRD * ATA_PRD_SZ), - ATA_PRD_EOT = (1 << 31), /* end-of-table flag */ + ATA_PRD_EOT = BIT(31), /* end-of-table flag */ ATA_DMA_TABLE_OFS = 4, ATA_DMA_STATUS = 2, ATA_DMA_CMD = 0, - ATA_DMA_WR = (1 << 3), - ATA_DMA_START = (1 << 0), - ATA_DMA_INTR = (1 << 2), - ATA_DMA_ERR = (1 << 1), - ATA_DMA_ACTIVE = (1 << 0), + ATA_DMA_WR = BIT(3), + ATA_DMA_START = BIT(0), + ATA_DMA_INTR = BIT(2), + ATA_DMA_ERR = BIT(1), + ATA_DMA_ACTIVE = BIT(0), /* bits in ATA command block registers */ - ATA_HOB = (1 << 7), /* LBA48 selector */ - ATA_NIEN = (1 << 1), /* disable-irq flag */ - ATA_LBA = (1 << 6), /* LBA28 selector */ - ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ - ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ - ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ - ATA_BUSY = (1 << 7), /* BSY status bit */ - ATA_DRDY = (1 << 6), /* device ready */ - ATA_DF = (1 << 5), /* device fault */ - ATA_DRQ = (1 << 3), /* data request i/o */ - ATA_ERR = (1 << 0), /* have an error */ - ATA_SRST = (1 << 2), /* software reset */ - ATA_ICRC = (1 << 7), /* interface CRC error */ - ATA_UNC = (1 << 6), /* uncorrectable media error */ - ATA_IDNF = (1 << 4), /* ID not found */ - ATA_ABORTED = (1 << 2), /* command aborted */ + ATA_HOB = BIT(7), /* LBA48 selector */ + ATA_NIEN = BIT(1), /* disable-irq flag */ + ATA_LBA = BIT(6), /* LBA28 selector */ + ATA_DEV1 = BIT(4), /* Select Device 1 (slave) */ + ATA_DEVICE_OBS = BIT(7) | BIT(5), /* obs bits in dev reg */ + ATA_DEVCTL_OBS = BIT(3), /* obsolete bit in devctl reg */ + ATA_BUSY = BIT(7), /* BSY status bit */ + ATA_DRDY = BIT(6), /* device ready */ + ATA_DF = BIT(5), /* device fault */ + ATA_DRQ = BIT(3), /* data request i/o */ + ATA_ERR = BIT(0), /* have an error */ + ATA_SRST = BIT(2), /* software reset */ + ATA_ICRC = BIT(7), /* interface CRC error */ + ATA_UNC = BIT(6), /* uncorrectable media error */ + ATA_IDNF = BIT(4), /* ID not found */ + ATA_ABORTED = BIT(2), /* command aborted */ /* ATA command block registers */ ATA_REG_DATA = 0x00, @@ -240,8 +240,8 @@ enum { ATA_DCO_SET = 0xC3, /* ATAPI stuff */ - ATAPI_PKT_DMA = (1 << 0), - ATAPI_DMADIR = (1 << 2), /* ATAPI data dir: + ATAPI_PKT_DMA = BIT(0), + ATAPI_DMADIR = BIT(2), /* ATAPI data dir: 0=to device, 1=to host */ ATAPI_CDB_LEN = 16, @@ -262,10 +262,10 @@ enum { SATA_PMP_PSCR_ERROR = 1, SATA_PMP_PSCR_CONTROL = 2, - SATA_PMP_FEAT_BIST = (1 << 0), - SATA_PMP_FEAT_PMREQ = (1 << 1), - SATA_PMP_FEAT_DYNSSC = (1 << 2), - SATA_PMP_FEAT_NOTIFY = (1 << 3), + SATA_PMP_FEAT_BIST = BIT(0), + SATA_PMP_FEAT_PMREQ = BIT(1), + SATA_PMP_FEAT_DYNSSC = BIT(2), + SATA_PMP_FEAT_NOTIFY = BIT(3), /* cable types */ ATA_CBL_NONE = 0, @@ -284,39 +284,39 @@ enum { SCR_NOTIFICATION = 4, /* SError bits */ - SERR_DATA_RECOVERED = (1 << 0), /* recovered data error */ - SERR_COMM_RECOVERED = (1 << 1), /* recovered comm failure */ - SERR_DATA = (1 << 8), /* unrecovered data error */ - SERR_PERSISTENT = (1 << 9), /* persistent data/comm error */ - SERR_PROTOCOL = (1 << 10), /* protocol violation */ - SERR_INTERNAL = (1 << 11), /* host internal error */ - SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */ - SERR_PHY_INT_ERR = (1 << 17), /* PHY internal error */ - SERR_COMM_WAKE = (1 << 18), /* Comm wake */ - SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */ - SERR_DISPARITY = (1 << 20), /* Disparity */ - SERR_CRC = (1 << 21), /* CRC error */ - SERR_HANDSHAKE = (1 << 22), /* Handshake error */ - SERR_LINK_SEQ_ERR = (1 << 23), /* Link sequence error */ - SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */ - SERR_UNRECOG_FIS = (1 << 25), /* Unrecognized FIS */ - SERR_DEV_XCHG = (1 << 26), /* device exchanged */ + SERR_DATA_RECOVERED = BIT(0), /* recovered data error */ + SERR_COMM_RECOVERED = BIT(1), /* recovered comm failure */ + SERR_DATA = BIT(8), /* unrecovered data error */ + SERR_PERSISTENT = BIT(9), /* persistent data/comm error */ + SERR_PROTOCOL = BIT(10), /* protocol violation */ + SERR_INTERNAL = BIT(11), /* host internal error */ + SERR_PHYRDY_CHG = BIT(16), /* PHY RDY changed */ + SERR_PHY_INT_ERR = BIT(17), /* PHY internal error */ + SERR_COMM_WAKE = BIT(18), /* Comm wake */ + SERR_10B_8B_ERR = BIT(19), /* 10b to 8b decode error */ + SERR_DISPARITY = BIT(20), /* Disparity */ + SERR_CRC = BIT(21), /* CRC error */ + SERR_HANDSHAKE = BIT(22), /* Handshake error */ + SERR_LINK_SEQ_ERR = BIT(23), /* Link sequence error */ + SERR_TRANS_ST_ERROR = BIT(24), /* Transport state trans. error */ + SERR_UNRECOG_FIS = BIT(25), /* Unrecognized FIS */ + SERR_DEV_XCHG = BIT(26), /* device exchanged */ /* struct ata_taskfile flags */ - ATA_TFLAG_LBA48 = (1 << 0), /* enable 48-bit LBA and "HOB" */ - ATA_TFLAG_ISADDR = (1 << 1), /* enable r/w to nsect/lba regs */ - ATA_TFLAG_DEVICE = (1 << 2), /* enable r/w to device reg */ - ATA_TFLAG_WRITE = (1 << 3), /* data dir: host->dev==1 (write) */ - ATA_TFLAG_LBA = (1 << 4), /* enable LBA */ - ATA_TFLAG_FUA = (1 << 5), /* enable FUA */ - ATA_TFLAG_POLLING = (1 << 6), /* set nIEN to 1 and use polling */ + ATA_TFLAG_LBA48 = BIT(0), /* enable 48-bit LBA and "HOB" */ + ATA_TFLAG_ISADDR = BIT(1), /* enable r/w to nsect/lba regs */ + ATA_TFLAG_DEVICE = BIT(2), /* enable r/w to device reg */ + ATA_TFLAG_WRITE = BIT(3), /* data dir: host->dev==1 (write) */ + ATA_TFLAG_LBA = BIT(4), /* enable LBA */ + ATA_TFLAG_FUA = BIT(5), /* enable FUA */ + ATA_TFLAG_POLLING = BIT(6), /* set nIEN to 1 and use polling */ /* protocol flags */ - ATA_PROT_FLAG_PIO = (1 << 0), /* is PIO */ - ATA_PROT_FLAG_DMA = (1 << 1), /* is DMA */ + ATA_PROT_FLAG_PIO = BIT(0), /* is PIO */ + ATA_PROT_FLAG_DMA = BIT(1), /* is DMA */ ATA_PROT_FLAG_DATA = ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA, - ATA_PROT_FLAG_NCQ = (1 << 2), /* is NCQ */ - ATA_PROT_FLAG_ATAPI = (1 << 3), /* is ATAPI */ + ATA_PROT_FLAG_NCQ = BIT(2), /* is NCQ */ + ATA_PROT_FLAG_ATAPI = BIT(3), /* is ATAPI */ }; enum ata_tf_protocols { @@ -423,14 +423,14 @@ static inline int ata_is_data(u8 prot) /* * id tests */ -#define ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0) -#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) -#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) -#define ata_id_has_ncq(id) ((id)[76] & (1 << 8)) +#define ata_id_is_ata(id) (((id)[0] & BIT(15)) == 0) +#define ata_id_has_lba(id) ((id)[49] & BIT(9)) +#define ata_id_has_dma(id) ((id)[49] & BIT(8)) +#define ata_id_has_ncq(id) ((id)[76] & BIT(8)) #define ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1) -#define ata_id_removeable(id) ((id)[0] & (1 << 7)) -#define ata_id_iordy_disable(id) ((id)[49] & (1 << 10)) -#define ata_id_has_iordy(id) ((id)[49] & (1 << 11)) +#define ata_id_removeable(id) ((id)[0] & BIT(7)) +#define ata_id_iordy_disable(id) ((id)[49] & BIT(10)) +#define ata_id_has_iordy(id) ((id)[49] & BIT(11)) #define ata_id_u32(id,n) \ (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) @@ -446,21 +446,21 @@ static inline int ata_id_has_fua(const u16 *id) { if ((id[84] & 0xC000) != 0x4000) return 0; - return id[84] & (1 << 6); + return id[84] & BIT(6); } static inline int ata_id_has_flush(const u16 *id) { if ((id[83] & 0xC000) != 0x4000) return 0; - return id[83] & (1 << 12); + return id[83] & BIT(12); } static inline int ata_id_has_flush_ext(const u16 *id) { if ((id[83] & 0xC000) != 0x4000) return 0; - return id[83] & (1 << 13); + return id[83] & BIT(13); } static inline int ata_id_has_lba48(const u16 *id) @@ -469,7 +469,7 @@ static inline int ata_id_has_lba48(const u16 *id) return 0; if (!ata_id_u64(id, 100)) return 0; - return id[83] & (1 << 10); + return id[83] & BIT(10); } static inline int ata_id_hpa_enabled(const u16 *id) @@ -483,7 +483,7 @@ static inline int ata_id_hpa_enabled(const u16 *id) /* Check command sets enabled as well as supported */ if ((id[85] & ( 1 << 10)) == 0) return 0; - return id[82] & (1 << 10); + return id[82] & BIT(10); } static inline int ata_id_has_wcache(const u16 *id) @@ -491,28 +491,28 @@ static inline int ata_id_has_wcache(const u16 *id) /* Yes children, word 83 valid bits cover word 82 data */ if ((id[83] & 0xC000) != 0x4000) return 0; - return id[82] & (1 << 5); + return id[82] & BIT(5); } static inline int ata_id_has_pm(const u16 *id) { if ((id[83] & 0xC000) != 0x4000) return 0; - return id[82] & (1 << 3); + return id[82] & BIT(3); } static inline int ata_id_rahead_enabled(const u16 *id) { if ((id[87] & 0xC000) != 0x4000) return 0; - return id[85] & (1 << 6); + return id[85] & BIT(6); } static inline int ata_id_wcache_enabled(const u16 *id) { if ((id[87] & 0xC000) != 0x4000) return 0; - return id[85] & (1 << 5); + return id[85] & BIT(5); } static inline unsigned int ata_id_major_version(const u16 *id) @@ -540,7 +540,7 @@ static inline int ata_id_has_tpm(const u16 *id) return 0; if ((id[48] & 0xC000) != 0x4000) return 0; - return id[48] & (1 << 0); + return id[48] & BIT(0); } static inline int ata_id_has_dword_io(const u16 *id) @@ -548,7 +548,7 @@ static inline int ata_id_has_dword_io(const u16 *id) /* ATA 8 reuses this flag for "trusted" computing */ if (ata_id_major_version(id) > 7) return 0; - if (id[48] & (1 << 0)) + if (id[48] & BIT(0)) return 1; return 0; } diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e724310..c098c9a 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -104,6 +104,7 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); } +#define BIT(nr) (1UL << (nr)) #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) diff --git a/include/linux/edd.h b/include/linux/edd.h index 4cbd0fe..a8fd773 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -54,19 +54,19 @@ #ifndef __ASSEMBLY__ -#define EDD_EXT_FIXED_DISK_ACCESS (1 << 0) -#define EDD_EXT_DEVICE_LOCKING_AND_EJECTING (1 << 1) -#define EDD_EXT_ENHANCED_DISK_DRIVE_SUPPORT (1 << 2) -#define EDD_EXT_64BIT_EXTENSIONS (1 << 3) +#define EDD_EXT_FIXED_DISK_ACCESS BIT(0) +#define EDD_EXT_DEVICE_LOCKING_AND_EJECTING BIT(1) +#define EDD_EXT_ENHANCED_DISK_DRIVE_SUPPORT BIT(2) +#define EDD_EXT_64BIT_EXTENSIONS BIT(3) -#define EDD_INFO_DMA_BOUNDARY_ERROR_TRANSPARENT (1 << 0) -#define EDD_INFO_GEOMETRY_VALID (1 << 1) -#define EDD_INFO_REMOVABLE (1 << 2) -#define EDD_INFO_WRITE_VERIFY (1 << 3) -#define EDD_INFO_MEDIA_CHANGE_NOTIFICATION (1 << 4) -#define EDD_INFO_LOCKABLE (1 << 5) -#define EDD_INFO_NO_MEDIA_PRESENT (1 << 6) -#define EDD_INFO_USE_INT13_FN50 (1 << 7) +#define EDD_INFO_DMA_BOUNDARY_ERROR_TRANSPARENT BIT(0) +#define EDD_INFO_GEOMETRY_VALID BIT(1) +#define EDD_INFO_REMOVABLE BIT(2) +#define EDD_INFO_WRITE_VERIFY BIT(3) +#define EDD_INFO_MEDIA_CHANGE_NOTIFICATION BIT(4) +#define EDD_INFO_LOCKABLE BIT(5) +#define EDD_INFO_NO_MEDIA_PRESENT BIT(6) +#define EDD_INFO_USE_INT13_FN50 BIT(7) struct edd_device_params { __u16 length; diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index f6dbdb0..32ba189 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -273,8 +273,8 @@ struct ethtool_sset_info { }; enum ethtool_test_flags { - ETH_TEST_FL_OFFLINE = (1 << 0), /* online / offline */ - ETH_TEST_FL_FAILED = (1 << 1), /* test passed / failed */ + ETH_TEST_FL_OFFLINE = BIT(0), /* online / offline */ + ETH_TEST_FL_FAILED = BIT(1), /* test passed / failed */ }; /* for requesting NIC test and getting results*/ @@ -309,11 +309,11 @@ struct ethtool_perm_addr { * flag differs from the read-only value. */ enum ethtool_flags { - ETH_FLAG_TXVLAN = (1 << 7), /* TX VLAN offload enabled */ - ETH_FLAG_RXVLAN = (1 << 8), /* RX VLAN offload enabled */ - ETH_FLAG_LRO = (1 << 15), /* LRO is enabled */ - ETH_FLAG_NTUPLE = (1 << 27), /* N-tuple filters enabled */ - ETH_FLAG_RXHASH = (1 << 28), + ETH_FLAG_TXVLAN = BIT(7), /* TX VLAN offload enabled */ + ETH_FLAG_RXVLAN = BIT(8), /* RX VLAN offload enabled */ + ETH_FLAG_LRO = BIT(15), /* LRO is enabled */ + ETH_FLAG_NTUPLE = BIT(27), /* N-tuple filters enabled */ + ETH_FLAG_RXHASH = BIT(28), }; /* The following structures are for supporting RX network flow @@ -559,54 +559,54 @@ enum ethtool_sfeatures_retval_bits { #define SPARC_ETH_SSET ETHTOOL_SSET /* Indicates what features are supported by the interface. */ -#define SUPPORTED_10baseT_Half (1 << 0) -#define SUPPORTED_10baseT_Full (1 << 1) -#define SUPPORTED_100baseT_Half (1 << 2) -#define SUPPORTED_100baseT_Full (1 << 3) -#define SUPPORTED_1000baseT_Half (1 << 4) -#define SUPPORTED_1000baseT_Full (1 << 5) -#define SUPPORTED_Autoneg (1 << 6) -#define SUPPORTED_TP (1 << 7) -#define SUPPORTED_AUI (1 << 8) -#define SUPPORTED_MII (1 << 9) -#define SUPPORTED_FIBRE (1 << 10) -#define SUPPORTED_BNC (1 << 11) -#define SUPPORTED_10000baseT_Full (1 << 12) -#define SUPPORTED_Pause (1 << 13) -#define SUPPORTED_Asym_Pause (1 << 14) -#define SUPPORTED_2500baseX_Full (1 << 15) -#define SUPPORTED_Backplane (1 << 16) -#define SUPPORTED_1000baseKX_Full (1 << 17) -#define SUPPORTED_10000baseKX4_Full (1 << 18) -#define SUPPORTED_10000baseKR_Full (1 << 19) -#define SUPPORTED_10000baseR_FEC (1 << 20) -#define SUPPORTED_1000baseX_Half (1 << 21) -#define SUPPORTED_1000baseX_Full (1 << 22) +#define SUPPORTED_10baseT_Half BIT(0) +#define SUPPORTED_10baseT_Full BIT(1) +#define SUPPORTED_100baseT_Half BIT(2) +#define SUPPORTED_100baseT_Full BIT(3) +#define SUPPORTED_1000baseT_Half BIT(4) +#define SUPPORTED_1000baseT_Full BIT(5) +#define SUPPORTED_Autoneg BIT(6) +#define SUPPORTED_TP BIT(7) +#define SUPPORTED_AUI BIT(8) +#define SUPPORTED_MII BIT(9) +#define SUPPORTED_FIBRE BIT(10) +#define SUPPORTED_BNC BIT(11) +#define SUPPORTED_10000baseT_Full BIT(12) +#define SUPPORTED_Pause BIT(13) +#define SUPPORTED_Asym_Pause BIT(14) +#define SUPPORTED_2500baseX_Full BIT(15) +#define SUPPORTED_Backplane BIT(16) +#define SUPPORTED_1000baseKX_Full BIT(17) +#define SUPPORTED_10000baseKX4_Full BIT(18) +#define SUPPORTED_10000baseKR_Full BIT(19) +#define SUPPORTED_10000baseR_FEC BIT(20) +#define SUPPORTED_1000baseX_Half BIT(21) +#define SUPPORTED_1000baseX_Full BIT(22) /* Indicates what features are advertised by the interface. */ -#define ADVERTISED_10baseT_Half (1 << 0) -#define ADVERTISED_10baseT_Full (1 << 1) -#define ADVERTISED_100baseT_Half (1 << 2) -#define ADVERTISED_100baseT_Full (1 << 3) -#define ADVERTISED_1000baseT_Half (1 << 4) -#define ADVERTISED_1000baseT_Full (1 << 5) -#define ADVERTISED_Autoneg (1 << 6) -#define ADVERTISED_TP (1 << 7) -#define ADVERTISED_AUI (1 << 8) -#define ADVERTISED_MII (1 << 9) -#define ADVERTISED_FIBRE (1 << 10) -#define ADVERTISED_BNC (1 << 11) -#define ADVERTISED_10000baseT_Full (1 << 12) -#define ADVERTISED_Pause (1 << 13) -#define ADVERTISED_Asym_Pause (1 << 14) -#define ADVERTISED_2500baseX_Full (1 << 15) -#define ADVERTISED_Backplane (1 << 16) -#define ADVERTISED_1000baseKX_Full (1 << 17) -#define ADVERTISED_10000baseKX4_Full (1 << 18) -#define ADVERTISED_10000baseKR_Full (1 << 19) -#define ADVERTISED_10000baseR_FEC (1 << 20) -#define ADVERTISED_1000baseX_Half (1 << 21) -#define ADVERTISED_1000baseX_Full (1 << 22) +#define ADVERTISED_10baseT_Half BIT(0) +#define ADVERTISED_10baseT_Full BIT(1) +#define ADVERTISED_100baseT_Half BIT(2) +#define ADVERTISED_100baseT_Full BIT(3) +#define ADVERTISED_1000baseT_Half BIT(4) +#define ADVERTISED_1000baseT_Full BIT(5) +#define ADVERTISED_Autoneg BIT(6) +#define ADVERTISED_TP BIT(7) +#define ADVERTISED_AUI BIT(8) +#define ADVERTISED_MII BIT(9) +#define ADVERTISED_FIBRE BIT(10) +#define ADVERTISED_BNC BIT(11) +#define ADVERTISED_10000baseT_Full BIT(12) +#define ADVERTISED_Pause BIT(13) +#define ADVERTISED_Asym_Pause BIT(14) +#define ADVERTISED_2500baseX_Full BIT(15) +#define ADVERTISED_Backplane BIT(16) +#define ADVERTISED_1000baseKX_Full BIT(17) +#define ADVERTISED_10000baseKX4_Full BIT(18) +#define ADVERTISED_10000baseKR_Full BIT(19) +#define ADVERTISED_10000baseR_FEC BIT(20) +#define ADVERTISED_1000baseX_Half BIT(21) +#define ADVERTISED_1000baseX_Full BIT(22) /* The following are all involved in forcing a particular link * mode for the device for setting things. When getting the @@ -654,13 +654,13 @@ enum ethtool_sfeatures_retval_bits { #define ETH_TP_MDI_X 0x02 /* Wake-On-Lan options. */ -#define WAKE_PHY (1 << 0) -#define WAKE_UCAST (1 << 1) -#define WAKE_MCAST (1 << 2) -#define WAKE_BCAST (1 << 3) -#define WAKE_ARP (1 << 4) -#define WAKE_MAGIC (1 << 5) -#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ +#define WAKE_PHY BIT(0) +#define WAKE_UCAST BIT(1) +#define WAKE_MCAST BIT(2) +#define WAKE_BCAST BIT(3) +#define WAKE_ARP BIT(4) +#define WAKE_MAGIC BIT(5) +#define WAKE_MAGICSECURE BIT(6) /* only meaningful if WAKE_MAGIC */ /* L2-L4 network traffic flow types */ #define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */ @@ -681,14 +681,14 @@ enum ethtool_sfeatures_retval_bits { #define ETHER_FLOW 0x12 /* spec only (ether_spec) */ /* L3-L4 network traffic flow hash options */ -#define RXH_L2DA (1 << 1) -#define RXH_VLAN (1 << 2) -#define RXH_L3_PROTO (1 << 3) -#define RXH_IP_SRC (1 << 4) -#define RXH_IP_DST (1 << 5) -#define RXH_L4_B_0_1 (1 << 6) /* src port in case of TCP/UDP/SCTP */ -#define RXH_L4_B_2_3 (1 << 7) /* dst port in case of TCP/UDP/SCTP */ -#define RXH_DISCARD (1 << 31) +#define RXH_L2DA BIT(1) +#define RXH_VLAN BIT(2) +#define RXH_L3_PROTO BIT(3) +#define RXH_IP_SRC BIT(4) +#define RXH_IP_DST BIT(5) +#define RXH_L4_B_0_1 BIT(6) /* src port in case of TCP/UDP/SCTP */ +#define RXH_L4_B_2_3 BIT(7) /* dst port in case of TCP/UDP/SCTP */ +#define RXH_DISCARD BIT(31) #define RX_CLS_FLOW_DISC 0xffffffffffffffffULL diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h index f0f7727..e96d9fb 100644 --- a/include/linux/mtd/fsmc_nand.h +++ b/include/linux/mtd/fsmc_nand.h @@ -33,29 +33,29 @@ struct fsmc_regs { }; /* ctrl register definitions */ -#define FSMC_WP (1 << 7) +#define FSMC_WP BIT(7) /* pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_RESET BIT(0) +#define FSMC_WAITON BIT(1) +#define FSMC_ENABLE BIT(2) +#define FSMC_DEVTYPE_NAND BIT(3) #define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) +#define FSMC_DEVWID_16 BIT(4) +#define FSMC_ECCEN BIT(6) #define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) +#define FSMC_ECCPLEN_256 BIT(7) +#define FSMC_TCLR_1 BIT(9) +#define FSMC_TAR_1 BIT(13) /* sts register definitions */ -#define FSMC_CODE_RDY (1 << 15) +#define FSMC_CODE_RDY BIT(15) /* comm register definitions */ #define FSMC_TSET_0 (0 << 0) #define FSMC_TWAIT_6 (6 << 8) #define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) +#define FSMC_THIZ_1 BIT(24) /* peripid2 register definitions */ #define FSMC_REVISION_MSK (0xf) diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index bc927ec..b22cee6 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -238,17 +238,17 @@ typedef enum { struct nand_chip; /* ONFI features */ -#define ONFI_FEATURE_16_BIT_BUS (1 << 0) -#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) +#define ONFI_FEATURE_16_BIT_BUS BIT(0) +#define ONFI_FEATURE_EXT_PARAM_PAGE BIT(7) /* ONFI timing mode, used in both asynchronous and synchronous mode */ -#define ONFI_TIMING_MODE_0 (1 << 0) -#define ONFI_TIMING_MODE_1 (1 << 1) -#define ONFI_TIMING_MODE_2 (1 << 2) -#define ONFI_TIMING_MODE_3 (1 << 3) -#define ONFI_TIMING_MODE_4 (1 << 4) -#define ONFI_TIMING_MODE_5 (1 << 5) -#define ONFI_TIMING_MODE_UNKNOWN (1 << 6) +#define ONFI_TIMING_MODE_0 BIT(0) +#define ONFI_TIMING_MODE_1 BIT(1) +#define ONFI_TIMING_MODE_2 BIT(2) +#define ONFI_TIMING_MODE_3 BIT(3) +#define ONFI_TIMING_MODE_4 BIT(4) +#define ONFI_TIMING_MODE_5 BIT(5) +#define ONFI_TIMING_MODE_UNKNOWN BIT(6) /* ONFI feature address */ #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 @@ -260,7 +260,7 @@ struct nand_chip; #define ONFI_SUBFEATURE_PARAM_LEN 4 /* ONFI optional commands SET/GET FEATURES supported? */ -#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) +#define ONFI_OPT_CMD_SET_GET_FEATURES BIT(2) struct nand_onfi_params { /* rev info and features block */ @@ -393,7 +393,7 @@ struct jedec_ecc_info { } __packed; /* JEDEC features */ -#define JEDEC_FEATURE_16_BIT_BUS (1 << 0) +#define JEDEC_FEATURE_16_BIT_BUS BIT(0) struct nand_jedec_params { /* rev info and features block */ diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index 8449a3c..86a394c 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -67,13 +67,13 @@ /* * Device ID Register F001h (R) */ -#define DEVICE_IS_FLEXONENAND (1 << 9) +#define DEVICE_IS_FLEXONENAND BIT(9) #define FLEXONENAND_PI_MASK (0x3ff) #define FLEXONENAND_PI_UNLOCK_SHIFT (14) #define ONENAND_DEVICE_DENSITY_MASK (0xf) #define ONENAND_DEVICE_DENSITY_SHIFT (4) -#define ONENAND_DEVICE_IS_DDP (1 << 3) -#define ONENAND_DEVICE_IS_DEMUX (1 << 2) +#define ONENAND_DEVICE_IS_DDP BIT(3) +#define ONENAND_DEVICE_IS_DEMUX BIT(2) #define ONENAND_DEVICE_VCC_MASK (0x3) #define ONENAND_DEVICE_DENSITY_512Mb (0x002) @@ -89,7 +89,7 @@ /* * Technology Register F006h (R) */ -#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0) +#define ONENAND_TECHNOLOGY_IS_MLC BIT(0) /* * Start Address 1 F100h (R/W) @@ -145,62 +145,62 @@ /* * System Configuration 1 Register F221h (R, R/W) */ -#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) +#define ONENAND_SYS_CFG1_SYNC_READ BIT(15) #define ONENAND_SYS_CFG1_BRL_7 (7 << 12) #define ONENAND_SYS_CFG1_BRL_6 (6 << 12) #define ONENAND_SYS_CFG1_BRL_5 (5 << 12) #define ONENAND_SYS_CFG1_BRL_4 (4 << 12) #define ONENAND_SYS_CFG1_BRL_3 (3 << 12) #define ONENAND_SYS_CFG1_BRL_10 (2 << 12) -#define ONENAND_SYS_CFG1_BRL_9 (1 << 12) +#define ONENAND_SYS_CFG1_BRL_9 BIT(12) #define ONENAND_SYS_CFG1_BRL_8 (0 << 12) #define ONENAND_SYS_CFG1_BRL_SHIFT (12) #define ONENAND_SYS_CFG1_BL_32 (4 << 9) #define ONENAND_SYS_CFG1_BL_16 (3 << 9) #define ONENAND_SYS_CFG1_BL_8 (2 << 9) -#define ONENAND_SYS_CFG1_BL_4 (1 << 9) +#define ONENAND_SYS_CFG1_BL_4 BIT(9) #define ONENAND_SYS_CFG1_BL_CONT (0 << 9) #define ONENAND_SYS_CFG1_BL_SHIFT (9) -#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) -#define ONENAND_SYS_CFG1_RDY (1 << 7) -#define ONENAND_SYS_CFG1_INT (1 << 6) -#define ONENAND_SYS_CFG1_IOBE (1 << 5) -#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) +#define ONENAND_SYS_CFG1_NO_ECC BIT(8) +#define ONENAND_SYS_CFG1_RDY BIT(7) +#define ONENAND_SYS_CFG1_INT BIT(6) +#define ONENAND_SYS_CFG1_IOBE BIT(5) +#define ONENAND_SYS_CFG1_RDY_CONF BIT(4) /* * Controller Status Register F240h (R) */ -#define ONENAND_CTRL_ONGO (1 << 15) -#define ONENAND_CTRL_LOCK (1 << 14) -#define ONENAND_CTRL_LOAD (1 << 13) -#define ONENAND_CTRL_PROGRAM (1 << 12) -#define ONENAND_CTRL_ERASE (1 << 11) -#define ONENAND_CTRL_ERROR (1 << 10) -#define ONENAND_CTRL_RSTB (1 << 7) +#define ONENAND_CTRL_ONGO BIT(15) +#define ONENAND_CTRL_LOCK BIT(14) +#define ONENAND_CTRL_LOAD BIT(13) +#define ONENAND_CTRL_PROGRAM BIT(12) +#define ONENAND_CTRL_ERASE BIT(11) +#define ONENAND_CTRL_ERROR BIT(10) +#define ONENAND_CTRL_RSTB BIT(7) /* * Interrupt Status Register F241h (R) */ -#define ONENAND_INT_MASTER (1 << 15) -#define ONENAND_INT_READ (1 << 7) -#define ONENAND_INT_WRITE (1 << 6) -#define ONENAND_INT_ERASE (1 << 5) -#define ONENAND_INT_RESET (1 << 4) +#define ONENAND_INT_MASTER BIT(15) +#define ONENAND_INT_READ BIT(7) +#define ONENAND_INT_WRITE BIT(6) +#define ONENAND_INT_ERASE BIT(5) +#define ONENAND_INT_RESET BIT(4) #define ONENAND_INT_CLEAR (0 << 0) /* * NAND Flash Write Protection Status Register F24Eh (R) */ -#define ONENAND_WP_US (1 << 2) -#define ONENAND_WP_LS (1 << 1) -#define ONENAND_WP_LTS (1 << 0) +#define ONENAND_WP_US BIT(2) +#define ONENAND_WP_LS BIT(1) +#define ONENAND_WP_LTS BIT(0) /* * ECC Status Reigser FF00h (R) */ -#define ONENAND_ECC_1BIT (1 << 0) +#define ONENAND_ECC_1BIT BIT(0) #define ONENAND_ECC_1BIT_ALL (0x5555) -#define ONENAND_ECC_2BIT (1 << 1) +#define ONENAND_ECC_2BIT BIT(1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) #define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010) #define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010) diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h index 246bcf8..e613890 100644 --- a/include/linux/mtd/samsung_onenand.h +++ b/include/linux/mtd/samsung_onenand.h @@ -92,22 +92,22 @@ struct samsung_onenand { #define ONENAND_MEM_RESET_WARM 0x1 #define INT_ERR_ALL 0x3fff -#define CACHE_OP_ERR (1 << 13) -#define RST_CMP (1 << 12) -#define RDY_ACT (1 << 11) -#define INT_ACT (1 << 10) -#define UNSUP_CMD (1 << 9) -#define LOCKED_BLK (1 << 8) -#define BLK_RW_CMP (1 << 7) -#define ERS_CMP (1 << 6) -#define PGM_CMP (1 << 5) -#define LOAD_CMP (1 << 4) -#define ERS_FAIL (1 << 3) -#define PGM_FAIL (1 << 2) -#define INT_TO (1 << 1) -#define LD_FAIL_ECC_ERR (1 << 0) +#define CACHE_OP_ERR BIT(13) +#define RST_CMP BIT(12) +#define RDY_ACT BIT(11) +#define INT_ACT BIT(10) +#define UNSUP_CMD BIT(9) +#define LOCKED_BLK BIT(8) +#define BLK_RW_CMP BIT(7) +#define ERS_CMP BIT(6) +#define PGM_CMP BIT(5) +#define LOAD_CMP BIT(4) +#define ERS_FAIL BIT(3) +#define PGM_FAIL BIT(2) +#define INT_TO BIT(1) +#define LD_FAIL_ECC_ERR BIT(0) -#define TSRF (1 << 0) +#define TSRF BIT(0) /* common initialize function */ extern void s3c_onenand_init(struct mtd_info *); diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h index 899fbb4..ee21256 100644 --- a/include/linux/screen_info.h +++ b/include/linux/screen_info.h @@ -66,7 +66,7 @@ struct screen_info { #define VIDEO_TYPE_EFI 0x70 /* EFI graphic mode */ -#define VIDEO_FLAGS_NOCURSOR (1 << 0) /* The video mode has no cursor set */ +#define VIDEO_FLAGS_NOCURSOR BIT(0) /* The video mode has no cursor set */ #ifdef __KERNEL__ extern struct screen_info screen_info; diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 9214b67..3daa7c6 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -300,29 +300,29 @@ #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ -#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ -#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ -#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ -#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ +#define UART_RSA_MSR_SWAP BIT(0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO BIT(2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW BIT(3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP BIT(4) /* Level (1) / Edge triger (0) */ #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ -#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ -#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ -#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ -#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ -#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ +#define UART_RSA_IER_Rx_FIFO_H BIT(0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H BIT(1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E BIT(2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT BIT(3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER BIT(4) /* Enable timer interrupt */ #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ -#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ -#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ -#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ -#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ -#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ -#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ -#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ -#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ +#define UART_RSA_SRR_Tx_FIFO_NEMP BIT(0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL BIT(1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL BIT(2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP BIT(3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL BIT(4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL BIT(5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT BIT(6) /* Character reception timeout occurred (1) */ +#define UART_RSA_SRR_TIMER BIT(7) /* Timer interrupt occurred */ #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ @@ -330,7 +330,7 @@ #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ -#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ +#define UART_RSA_TCR_SWITCH BIT(0) /* Timer on */ /* * The RSA DSV/II board has two fixed clock frequencies. One is the diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h index c1d039c..a630e06 100644 --- a/include/linux/usb/cdc.h +++ b/include/linux/usb/cdc.h @@ -194,11 +194,11 @@ struct usb_cdc_line_coding { } __attribute__ ((packed)); /* table 62; bits in multicast filter */ -#define USB_CDC_PACKET_TYPE_PROMISCUOUS (1 << 0) -#define USB_CDC_PACKET_TYPE_ALL_MULTICAST (1 << 1) /* no filter */ -#define USB_CDC_PACKET_TYPE_DIRECTED (1 << 2) -#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3) -#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */ +#define USB_CDC_PACKET_TYPE_PROMISCUOUS BIT(0) +#define USB_CDC_PACKET_TYPE_ALL_MULTICAST BIT(1) /* no filter */ +#define USB_CDC_PACKET_TYPE_DIRECTED BIT(2) +#define USB_CDC_PACKET_TYPE_BROADCAST BIT(3) +#define USB_CDC_PACKET_TYPE_MULTICAST BIT(4) /* filtered */ /*-------------------------------------------------------------------------*/ diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 822fca0..5c78c72 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -321,10 +321,10 @@ struct usb_config_descriptor { #define USB_DT_CONFIG_SIZE 9 /* from config descriptor bmAttributes */ -#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ -#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ -#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ -#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ +#define USB_CONFIG_ATT_ONE BIT(7) /* must be set */ +#define USB_CONFIG_ATT_SELFPOWER BIT(6) /* self powered */ +#define USB_CONFIG_ATT_WAKEUP BIT(5) /* can wakeup */ +#define USB_CONFIG_ATT_BATTERY BIT(4) /* battery powered */ /*-------------------------------------------------------------------------*/ @@ -401,11 +401,11 @@ struct usb_generic_descriptor { /* The USB 3.0 spec redefines bits 5:4 of bmAttributes as interrupt ep type. */ #define USB_ENDPOINT_INTRTYPE 0x30 #define USB_ENDPOINT_INTR_PERIODIC (0 << 4) -#define USB_ENDPOINT_INTR_NOTIFICATION (1 << 4) +#define USB_ENDPOINT_INTR_NOTIFICATION BIT(4) #define USB_ENDPOINT_SYNCTYPE 0x0c #define USB_ENDPOINT_SYNC_NONE (0 << 2) -#define USB_ENDPOINT_SYNC_ASYNC (1 << 2) +#define USB_ENDPOINT_SYNC_ASYNC BIT(2) #define USB_ENDPOINT_SYNC_ADAPTIVE (2 << 2) #define USB_ENDPOINT_SYNC_SYNC (3 << 2) @@ -675,8 +675,8 @@ struct usb_otg_descriptor { } __attribute__ ((packed)); /* from usb_otg_descriptor.bmAttributes */ -#define USB_OTG_SRP (1 << 0) -#define USB_OTG_HNP (1 << 1) /* swap host/device roles */ +#define USB_OTG_SRP BIT(0) +#define USB_OTG_HNP BIT(1) /* swap host/device roles */ /*-------------------------------------------------------------------------*/ @@ -779,20 +779,20 @@ struct usb_wireless_cap_descriptor { /* Ultra Wide Band */ __u8 bDevCapabilityType; __u8 bmAttributes; -#define USB_WIRELESS_P2P_DRD (1 << 1) +#define USB_WIRELESS_P2P_DRD BIT(1) #define USB_WIRELESS_BEACON_MASK (3 << 2) -#define USB_WIRELESS_BEACON_SELF (1 << 2) +#define USB_WIRELESS_BEACON_SELF BIT(2) #define USB_WIRELESS_BEACON_DIRECTED (2 << 2) #define USB_WIRELESS_BEACON_NONE (3 << 2) __le16 wPHYRates; /* bit rates, Mbps */ -#define USB_WIRELESS_PHY_53 (1 << 0) /* always set */ -#define USB_WIRELESS_PHY_80 (1 << 1) -#define USB_WIRELESS_PHY_107 (1 << 2) /* always set */ -#define USB_WIRELESS_PHY_160 (1 << 3) -#define USB_WIRELESS_PHY_200 (1 << 4) /* always set */ -#define USB_WIRELESS_PHY_320 (1 << 5) -#define USB_WIRELESS_PHY_400 (1 << 6) -#define USB_WIRELESS_PHY_480 (1 << 7) +#define USB_WIRELESS_PHY_53 BIT(0) /* always set */ +#define USB_WIRELESS_PHY_80 BIT(1) +#define USB_WIRELESS_PHY_107 BIT(2) /* always set */ +#define USB_WIRELESS_PHY_160 BIT(3) +#define USB_WIRELESS_PHY_200 BIT(4) /* always set */ +#define USB_WIRELESS_PHY_320 BIT(5) +#define USB_WIRELESS_PHY_400 BIT(6) +#define USB_WIRELESS_PHY_480 BIT(7) __u8 bmTFITXPowerInfo; /* TFI power levels */ __u8 bmFFITXPowerInfo; /* FFI power levels */ __le16 bmBandGroup; @@ -807,10 +807,10 @@ struct usb_ext_cap_descriptor { /* Link Power Management */ __u8 bDescriptorType; __u8 bDevCapabilityType; __le32 bmAttributes; -#define USB_LPM_SUPPORT (1 << 1) /* supports LPM */ -#define USB_BESL_SUPPORT (1 << 2) /* supports BESL */ -#define USB_BESL_BASELINE_VALID (1 << 3) /* Baseline BESL valid*/ -#define USB_BESL_DEEP_VALID (1 << 4) /* Deep BESL valid */ +#define USB_LPM_SUPPORT BIT(1) /* supports LPM */ +#define USB_BESL_SUPPORT BIT(2) /* supports BESL */ +#define USB_BESL_BASELINE_VALID BIT(3) /* Baseline BESL valid*/ +#define USB_BESL_DEEP_VALID BIT(4) /* Deep BESL valid */ #define USB_GET_BESL_BASELINE(p) (((p) & (0xf << 8)) >> 8) #define USB_GET_BESL_DEEP(p) (((p) & (0xf << 12)) >> 12) } __attribute__((packed)); @@ -827,12 +827,12 @@ struct usb_ss_cap_descriptor { /* Link Power Management */ __u8 bDescriptorType; __u8 bDevCapabilityType; __u8 bmAttributes; -#define USB_LTM_SUPPORT (1 << 1) /* supports LTM */ +#define USB_LTM_SUPPORT BIT(1) /* supports LTM */ __le16 wSpeedSupported; #define USB_LOW_SPEED_OPERATION (1) /* Low speed operation */ -#define USB_FULL_SPEED_OPERATION (1 << 1) /* Full speed operation */ -#define USB_HIGH_SPEED_OPERATION (1 << 2) /* High speed operation */ -#define USB_5GBPS_OPERATION (1 << 3) /* Operation at 5Gbps */ +#define USB_FULL_SPEED_OPERATION BIT(1) /* Full speed operation */ +#define USB_HIGH_SPEED_OPERATION BIT(2) /* High speed operation */ +#define USB_5GBPS_OPERATION BIT(3) /* Operation at 5Gbps */ __u8 bFunctionalitySupport; __u8 bU1devExitLat; __le16 bU2DevExitLat; diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 7edc760..1fb532d 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -151,7 +151,7 @@ struct dwc3 { /* offset: 0xC100 */ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) -#define DWC3_GCTL_U2RSTECN (1 << 16) +#define DWC3_GCTL_U2RSTECN BIT(16) #define DWC3_GCTL_RAMCLKSEL(x) \ (((x) & DWC3_GCTL_CLK_MASK) << 6) #define DWC3_GCTL_CLK_BUS (0) @@ -163,11 +163,11 @@ struct dwc3 { /* offset: 0xC100 */ #define DWC3_GCTL_PRTCAP_HOST 1 #define DWC3_GCTL_PRTCAP_DEVICE 2 #define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_CORESOFTRESET (1 << 11) +#define DWC3_GCTL_CORESOFTRESET BIT(11) #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +#define DWC3_GCTL_DISSCRAMBLE BIT(3) +#define DWC3_GCTL_DSBLCLKGTNG BIT(0) /* Global HWPARAMS1 Register */ #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) @@ -175,20 +175,20 @@ struct dwc3 { /* offset: 0xC100 */ #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 /* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) -#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) +#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) /* Global USB3 PIPE Control Register */ -#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) -#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) +#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) /* Global TX Fifo Size Register */ #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) /* Device Control Register */ -#define DWC3_DCTL_RUN_STOP (1 << 31) -#define DWC3_DCTL_CSFTRST (1 << 30) -#define DWC3_DCTL_LSFTRST (1 << 29) +#define DWC3_DCTL_RUN_STOP BIT(31) +#define DWC3_DCTL_CSFTRST BIT(30) +#define DWC3_DCTL_LSFTRST BIT(29) #endif /* __DWC3_H_ */ diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h index cb166e6..f67c686 100644 --- a/include/linux/usb/xhci-omap.h +++ b/include/linux/usb/xhci-omap.h @@ -47,37 +47,37 @@ #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC -#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) -#define USB3_PHY_RX_POWERON (1 << 14) -#define USB3_PHY_TX_POWERON (1 << 15) +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) #define USB3_PWRCTL_CLK_CMD_SHIFT 14 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 /* USBOTGSS_WRAPPER definitions */ -#define USBOTGSS_WRAPRESET (1 << 17) -#define USBOTGSS_DMADISABLE (1 << 16) -#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) -#define USBOTGSS_STANDBYMODE_SMRT (1 << 5) +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) -#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) -#define USBOTGSS_IDLEMODE_SMRT (1 << 3) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) /* USBOTGSS_IRQENABLE_SET_0 bit */ -#define USBOTGSS_COREIRQ_EN (1 << 0) +#define USBOTGSS_COREIRQ_EN BIT(0) /* USBOTGSS_IRQENABLE_SET_1 bits */ -#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) -#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) -#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) -#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) -#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) -#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) -#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(0) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) /* * USBOTGSS_WRAPPER registers diff --git a/include/mc13783.h b/include/mc13783.h index 3b20591..aad149d 100644 --- a/include/mc13783.h +++ b/include/mc13783.h @@ -10,55 +10,55 @@ #define __MC13783_H__ /* REG_MODE_0 */ -#define VAUDIOEN (1 << 0) -#define VAUDIOSTBY (1 << 1) -#define VAUDIOMODE (1 << 2) -#define VIOHIEN (1 << 3) -#define VIOHISTBY (1 << 4) -#define VIOHIMODE (1 << 5) -#define VIOLOEN (1 << 6) -#define VIOLOSTBY (1 << 7) -#define VIOLOMODE (1 << 8) -#define VDIGEN (1 << 9) -#define VDIGSTBY (1 << 10) -#define VDIGMODE (1 << 11) -#define VGENEN (1 << 12) -#define VGENSTBY (1 << 13) -#define VGENMODE (1 << 14) -#define VRFDIGEN (1 << 15) -#define VRFDIGSTBY (1 << 16) -#define VRFDIGMODE (1 << 17) -#define VRFREFEN (1 << 18) -#define VRFREFSTBY (1 << 19) -#define VRFREFMODE (1 << 20) -#define VRFCPEN (1 << 21) -#define VRFCPSTBY (1 << 22) -#define VRFCPMODE (1 << 23) +#define VAUDIOEN BIT(0) +#define VAUDIOSTBY BIT(1) +#define VAUDIOMODE BIT(2) +#define VIOHIEN BIT(3) +#define VIOHISTBY BIT(4) +#define VIOHIMODE BIT(5) +#define VIOLOEN BIT(6) +#define VIOLOSTBY BIT(7) +#define VIOLOMODE BIT(8) +#define VDIGEN BIT(9) +#define VDIGSTBY BIT(10) +#define VDIGMODE BIT(11) +#define VGENEN BIT(12) +#define VGENSTBY BIT(13) +#define VGENMODE BIT(14) +#define VRFDIGEN BIT(15) +#define VRFDIGSTBY BIT(16) +#define VRFDIGMODE BIT(17) +#define VRFREFEN BIT(18) +#define VRFREFSTBY BIT(19) +#define VRFREFMODE BIT(20) +#define VRFCPEN BIT(21) +#define VRFCPSTBY BIT(22) +#define VRFCPMODE BIT(23) /* REG_MODE_1 */ -#define VSIMEN (1 << 0) -#define VSIMSTBY (1 << 1) -#define VSIMMODE (1 << 2) -#define VESIMEN (1 << 3) -#define VESIMSTBY (1 << 4) -#define VESIMMODE (1 << 5) -#define VCAMEN (1 << 6) -#define VCAMSTBY (1 << 7) -#define VCAMMODE (1 << 8) -#define VRFBGEN (1 << 9) -#define VRFBGSTBY (1 << 10) -#define VVIBEN (1 << 11) -#define VRF1EN (1 << 12) -#define VRF1STBY (1 << 13) -#define VRF1MODE (1 << 14) -#define VRF2EN (1 << 15) -#define VRF2STBY (1 << 16) -#define VRF2MODE (1 << 17) -#define VMMC1EN (1 << 18) -#define VMMC1STBY (1 << 19) -#define VMMC1MODE (1 << 20) -#define VMMC2EN (1 << 21) -#define VMMC2STBY (1 << 22) -#define VMMC2MODE (1 << 23) +#define VSIMEN BIT(0) +#define VSIMSTBY BIT(1) +#define VSIMMODE BIT(2) +#define VESIMEN BIT(3) +#define VESIMSTBY BIT(4) +#define VESIMMODE BIT(5) +#define VCAMEN BIT(6) +#define VCAMSTBY BIT(7) +#define VCAMMODE BIT(8) +#define VRFBGEN BIT(9) +#define VRFBGSTBY BIT(10) +#define VVIBEN BIT(11) +#define VRF1EN BIT(12) +#define VRF1STBY BIT(13) +#define VRF1MODE BIT(14) +#define VRF2EN BIT(15) +#define VRF2STBY BIT(16) +#define VRF2MODE BIT(17) +#define VMMC1EN BIT(18) +#define VMMC1STBY BIT(19) +#define VMMC1MODE BIT(20) +#define VMMC2EN BIT(21) +#define VMMC2STBY BIT(22) +#define VMMC2MODE BIT(23) #endif diff --git a/include/mc13892.h b/include/mc13892.h index 218f36f..6574c54 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -13,28 +13,28 @@ /* REG_CHARGE */ -#define VCHRG0 (1 << 0) -#define VCHRG1 (1 << 1) -#define VCHRG2 (1 << 2) -#define ICHRG0 (1 << 3) -#define ICHRG1 (1 << 4) -#define ICHRG2 (1 << 5) -#define ICHRG3 (1 << 6) -#define TREN (1 << 7) -#define ACKLPB (1 << 8) -#define THCHKB (1 << 9) -#define FETOVRD (1 << 10) -#define FETCTRL (1 << 11) -#define RVRSMODE (1 << 13) -#define PLIM0 (1 << 15) -#define PLIM1 (1 << 16) -#define PLIMDIS (1 << 17) -#define CHRGLEDEN (1 << 18) -#define CHGTMRRST (1 << 19) -#define CHGRESTART (1 << 20) -#define CHGAUTOB (1 << 21) -#define CYCLB (1 << 22) -#define CHGAUTOVIB (1 << 23) +#define VCHRG0 BIT(0) +#define VCHRG1 BIT(1) +#define VCHRG2 BIT(2) +#define ICHRG0 BIT(3) +#define ICHRG1 BIT(4) +#define ICHRG2 BIT(5) +#define ICHRG3 BIT(6) +#define TREN BIT(7) +#define ACKLPB BIT(8) +#define THCHKB BIT(9) +#define FETOVRD BIT(10) +#define FETCTRL BIT(11) +#define RVRSMODE BIT(13) +#define PLIM0 BIT(15) +#define PLIM1 BIT(16) +#define PLIMDIS BIT(17) +#define CHRGLEDEN BIT(18) +#define CHGTMRRST BIT(19) +#define CHGRESTART BIT(20) +#define CHGAUTOB BIT(21) +#define CYCLB BIT(22) +#define CHGAUTOVIB BIT(23) /* REG_SETTING_0/1 */ #define VO_1_20V 0 @@ -75,17 +75,17 @@ /* Fields in REG_SETTING_1 */ #define VVIDEO_2_7 (0 << 2) -#define VVIDEO_2_775 (1 << 2) +#define VVIDEO_2_775 BIT(2) #define VVIDEO_2_5 (2 << 2) #define VVIDEO_2_6 (3 << 2) #define VVIDEO_MASK (3 << 2) #define VAUDIO_2_3 (0 << 4) -#define VAUDIO_2_5 (1 << 4) +#define VAUDIO_2_5 BIT(4) #define VAUDIO_2_775 (2 << 4) #define VAUDIO_3_0 (3 << 4) #define VAUDIO_MASK (3 << 4) #define VSD_1_8 (0 << 6) -#define VSD_2_0 (1 << 6) +#define VSD_2_0 BIT(6) #define VSD_2_6 (2 << 6) #define VSD_2_7 (3 << 6) #define VSD_2_8 (4 << 6) @@ -99,7 +99,7 @@ #define VGEN1_3_15 3 #define VGEN1_MASK 3 #define VGEN2_1_2 (0 << 6) -#define VGEN2_1_5 (1 << 6) +#define VGEN2_1_5 BIT(6) #define VGEN2_1_6 (2 << 6) #define VGEN2_1_8 (3 << 6) #define VGEN2_2_7 (4 << 6) @@ -110,55 +110,55 @@ /* Fields in REG_SETTING_1 */ #define VGEN3_1_8 (0 << 14) -#define VGEN3_2_9 (1 << 14) -#define VGEN3_MASK (1 << 14) +#define VGEN3_2_9 BIT(14) +#define VGEN3_MASK BIT(14) #define VDIG_1_05 (0 << 4) -#define VDIG_1_25 (1 << 4) +#define VDIG_1_25 BIT(4) #define VDIG_1_65 (2 << 4) #define VDIG_1_8 (3 << 4) #define VDIG_MASK (3 << 4) #define VCAM_2_5 (0 << 16) -#define VCAM_2_6 (1 << 16) +#define VCAM_2_6 BIT(16) #define VCAM_2_75 (2 << 16) #define VCAM_3_0 (3 << 16) #define VCAM_MASK (3 << 16) /* Reg Mode 0 */ -#define VGEN1EN (1 << 0) -#define VGEN1STBY (1 << 1) -#define VGEN1MODE (1 << 2) -#define VIOHIEN (1 << 3) -#define VIOHISTBY (1 << 4) -#define VDIGEN (1 << 9) -#define VDIGSTBY (1 << 10) -#define VGEN2EN (1 << 12) -#define VGEN2STBY (1 << 13) -#define VGEN2MODE (1 << 14) -#define VPLLEN (1 << 15) -#define VPLLSTBY (1 << 16) -#define VUSBEN (1 << 18) -#define VUSBSTBY (1 << 19) +#define VGEN1EN BIT(0) +#define VGEN1STBY BIT(1) +#define VGEN1MODE BIT(2) +#define VIOHIEN BIT(3) +#define VIOHISTBY BIT(4) +#define VDIGEN BIT(9) +#define VDIGSTBY BIT(10) +#define VGEN2EN BIT(12) +#define VGEN2STBY BIT(13) +#define VGEN2MODE BIT(14) +#define VPLLEN BIT(15) +#define VPLLSTBY BIT(16) +#define VUSBEN BIT(18) +#define VUSBSTBY BIT(19) /* Reg Mode 1 */ -#define VGEN3EN (1 << 0) -#define VGEN3STBY (1 << 1) -#define VGEN3MODE (1 << 2) -#define VGEN3CONFIG (1 << 3) -#define VCAMEN (1 << 6) -#define VCAMSTBY (1 << 7) -#define VCAMMODE (1 << 8) -#define VCAMCONFIG (1 << 9) -#define VVIDEOEN (1 << 12) -#define VIDEOSTBY (1 << 13) -#define VVIDEOMODE (1 << 14) -#define VAUDIOEN (1 << 15) -#define VAUDIOSTBY (1 << 16) -#define VSDEN (1 << 18) -#define VSDSTBY (1 << 19) -#define VSDMODE (1 << 20) +#define VGEN3EN BIT(0) +#define VGEN3STBY BIT(1) +#define VGEN3MODE BIT(2) +#define VGEN3CONFIG BIT(3) +#define VCAMEN BIT(6) +#define VCAMSTBY BIT(7) +#define VCAMMODE BIT(8) +#define VCAMCONFIG BIT(9) +#define VVIDEOEN BIT(12) +#define VIDEOSTBY BIT(13) +#define VVIDEOMODE BIT(14) +#define VAUDIOEN BIT(15) +#define VAUDIOSTBY BIT(16) +#define VSDEN BIT(18) +#define VSDSTBY BIT(19) +#define VSDMODE BIT(20) /* Reg Power Control 2*/ -#define WDIRESET (1 << 12) +#define WDIRESET BIT(12) /* SWx Output Volts */ #define SWX_OUT_MASK 0x1F diff --git a/include/mc34704.h b/include/mc34704.h index 482d51a..2979815 100644 --- a/include/mc34704.h +++ b/include/mc34704.h @@ -38,9 +38,9 @@ enum { }; /* GENERAL2 register fields */ -#define ONOFFE (1 << 0) -#define ONOFFD (1 << 1) -#define ONOFFA (1 << 3) -#define ALLOFF (1 << 4) +#define ONOFFE BIT(0) +#define ONOFFD BIT(1) +#define ONOFFA BIT(3) +#define ALLOFF BIT(4) #endif /* __MC34704_H__ */ diff --git a/include/mmc.h b/include/mmc.h index 2ad0f19..b7d4c37 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -50,13 +50,13 @@ #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) -#define MMC_MODE_HS (1 << 0) -#define MMC_MODE_HS_52MHz (1 << 1) -#define MMC_MODE_4BIT (1 << 2) -#define MMC_MODE_8BIT (1 << 3) -#define MMC_MODE_SPI (1 << 4) -#define MMC_MODE_HC (1 << 5) -#define MMC_MODE_DDR_52MHz (1 << 6) +#define MMC_MODE_HS BIT(0) +#define MMC_MODE_HS_52MHz BIT(1) +#define MMC_MODE_4BIT BIT(2) +#define MMC_MODE_8BIT BIT(3) +#define MMC_MODE_SPI BIT(4) +#define MMC_MODE_HC BIT(5) +#define MMC_MODE_DDR_52MHz BIT(6) #define SD_DATA_4BIT 0x00040000 @@ -126,10 +126,10 @@ #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) -#define MMC_STATUS_SWITCH_ERROR (1 << 7) -#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_SWITCH_ERROR BIT(7) +#define MMC_STATUS_RDY_FOR_DATA BIT(8) #define MMC_STATUS_CURR_STATE (0xf << 9) -#define MMC_STATUS_ERROR (1 << 19) +#define MMC_STATUS_ERROR BIT(19) #define MMC_STATE_PRG (7 << 9) @@ -193,14 +193,14 @@ * EXT_CSD field definitions */ -#define EXT_CSD_CMD_SET_NORMAL (1 << 0) -#define EXT_CSD_CMD_SET_SECURE (1 << 1) -#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) +#define EXT_CSD_CMD_SET_NORMAL BIT(0) +#define EXT_CSD_CMD_SET_SECURE BIT(1) +#define EXT_CSD_CMD_SET_CPSECURE BIT(2) -#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ -#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) -#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_26 BIT(0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 BIT(1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V BIT(2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V BIT(3) #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | EXT_CSD_CARD_TYPE_DDR_1_2V) @@ -210,9 +210,9 @@ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ -#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) -#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) -#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) +#define EXT_CSD_BOOT_ACK_ENABLE BIT(6) +#define EXT_CSD_BOOT_PARTITION_ENABLE BIT(3) +#define EXT_CSD_PARTITION_ACCESS_ENABLE BIT(0) #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) #define EXT_CSD_BOOT_ACK(x) (x << 6) @@ -223,24 +223,24 @@ #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) -#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) +#define EXT_CSD_PARTITION_SETTING_COMPLETED BIT(0) -#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ +#define EXT_CSD_ENH_USR BIT(0) /* user data area is enhanced */ #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ -#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ +#define EXT_CSD_HS_CTRL_REL BIT(0) /* host controlled WR_REL_SET */ -#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ +#define EXT_CSD_WR_DATA_REL_USR BIT(0) /* user data area WR_REL */ #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ -#define R1_ILLEGAL_COMMAND (1 << 22) -#define R1_APP_CMD (1 << 5) +#define R1_ILLEGAL_COMMAND BIT(22) +#define R1_APP_CMD BIT(5) -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ +#define MMC_RSP_PRESENT BIT(0) +#define MMC_RSP_136 BIT(1) /* 136 bit response */ +#define MMC_RSP_CRC BIT(2) /* expect valid crc */ +#define MMC_RSP_BUSY BIT(3) /* card may send busy */ +#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */ #define MMC_RSP_NONE (0) #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a6d721a..56a24d2 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -340,50 +340,50 @@ #elif defined(CONFIG_MPC8308) /* SICRL bits - MPC8308 specific */ #define SICRL_SPI_PF0 (0 << 28) -#define SICRL_SPI_PF1 (1 << 28) +#define SICRL_SPI_PF1 BIT(28) #define SICRL_SPI_PF3 (3 << 28) #define SICRL_UART_PF0 (0 << 26) -#define SICRL_UART_PF1 (1 << 26) +#define SICRL_UART_PF1 BIT(26) #define SICRL_UART_PF3 (3 << 26) #define SICRL_IRQ_PF0 (0 << 24) -#define SICRL_IRQ_PF1 (1 << 24) +#define SICRL_IRQ_PF1 BIT(24) #define SICRL_I2C2_PF0 (0 << 20) -#define SICRL_I2C2_PF1 (1 << 20) +#define SICRL_I2C2_PF1 BIT(20) #define SICRL_ETSEC1_TX_CLK (0 << 6) -#define SICRL_ETSEC1_GTX_CLK125 (1 << 6) +#define SICRL_ETSEC1_GTX_CLK125 BIT(6) /* SICRH bits - MPC8308 specific */ #define SICRH_ESDHC_A_SD (0 << 30) -#define SICRH_ESDHC_A_GTM (1 << 30) +#define SICRH_ESDHC_A_GTM BIT(30) #define SICRH_ESDHC_A_GPIO (3 << 30) #define SICRH_ESDHC_B_SD (0 << 28) -#define SICRH_ESDHC_B_GTM (1 << 28) +#define SICRH_ESDHC_B_GTM BIT(28) #define SICRH_ESDHC_B_GPIO (3 << 28) #define SICRH_ESDHC_C_SD (0 << 26) -#define SICRH_ESDHC_C_GTM (1 << 26) +#define SICRH_ESDHC_C_GTM BIT(26) #define SICRH_ESDHC_C_GPIO (3 << 26) #define SICRH_GPIO_A_GPIO (0 << 24) -#define SICRH_GPIO_A_TSEC2 (1 << 24) +#define SICRH_GPIO_A_TSEC2 BIT(24) #define SICRH_GPIO_B_GPIO (0 << 22) -#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) +#define SICRH_GPIO_B_TSEC2_TX_CLK BIT(22) #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) -#define SICRH_IEEE1588_A_TMR (1 << 20) +#define SICRH_IEEE1588_A_TMR BIT(20) #define SICRH_IEEE1588_A_GPIO (3 << 20) -#define SICRH_USB (1 << 18) -#define SICRH_GTM_GTM (1 << 16) +#define SICRH_USB BIT(18) +#define SICRH_GTM_GTM BIT(16) #define SICRH_GTM_GPIO (3 << 16) -#define SICRH_IEEE1588_B_TMR (1 << 14) +#define SICRH_IEEE1588_B_TMR BIT(14) #define SICRH_IEEE1588_B_GPIO (3 << 14) -#define SICRH_ETSEC2_CRS (1 << 12) +#define SICRH_ETSEC2_CRS BIT(12) #define SICRH_ETSEC2_GPIO (3 << 12) #define SICRH_GPIOSEL_0 (0 << 8) -#define SICRH_GPIOSEL_1 (1 << 8) +#define SICRH_GPIOSEL_1 BIT(8) #define SICRH_TMROBI_V3P3 (0 << 4) -#define SICRH_TMROBI_V2P5 (1 << 4) +#define SICRH_TMROBI_V2P5 BIT(4) #define SICRH_TSOBI1_V3P3 (0 << 1) -#define SICRH_TSOBI1_V2P5 (1 << 1) +#define SICRH_TSOBI1_V2P5 BIT(1) #define SICRH_TSOBI2_V3P3 (0 << 0) -#define SICRH_TSOBI2_V2P5 (1 << 0) +#define SICRH_TSOBI2_V2P5 BIT(0) #elif defined(CONFIG_MPC8309) /* SICR_1 */ diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index 7fb71f7..8be18a2 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -75,12 +75,12 @@ #define WINDOW_BASE(i) (0x10c + ((i) << 3)) /* SDIO_PRESENT_STATE */ -#define CARD_BUSY (1 << 1) -#define CMD_INHIBIT (1 << 0) -#define CMD_TXACTIVE (1 << 8) -#define CMD_RXACTIVE (1 << 9) -#define CMD_FIFO_EMPTY (1 << 13) -#define CMD_AUTOCMD12ACTIVE (1 << 14) +#define CARD_BUSY BIT(1) +#define CMD_INHIBIT BIT(0) +#define CMD_TXACTIVE BIT(8) +#define CMD_RXACTIVE BIT(9) +#define CMD_FIFO_EMPTY BIT(13) +#define CMD_AUTOCMD12ACTIVE BIT(14) #define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ CMD_RXACTIVE | \ CMD_TXACTIVE | \ @@ -92,15 +92,15 @@ */ #define SDIO_CMD_RSP_NONE (0 << 0) -#define SDIO_CMD_RSP_136 (1 << 0) +#define SDIO_CMD_RSP_136 BIT(0) #define SDIO_CMD_RSP_48 (2 << 0) #define SDIO_CMD_RSP_48BUSY (3 << 0) -#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) -#define SDIO_CMD_CHECK_CMDCRC (1 << 3) -#define SDIO_CMD_INDX_CHECK (1 << 4) -#define SDIO_CMD_DATA_PRESENT (1 << 5) -#define SDIO_UNEXPECTED_RESP (1 << 7) +#define SDIO_CMD_CHECK_DATACRC16 BIT(2) +#define SDIO_CMD_CHECK_CMDCRC BIT(3) +#define SDIO_CMD_INDX_CHECK BIT(4) +#define SDIO_CMD_DATA_PRESENT BIT(5) +#define SDIO_UNEXPECTED_RESP BIT(7) #define SDIO_CMD_INDEX(x) ((x) << 8) @@ -108,79 +108,79 @@ * SDIO_XFER_MODE */ -#define SDIO_XFER_MODE_STOP_CLK (1 << 5) -#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) -#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) -#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) -#define SDIO_XFER_MODE_TO_HOST (1 << 4) +#define SDIO_XFER_MODE_STOP_CLK BIT(5) +#define SDIO_XFER_MODE_HW_WR_DATA_EN BIT(1) +#define SDIO_XFER_MODE_AUTO_CMD12 BIT(2) +#define SDIO_XFER_MODE_INT_CHK_EN BIT(3) +#define SDIO_XFER_MODE_TO_HOST BIT(4) #define SDIO_XFER_MODE_DMA (0 << 6) /* * SDIO_HOST_CTRL */ -#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) +#define SDIO_HOST_CTRL_PUSH_PULL_EN BIT(0) #define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) -#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY BIT(1) #define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) #define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) #define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) -#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) -#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) +#define SDIO_HOST_CTRL_BIG_ENDIAN BIT(3) +#define SDIO_HOST_CTRL_LSB_FIRST BIT(4) #define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) -#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) -#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS BIT(9) +#define SDIO_HOST_CTRL_HI_SPEED_EN BIT(10) #define SDIO_HOST_CTRL_TMOUT_MAX 0xf #define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) #define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) -#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) +#define SDIO_HOST_CTRL_TMOUT_EN BIT(15) /* * SDIO_SW_RESET */ -#define SDIO_SW_RESET_NOW (1 << 8) +#define SDIO_SW_RESET_NOW BIT(8) /* * Normal interrupt status bits */ -#define SDIO_NOR_ERROR (1 << 15) -#define SDIO_NOR_UNEXP_RSP (1 << 14) -#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) -#define SDIO_NOR_SUSPEND_ON (1 << 12) -#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) -#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) -#define SDIO_NOR_READ_WAIT_ON (1 << 9) -#define SDIO_NOR_CARD_INT (1 << 8) -#define SDIO_NOR_READ_READY (1 << 5) -#define SDIO_NOR_WRITE_READY (1 << 4) -#define SDIO_NOR_DMA_INI (1 << 3) -#define SDIO_NOR_BLK_GAP_EVT (1 << 2) -#define SDIO_NOR_XFER_DONE (1 << 1) -#define SDIO_NOR_CMD_DONE (1 << 0) +#define SDIO_NOR_ERROR BIT(15) +#define SDIO_NOR_UNEXP_RSP BIT(14) +#define SDIO_NOR_AUTOCMD12_DONE BIT(13) +#define SDIO_NOR_SUSPEND_ON BIT(12) +#define SDIO_NOR_LMB_FF_8W_AVAIL BIT(11) +#define SDIO_NOR_LMB_FF_8W_FILLED BIT(10) +#define SDIO_NOR_READ_WAIT_ON BIT(9) +#define SDIO_NOR_CARD_INT BIT(8) +#define SDIO_NOR_READ_READY BIT(5) +#define SDIO_NOR_WRITE_READY BIT(4) +#define SDIO_NOR_DMA_INI BIT(3) +#define SDIO_NOR_BLK_GAP_EVT BIT(2) +#define SDIO_NOR_XFER_DONE BIT(1) +#define SDIO_NOR_CMD_DONE BIT(0) /* * Error status bits */ -#define SDIO_ERR_CRC_STATUS (1 << 14) -#define SDIO_ERR_CRC_STARTBIT (1 << 13) -#define SDIO_ERR_CRC_ENDBIT (1 << 12) -#define SDIO_ERR_RESP_TBIT (1 << 11) -#define SDIO_ERR_XFER_SIZE (1 << 10) -#define SDIO_ERR_CMD_STARTBIT (1 << 9) -#define SDIO_ERR_AUTOCMD12 (1 << 8) -#define SDIO_ERR_DATA_ENDBIT (1 << 6) -#define SDIO_ERR_DATA_CRC (1 << 5) -#define SDIO_ERR_DATA_TIMEOUT (1 << 4) -#define SDIO_ERR_CMD_INDEX (1 << 3) -#define SDIO_ERR_CMD_ENDBIT (1 << 2) -#define SDIO_ERR_CMD_CRC (1 << 1) -#define SDIO_ERR_CMD_TIMEOUT (1 << 0) +#define SDIO_ERR_CRC_STATUS BIT(14) +#define SDIO_ERR_CRC_STARTBIT BIT(13) +#define SDIO_ERR_CRC_ENDBIT BIT(12) +#define SDIO_ERR_RESP_TBIT BIT(11) +#define SDIO_ERR_XFER_SIZE BIT(10) +#define SDIO_ERR_CMD_STARTBIT BIT(9) +#define SDIO_ERR_AUTOCMD12 BIT(8) +#define SDIO_ERR_DATA_ENDBIT BIT(6) +#define SDIO_ERR_DATA_CRC BIT(5) +#define SDIO_ERR_DATA_TIMEOUT BIT(4) +#define SDIO_ERR_CMD_INDEX BIT(3) +#define SDIO_ERR_CMD_ENDBIT BIT(2) +#define SDIO_ERR_CMD_CRC BIT(1) +#define SDIO_ERR_CMD_TIMEOUT BIT(0) /* enable all for polling */ #define SDIO_POLL_MASK 0xffff @@ -188,23 +188,23 @@ * CMD12 error status bits */ -#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) -#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) -#define SDIO_AUTOCMD12_ERR_CRC (1 << 2) -#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) -#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) -#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) -#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) +#define SDIO_AUTOCMD12_ERR_NOTEXE BIT(0) +#define SDIO_AUTOCMD12_ERR_TIMEOUT BIT(1) +#define SDIO_AUTOCMD12_ERR_CRC BIT(2) +#define SDIO_AUTOCMD12_ERR_ENDBIT BIT(3) +#define SDIO_AUTOCMD12_ERR_INDEX BIT(4) +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT BIT(5) +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT BIT(6) -#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_PRESENT BIT(0) /* 136 bit response */ -#define MMC_RSP_136 (1 << 1) +#define MMC_RSP_136 BIT(1) /* expect valid crc */ -#define MMC_RSP_CRC (1 << 2) +#define MMC_RSP_CRC BIT(2) /* card may send busy */ -#define MMC_RSP_BUSY (1 << 3) +#define MMC_RSP_BUSY BIT(3) /* response contains opcode */ -#define MMC_RSP_OPCODE (1 << 4) +#define MMC_RSP_OPCODE BIT(4) #define MMC_BUSMODE_OPENDRAIN 1 #define MMC_BUSMODE_PUSHPULL 2 @@ -214,54 +214,54 @@ #define MMC_BUS_WIDTH_8 3 /* Can the host do 4 bit transfers */ -#define MMC_CAP_4_BIT_DATA (1 << 0) +#define MMC_CAP_4_BIT_DATA BIT(0) /* Can do MMC high-speed timing */ -#define MMC_CAP_MMC_HIGHSPEED (1 << 1) +#define MMC_CAP_MMC_HIGHSPEED BIT(1) /* Can do SD high-speed timing */ -#define MMC_CAP_SD_HIGHSPEED (1 << 2) +#define MMC_CAP_SD_HIGHSPEED BIT(2) /* Can signal pending SDIO IRQs */ -#define MMC_CAP_SDIO_IRQ (1 << 3) +#define MMC_CAP_SDIO_IRQ BIT(3) /* Talks only SPI protocols */ -#define MMC_CAP_SPI (1 << 4) +#define MMC_CAP_SPI BIT(4) /* Needs polling for card-detection */ -#define MMC_CAP_NEEDS_POLL (1 << 5) +#define MMC_CAP_NEEDS_POLL BIT(5) /* Can the host do 8 bit transfers */ -#define MMC_CAP_8_BIT_DATA (1 << 6) +#define MMC_CAP_8_BIT_DATA BIT(6) /* Nonremovable e.g. eMMC */ -#define MMC_CAP_NONREMOVABLE (1 << 8) +#define MMC_CAP_NONREMOVABLE BIT(8) /* Waits while card is busy */ -#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) +#define MMC_CAP_WAIT_WHILE_BUSY BIT(9) /* Allow erase/trim commands */ -#define MMC_CAP_ERASE (1 << 10) +#define MMC_CAP_ERASE BIT(10) /* can support DDR mode at 1.8V */ -#define MMC_CAP_1_8V_DDR (1 << 11) +#define MMC_CAP_1_8V_DDR BIT(11) /* can support DDR mode at 1.2V */ -#define MMC_CAP_1_2V_DDR (1 << 12) +#define MMC_CAP_1_2V_DDR BIT(12) /* Can power off after boot */ -#define MMC_CAP_POWER_OFF_CARD (1 << 13) +#define MMC_CAP_POWER_OFF_CARD BIT(13) /* CMD14/CMD19 bus width ok */ -#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) +#define MMC_CAP_BUS_WIDTH_TEST BIT(14) /* Host supports UHS SDR12 mode */ -#define MMC_CAP_UHS_SDR12 (1 << 15) +#define MMC_CAP_UHS_SDR12 BIT(15) /* Host supports UHS SDR25 mode */ -#define MMC_CAP_UHS_SDR25 (1 << 16) +#define MMC_CAP_UHS_SDR25 BIT(16) /* Host supports UHS SDR50 mode */ -#define MMC_CAP_UHS_SDR50 (1 << 17) +#define MMC_CAP_UHS_SDR50 BIT(17) /* Host supports UHS SDR104 mode */ -#define MMC_CAP_UHS_SDR104 (1 << 18) +#define MMC_CAP_UHS_SDR104 BIT(18) /* Host supports UHS DDR50 mode */ -#define MMC_CAP_UHS_DDR50 (1 << 19) +#define MMC_CAP_UHS_DDR50 BIT(19) /* Host supports Driver Type A */ -#define MMC_CAP_DRIVER_TYPE_A (1 << 23) +#define MMC_CAP_DRIVER_TYPE_A BIT(23) /* Host supports Driver Type C */ -#define MMC_CAP_DRIVER_TYPE_C (1 << 24) +#define MMC_CAP_DRIVER_TYPE_C BIT(24) /* Host supports Driver Type D */ -#define MMC_CAP_DRIVER_TYPE_D (1 << 25) +#define MMC_CAP_DRIVER_TYPE_D BIT(25) /* CMD23 supported. */ -#define MMC_CAP_CMD23 (1 << 30) +#define MMC_CAP_CMD23 BIT(30) /* Hardware reset */ -#define MMC_CAP_HW_RESET (1 << 31) +#define MMC_CAP_HW_RESET BIT(31) struct mvebu_mmc_cfg { u32 mvebu_mmc_base; diff --git a/include/nand.h b/include/nand.h index d2a53ab..e9c84ed 100644 --- a/include/nand.h +++ b/include/nand.h @@ -104,8 +104,8 @@ typedef struct nand_erase_options nand_erase_options_t; int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer); -#define WITH_DROP_FFS (1 << 0) /* drop trailing all-0xff pages */ -#define WITH_WR_VERIFY (1 << 1) /* verify data was written correctly */ +#define WITH_DROP_FFS BIT(0) /* drop trailing all-0xff pages */ +#define WITH_WR_VERIFY BIT(1) /* verify data was written correctly */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer, int flags); diff --git a/include/netdev.h b/include/netdev.h index d96e1da..c19f490 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -102,8 +102,8 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, */ #if defined(CONFIG_XILINX_LL_TEMAC) #define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */ -#define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */ -#define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */ +#define XILINX_LL_TEMAC_M_SDMA_PLB BIT(0)/* use SDMA Ctrl via PLB */ +#define XILINX_LL_TEMAC_M_SDMA_DCR BIT(1)/* use SDMA Ctrl via DCR */ #endif /* Boards with PCI network controllers can call this from their board_eth_init() diff --git a/include/palmas.h b/include/palmas.h index cca3f9a..46fc310 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -47,10 +47,10 @@ * Bit field definitions for LDOx_CTRL, SYSENx_CTRL * and some other xxx_CTRL resources: */ -#define LDO9_BYP_EN (1 << 6) /* LDO9 only! */ -#define RSC_STAT_ON (1 << 4) /* RO status bit! */ -#define RSC_MODE_SLEEP (1 << 2) -#define RSC_MODE_ACTIVE (1 << 0) +#define LDO9_BYP_EN BIT(6) /* LDO9 only! */ +#define RSC_STAT_ON BIT(4) /* RO status bit! */ +#define RSC_MODE_SLEEP BIT(2) +#define RSC_MODE_ACTIVE BIT(0) /* Some LDO voltage values */ #define LDO_VOLT_OFF 0 @@ -75,7 +75,7 @@ #define SMPS_MODE_ACT_AUTO 1 #define SMPS_MODE_ACT_ECO 2 #define SMPS_MODE_ACT_FPWM 3 -#define SMPS_MODE_SLP_AUTO (1 << 2) +#define SMPS_MODE_SLP_AUTO BIT(2) #define SMPS_MODE_SLP_ECO (2 << 2) #define SMPS_MODE_SLP_FPWM (3 << 2) @@ -93,16 +93,16 @@ /* Backup Battery & VRTC Control */ #define BB_VRTC_CTRL 0xa8 /* Bit definitions for BB_VRTC_CTRL */ -#define VRTC_EN_SLP (1 << 6) -#define VRTC_EN_OFF (1 << 5) -#define VRTC_PWEN (1 << 4) -#define BB_LOW_ICHRG (1 << 3) +#define VRTC_EN_SLP BIT(6) +#define VRTC_EN_OFF BIT(5) +#define VRTC_PWEN BIT(4) +#define BB_LOW_ICHRG BIT(3) #define BB_HIGH_ICHRG (0 << 3) #define BB_VSEL_3V0 (0 << 1) -#define BB_VSEL_2V5 (1 << 1) +#define BB_VSEL_2V5 BIT(1) #define BB_VSEL_3V15 (2 << 1) #define BB_VSEL_VBAT (3 << 1) -#define BB_CHRG_EN (1 << 0) +#define BB_CHRG_EN BIT(0) /* * Functions to read and write from TPS659038/TWL6035/TWL6037 diff --git a/include/power/as3722.h b/include/power/as3722.h index aa966d2..06f713b 100644 --- a/include/power/as3722.h +++ b/include/power/as3722.h @@ -9,8 +9,8 @@ #include -#define AS3722_GPIO_OUTPUT_VDDH (1 << 0) -#define AS3722_GPIO_INVERT (1 << 1) +#define AS3722_GPIO_OUTPUT_VDDH BIT(0) +#define AS3722_GPIO_INVERT BIT(1) struct udevice; diff --git a/include/power/max17042_fg.h b/include/power/max17042_fg.h index ce96053..f3c00a1 100644 --- a/include/power/max17042_fg.h +++ b/include/power/max17042_fg.h @@ -45,7 +45,7 @@ enum { #define TempCo 0x1015 -#define MAX17042_POR (1 << 1) +#define MAX17042_POR BIT(1) #define MODEL_UNLOCK1 0x0059 #define MODEL_UNLOCK2 0x00c4 diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index b0e4255..01806a1 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -177,13 +177,13 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); #define MAX77686_BUCK1CTRL_EN (3 << 0) /* Buck2 1.3 volt value */ #define MAX77686_BUCK2DVS1_1_3V 0x38 -#define MAX77686_BUCK2CTRL_ON (1 << 4) +#define MAX77686_BUCK2CTRL_ON BIT(4) /* Buck3 1.0125 volt value */ #define MAX77686_BUCK3DVS1_1_0125V 0x21 -#define MAX77686_BUCK3CTRL_ON (1 << 4) +#define MAX77686_BUCK3CTRL_ON BIT(4) /* Buck4 1.2 volt value */ #define MAX77686_BUCK4DVS1_1_2V 0x30 -#define MAX77686_BUCK4CTRL_ON (1 << 4) +#define MAX77686_BUCK4CTRL_ON BIT(4) /* LDO2 1.5 volt value */ #define MAX77686_LD02CTRL1_1_5V 0x1c /* LDO3 1.8 volt value */ @@ -196,12 +196,12 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); * MAX77686_REG_PMIC_32KHZ set to 32KH CP * output is activated */ -#define MAX77686_32KHCP_EN (1 << 1) +#define MAX77686_32KHCP_EN BIT(1) /* * MAX77686_REG_PMIC_BBAT set to * Back up batery charger on and * limit voltage setting to 3.5v */ -#define MAX77686_BBCHOSTEN (1 << 0) +#define MAX77686_BBCHOSTEN BIT(0) #define MAX77686_BBCVS_3_5V (3 << 3) #endif /* __MAX77686_PMIC_H_ */ diff --git a/include/power/max77693_fg.h b/include/power/max77693_fg.h index 42626ed..11ee14c 100644 --- a/include/power/max77693_fg.h +++ b/include/power/max77693_fg.h @@ -36,7 +36,7 @@ enum { FG_NUM_OF_REGS = 0x100, }; -#define MAX77693_POR (1 << 1) +#define MAX77693_POR BIT(1) #define MODEL_UNLOCK1 0x0059 #define MODEL_UNLOCK2 0x00c4 diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h index 3d59e59..14553fa 100644 --- a/include/power/max77693_pmic.h +++ b/include/power/max77693_pmic.h @@ -32,8 +32,8 @@ #define MAX77693_CHG_LOCK (0x0 << 2) /* MAX77693_CHG_CNFG_06 */ #define MAX77693_CHG_UNLOCK (0x3 << 2) /* MAX77693_CHG_CNFG_06 */ -#define MAX77693_ENSAFEOUT1 (1 << 6) -#define MAX77693_ENSAFEOUT2 (1 << 7) +#define MAX77693_ENSAFEOUT1 BIT(6) +#define MAX77693_ENSAFEOUT2 BIT(7) #define MAX77693_PMIC_I2C_ADDR (0xCC >> 1) diff --git a/include/power/max8997_pmic.h b/include/power/max8997_pmic.h index 728d60a..fe981ae 100644 --- a/include/power/max8997_pmic.h +++ b/include/power/max8997_pmic.h @@ -155,25 +155,25 @@ enum { PMIC_NUM_OF_REGS = 0x9b, }; -#define ACTDISSAFEO1 (1 << 4) -#define ACTDISSAFEO2 (1 << 5) -#define ENSAFEOUT1 (1 << 6) -#define ENSAFEOUT2 (1 << 7) - -#define ENBUCK (1 << 0) -#define ACTIVE_DISCHARGE (1 << 3) -#define GNSLCT (1 << 2) -#define LDO_ADE (1 << 1) +#define ACTDISSAFEO1 BIT(4) +#define ACTDISSAFEO2 BIT(5) +#define ENSAFEOUT1 BIT(6) +#define ENSAFEOUT2 BIT(7) + +#define ENBUCK BIT(0) +#define ACTIVE_DISCHARGE BIT(3) +#define GNSLCT BIT(2) +#define LDO_ADE BIT(1) #define SAFEOUT_4_85V 0x00 #define SAFEOUT_4_90V 0x01 #define SAFEOUT_4_95V 0x02 #define SAFEOUT_3_30V 0x03 /* Charger */ -#define DETBAT (1 << 2) -#define MBCICHFCSET (1 << 4) -#define MBCHOSTEN (1 << 6) -#define VCHGR_FC (1 << 7) +#define DETBAT BIT(2) +#define MBCICHFCSET BIT(4) +#define MBCHOSTEN BIT(6) +#define VCHGR_FC BIT(7) #define CHARGER_MIN_CURRENT 200 #define CHARGER_MAX_CURRENT 950 diff --git a/include/power/max8998_pmic.h b/include/power/max8998_pmic.h index 03d06e8..98d00eb 100644 --- a/include/power/max8998_pmic.h +++ b/include/power/max8998_pmic.h @@ -58,12 +58,12 @@ enum { PMIC_NUM_OF_REGS, }; -#define MAX8998_LDO3 (1 << 2) -#define MAX8998_LDO4 (1 << 1) -#define MAX8998_LDO7 (1 << 6) -#define MAX8998_LDO8 (1 << 5) -#define MAX8998_LDO17 (1 << 4) -#define MAX8998_SAFEOUT1 (1 << 4) +#define MAX8998_LDO3 BIT(2) +#define MAX8998_LDO4 BIT(1) +#define MAX8998_LDO7 BIT(6) +#define MAX8998_LDO8 BIT(5) +#define MAX8998_LDO17 BIT(4) +#define MAX8998_SAFEOUT1 BIT(4) #define MAX8998_I2C_ADDR (0xCC >> 1) diff --git a/include/radeon.h b/include/radeon.h index da6c26b..8a67819 100644 --- a/include/radeon.h +++ b/include/radeon.h @@ -154,10 +154,10 @@ #define PALETTE_30_DATA 0x00B8 #define CRTC_H_TOTAL_DISP 0x0200 #define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_H_SYNC_POL (1 << 23) +#define CRTC_H_SYNC_POL BIT(23) #define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_V_SYNC_POL (1 << 23) +#define CRTC_V_SYNC_POL BIT(23) #define CRTC_VLINE_CRNT_VLINE 0x0210 #define CRTC_CRNT_FRAME 0x0214 #define CRTC_GUI_TRIG_VLINE 0x0218 @@ -415,7 +415,7 @@ #define BIOS_6_SCRATCH 0x0028 #define BIOS_7_SCRATCH 0x002c -#define HDP_SOFT_RESET (1 << 26) +#define HDP_SOFT_RESET BIT(26) #define TV_DAC_CNTL 0x088c #define GPIOPAD_MASK 0x0198 @@ -456,12 +456,12 @@ #define SCLK_MORE_CNTL 0x0035 /* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) +#define FORCEON_MCLKA BIT(16) +#define FORCEON_MCLKB BIT(17) +#define FORCEON_YCLKA BIT(18) +#define FORCEON_YCLKB BIT(19) +#define FORCEON_MC BIT(20) +#define FORCEON_AIC BIT(21) /* SCLK_CNTL bit constants */ #define DYN_STOP_LAT_MASK 0x00007ff8 @@ -504,9 +504,9 @@ #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 #define PIX2CLK_ALWAYS_ONb (1<<6) #define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define PIXCLK_TV_SRC_SEL BIT(8) +#define PIXCLK_LVDS_ALWAYS_ONb BIT(14) +#define PIXCLK_TMDS_ALWAYS_ONb BIT(15) /* CLOCK_CNTL_INDEX bit constants */ @@ -516,42 +516,42 @@ #define CONFIG_SYS_VGA_RAM_EN 0x00000100 #define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16) #define CONFIG_SYS_ATI_REV_A11 (0 << 16) -#define CONFIG_SYS_ATI_REV_A12 (1 << 16) +#define CONFIG_SYS_ATI_REV_A12 BIT(16) #define CONFIG_SYS_ATI_REV_A13 (2 << 16) /* CRTC_EXT_CNTL bit constants */ #define VGA_ATI_LINEAR 0x00000008 #define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) +#define XCRT_CNT_EN BIT(6) +#define CRTC_HSYNC_DIS BIT(8) +#define CRTC_VSYNC_DIS BIT(9) +#define CRTC_DISPLAY_DIS BIT(10) +#define CRTC_CRT_ON BIT(15) /* DSTCACHE_CTLSTAT bit constants */ #define RB2D_DC_FLUSH (3 << 0) #define RB2D_DC_FLUSH_ALL 0xf -#define RB2D_DC_BUSY (1 << 31) +#define RB2D_DC_BUSY BIT(31) /* CRTC_GEN_CNTL bit constants */ #define CRTC_DBL_SCAN_EN 0x00000001 #define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC_INTERLACE_EN BIT(1) +#define CRTC_BYPASS_LUT_EN BIT(14) +#define CRTC_EXT_DISP_EN BIT(24) +#define CRTC_EN BIT(25) +#define CRTC_DISP_REQ_EN_B BIT(26) /* CRTC_STATUS bit constants */ #define CRTC_VBLANK 0x00000001 /* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) +#define CRT2_ON BIT(7) +#define CRTC2_DISPLAY_DIS BIT(23) +#define CRTC2_EN BIT(25) +#define CRTC2_DISP_REQ_EN_B BIT(26) /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ #define CUR_LOCK 0x80000000 @@ -561,10 +561,10 @@ #define GPIO_A_1 (1 << 1) #define GPIO_Y_0 (1 << 8) #define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) +#define GPIO_EN_0 BIT(16) +#define GPIO_EN_1 BIT(17) +#define GPIO_MASK_0 BIT(24) +#define GPIO_MASK_1 BIT(25) #define VGA_DDC_DATA_OUTPUT GPIO_A_0 #define VGA_DDC_CLK_OUTPUT GPIO_A_1 #define VGA_DDC_DATA_INPUT GPIO_Y_0 @@ -592,61 +592,61 @@ #define FP_V_SYNC_WID_SHIFT 0x00000010 /* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) +#define FP_FPON BIT(0) +#define FP_TMDS_EN BIT(2) +#define FP_PANEL_FORMAT BIT(3) +#define FP_EN_TMDS BIT(7) +#define FP_DETECT_SENSE BIT(8) #define R200_FP_SOURCE_SEL_MASK (3 << 10) #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 BIT(10) #define R200_FP_SOURCE_SEL_RMX (2 << 10) #define R200_FP_SOURCE_SEL_TRANS (3 << 10) #define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) +#define FP_SEL_CRTC2 BIT(13) +#define FP_USE_VGA_HSYNC BIT(14) +#define FP_CRTC_DONT_SHADOW_HPAR BIT(15) +#define FP_CRTC_DONT_SHADOW_VPAR BIT(16) +#define FP_CRTC_DONT_SHADOW_HEND BIT(17) +#define FP_CRTC_USE_SHADOW_VEND BIT(18) +#define FP_RMX_HVSYNC_CONTROL_EN BIT(20) +#define FP_DFP_SYNC_SEL BIT(21) +#define FP_CRTC_LOCK_8DOT BIT(22) +#define FP_CRT_SYNC_SEL BIT(23) +#define FP_USE_SHADOW_EN BIT(24) +#define FP_CRT_SYNC_ALT BIT(26) /* FP2_GEN_CNTL bit constants */ #define FP2_BLANK_EN (1 << 1) #define FP2_ON (1 << 2) #define FP2_PANEL_FORMAT (1 << 3) #define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SOURCE_SEL_CRTC2 BIT(10) #define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) +#define FP2_SRC_SEL_CRTC2 BIT(13) +#define FP2_FP_POL BIT(16) +#define FP2_LP_POL BIT(17) +#define FP2_SCK_POL BIT(18) #define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) +#define FP2_PAD_FLOP_EN BIT(22) +#define FP2_CRC_EN BIT(23) +#define FP2_CRC_READ_EN BIT(24) +#define FP2_DV0_EN BIT(25) +#define FP2_DV0_RATE_SEL_SDR BIT(26) /* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) +#define LVDS_ON BIT(0) +#define LVDS_DISPLAY_DIS BIT(1) +#define LVDS_PANEL_TYPE BIT(2) +#define LVDS_PANEL_FORMAT BIT(3) +#define LVDS_EN BIT(7) #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 #define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_BL_MOD_EN BIT(16) +#define LVDS_DIGON BIT(18) +#define LVDS_BLON BIT(19) +#define LVDS_SEL_CRTC2 BIT(23) #define LVDS_STATE_MASK \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) @@ -655,10 +655,10 @@ #define HSYNC_DELAY_MASK (0xf << 0x1c) /* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) +#define TMDS_PLL_EN BIT(0) +#define TMDS_PLLRST BIT(1) +#define TMDS_RAN_PAT_RST BIT(7) +#define TMDS_ICHCSEL BIT(28) /* FP_HORZ_STRETCH bit constants */ #define HORZ_STRETCH_RATIO_MASK 0xffff @@ -666,11 +666,11 @@ #define HORZ_PANEL_SIZE (0x1ff << 16) #define HORZ_PANEL_SHIFT 16 #define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_STRETCH_BLEND BIT(26) +#define HORZ_STRETCH_ENABLE BIT(25) +#define HORZ_AUTO_RATIO BIT(27) #define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) +#define HORZ_AUTO_RATIO_INC BIT(31) /* FP_VERT_STRETCH bit constants */ @@ -679,9 +679,9 @@ #define VERT_PANEL_SIZE (0xfff << 12) #define VERT_PANEL_SHIFT 12 #define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_STRETCH_BLEND BIT(26) +#define VERT_STRETCH_ENABLE BIT(25) +#define VERT_AUTO_RATIO_EN BIT(27) #define VERT_FP_LOOP_STRETCH (0x7 << 28) #define VERT_STRETCH_RESERVED 0xf1000000 @@ -690,9 +690,9 @@ #define DAC_4BPP_PIX_ORDER 0x00000200 #define DAC_CRC_EN 0x00080000 #define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_PDWN BIT(15) +#define DAC_EXPAND_MODE BIT(14) +#define DAC_VGA_ADR_EN BIT(13) #define DAC_RANGE_CNTL (3 << 0) #define DAC_RANGE_CNTL_MASK 0x03 #define DAC_BLANKING (1 << 2) @@ -700,13 +700,13 @@ #define DAC_CMP_OUTPUT (1 << 7) /* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) +#define DAC2_EXPAND_MODE BIT(14) +#define DAC2_CMP_EN BIT(7) +#define DAC2_PALETTE_ACCESS_CNTL BIT(5) /* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_BLANK_OFF_EN BIT(4) +#define DAC_FORCE_DATA_EN BIT(5) #define DAC_FORCE_DATA_SEL_MASK (3 << 6) #define DAC_FORCE_DATA_MASK 0x0003ff00 #define DAC_FORCE_DATA_SHIFT 8 @@ -745,13 +745,13 @@ #define SOFT_RESET_HDP (1 << 7) /* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) +#define SURF_TRANSLATION_DIS BIT(8) +#define NONSURF_AP0_SWP_16BPP BIT(20) +#define NONSURF_AP0_SWP_32BPP BIT(21) +#define NONSURF_AP1_SWP_16BPP BIT(22) +#define NONSURF_AP1_SWP_32BPP BIT(23) -#define R200_SURF_TILE_COLOR_MACRO (1 << 16) +#define R200_SURF_TILE_COLOR_MACRO BIT(16) /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) @@ -825,7 +825,7 @@ #define BYTE_ORDER_MSB_TO_LSB 0x00000000 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 #define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) +#define HOST_BIG_ENDIAN_EN BIT(29) /* DP_GUI_MASTER_CNTL bit constants */ @@ -881,7 +881,7 @@ #define GMC_AUX_CLIP_CLEAR 0x20000000 #define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_CLR_CMP_CNTL_DIS BIT(28) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define ROP3_S 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000 @@ -947,33 +947,33 @@ #define TV_DAC_CNTL_BDACPD 0x04000000 /* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP BIT(0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP BIT(1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP BIT(2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK BIT(4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK BIT(5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK BIT(6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP BIT(12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK BIT(15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS BIT(16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS BIT(17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS BIT(18) +#define DISP_MISC_CNTL_SOFT_RESET_TV BIT(19) /* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN BIT(0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN BIT(4) +#define DISP_PWR_MAN_DISP_D3_RST BIT(16) +#define DISP_PWR_MAN_DISP_D3_REG_RST BIT(17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST BIT(18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST BIT(19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST BIT(20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST BIT(21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST BIT(22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST BIT(23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST BIT(24) +#define DISP_PWR_MAN_TV_ENABLE_RST BIT(25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN BIT(26) /* masks */ @@ -1106,14 +1106,14 @@ #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb BIT(9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb BIT(10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb BIT(13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb BIT(16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb BIT(17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb BIT(18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb BIT(19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF BIT(23) /* pllP2PLL_DIV_0 */ @@ -1213,8 +1213,8 @@ #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA BIT(21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB BIT(21) /* MCLK_MISC */ #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L diff --git a/include/sdhci.h b/include/sdhci.h index 23893b5..f716b63 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -205,15 +205,15 @@ /* * quirks */ -#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) -#define SDHCI_QUIRK_REG32_RW (1 << 1) -#define SDHCI_QUIRK_BROKEN_R1B (1 << 2) -#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) -#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) -#define SDHCI_QUIRK_NO_CD (1 << 5) -#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) -#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) -#define SDHCI_QUIRK_USE_WIDE8 (1 << 8) +#define SDHCI_QUIRK_32BIT_DMA_ADDR BIT(0) +#define SDHCI_QUIRK_REG32_RW BIT(1) +#define SDHCI_QUIRK_BROKEN_R1B BIT(2) +#define SDHCI_QUIRK_NO_HISPD_BIT BIT(3) +#define SDHCI_QUIRK_BROKEN_VOLTAGE BIT(4) +#define SDHCI_QUIRK_NO_CD BIT(5) +#define SDHCI_QUIRK_WAIT_SEND_CMD BIT(6) +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER BIT(7) +#define SDHCI_QUIRK_USE_WIDE8 BIT(8) /* to make gcc happy */ struct sdhci_host; diff --git a/include/search.h b/include/search.h index 9701efb..99e93da 100644 --- a/include/search.h +++ b/include/search.h @@ -109,16 +109,16 @@ extern int himport_r(struct hsearch_data *__htab, extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *)); /* Flags for himport_r(), hexport_r(), hdelete_r(), and hsearch_r() */ -#define H_NOCLEAR (1 << 0) /* do not clear hash table before importing */ -#define H_FORCE (1 << 1) /* overwrite read-only/write-once variables */ -#define H_INTERACTIVE (1 << 2) /* indicate that an import is user directed */ -#define H_HIDE_DOT (1 << 3) /* don't print env vars that begin with '.' */ -#define H_MATCH_KEY (1 << 4) /* search/grep key = variable names */ -#define H_MATCH_DATA (1 << 5) /* search/grep data = variable values */ +#define H_NOCLEAR BIT(0) /* do not clear hash table before importing */ +#define H_FORCE BIT(1) /* overwrite read-only/write-once variables */ +#define H_INTERACTIVE BIT(2) /* indicate that an import is user directed */ +#define H_HIDE_DOT BIT(3) /* don't print env vars that begin with '.' */ +#define H_MATCH_KEY BIT(4) /* search/grep key = variable names */ +#define H_MATCH_DATA BIT(5) /* search/grep data = variable values */ #define H_MATCH_BOTH (H_MATCH_KEY | H_MATCH_DATA) /* search/grep both */ -#define H_MATCH_IDENT (1 << 6) /* search for indentical strings */ -#define H_MATCH_SUBSTR (1 << 7) /* search for substring matches */ -#define H_MATCH_REGEX (1 << 8) /* search for regular expression matches */ +#define H_MATCH_IDENT BIT(6) /* search for indentical strings */ +#define H_MATCH_SUBSTR BIT(7) /* search for substring matches */ +#define H_MATCH_REGEX BIT(8) /* search for regular expression matches */ #define H_MATCH_METHOD (H_MATCH_IDENT | H_MATCH_SUBSTR | H_MATCH_REGEX) #endif /* search.h */ diff --git a/include/sh_pfc.h b/include/sh_pfc.h index 7f6548f..7808e5e 100644 --- a/include/sh_pfc.h +++ b/include/sh_pfc.h @@ -24,8 +24,8 @@ typedef unsigned short pinmux_flag_t; #define PINMUX_TYPE_INPUT_PULLDOWN 6 #define PINMUX_FLAG_TYPE (0x7) -#define PINMUX_FLAG_WANT_PULLUP (1 << 3) -#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4) +#define PINMUX_FLAG_WANT_PULLUP BIT(3) +#define PINMUX_FLAG_WANT_PULLDOWN BIT(4) #define PINMUX_FLAG_DBIT_SHIFT 5 #define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) diff --git a/include/spi.h b/include/spi.h index 9495ca5..d040fc9 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,26 +30,26 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_U_PAGE (1 << 5) +#define SPI_XFER_U_PAGE BIT(5) /* SPI TX operation modes */ -#define SPI_OPM_TX_QPP (1 << 0) -#define SPI_OPM_TX_BP (1 << 1) +#define SPI_OPM_TX_QPP BIT(0) +#define SPI_OPM_TX_BP BIT(1) /* SPI RX operation modes */ -#define SPI_OPM_RX_AS (1 << 0) -#define SPI_OPM_RX_AF (1 << 1) -#define SPI_OPM_RX_DOUT (1 << 2) -#define SPI_OPM_RX_DIO (1 << 3) -#define SPI_OPM_RX_QOF (1 << 4) -#define SPI_OPM_RX_QIOF (1 << 5) +#define SPI_OPM_RX_AS BIT(0) +#define SPI_OPM_RX_AF BIT(1) +#define SPI_OPM_RX_DOUT BIT(2) +#define SPI_OPM_RX_DIO BIT(3) +#define SPI_OPM_RX_QOF BIT(4) +#define SPI_OPM_RX_QIOF BIT(5) #define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF) /* SPI bus connection options - see enum spi_dual_flash */ -#define SPI_CONN_DUAL_SHARED (1 << 0) -#define SPI_CONN_DUAL_SEPARATED (1 << 1) +#define SPI_CONN_DUAL_SHARED BIT(0) +#define SPI_CONN_DUAL_SEPARATED BIT(1) /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec diff --git a/include/tsec.h b/include/tsec.h index 58cdc19..c75aad9 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -392,11 +392,11 @@ struct tsec { u32 resc00[256]; }; -#define TSEC_GIGABIT (1 << 0) +#define TSEC_GIGABIT BIT(0) /* These flags currently only have meaning if we're using the eTSEC */ -#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ -#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ +#define TSEC_REDUCED BIT(1) /* MAC-PHY interface uses RGMII */ +#define TSEC_SGMII BIT(2) /* MAC-PHY interface uses SGMII */ struct tsec_private { struct tsec __iomem *regs; diff --git a/include/tsi108.h b/include/tsi108.h index 34bd424..8de480c 100644 --- a/include/tsi108.h +++ b/include/tsi108.h @@ -108,11 +108,11 @@ #define SD_ECC_CTRL (0x040) #define SD_DLL_STATUS (0x250) -#define TS_SD_CTRL_ENABLE (1 << 31) +#define TS_SD_CTRL_ENABLE BIT(31) -#define PB_ERRCS_ES (1 << 1) -#define PB_ISR_PBS_RD_ERR (1 << 8) -#define PCI_IRP_STAT_P_CSR (1 << 23) +#define PB_ERRCS_ES BIT(1) +#define PB_ISR_PBS_RD_ERR BIT(8) +#define PCI_IRP_STAT_P_CSR BIT(23) /* * I2C : Register address offset definitions diff --git a/include/twl4030.h b/include/twl4030.h index 50f8da8..6d048fd 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -130,13 +130,13 @@ #define TWL4030_PM_MASTER_MISC_TST 0x6E #define TWL4030_PM_MASTER_TRIM1 0x6F /* P[1-3]_SW_EVENTS */ -#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6) -#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5) -#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4) -#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3) -#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2) -#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) -#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) +#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON BIT(6) +#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN BIT(5) +#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET BIT(4) +#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP BIT(3) +#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT BIT(2) +#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP BIT(1) +#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF BIT(0) /* Power bus message definitions */ @@ -407,10 +407,10 @@ /* LED */ #define TWL4030_LED_LEDEN 0xEE -#define TWL4030_LED_LEDEN_LEDAON (1 << 0) -#define TWL4030_LED_LEDEN_LEDBON (1 << 1) -#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4) -#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5) +#define TWL4030_LED_LEDEN_LEDAON BIT(0) +#define TWL4030_LED_LEDEN_LEDBON BIT(1) +#define TWL4030_LED_LEDEN_LEDAPWM BIT(4) +#define TWL4030_LED_LEDEN_LEDBPWM BIT(5) /* Keypad */ #define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2 @@ -438,13 +438,13 @@ #define TWL4030_KEYPAD_KEYP_EDR 0xE8 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9 -#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6) -#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5) -#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4) -#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3) -#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2) -#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1) -#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0) +#define TWL4030_KEYPAD_CTRL_KBD_ON BIT(6) +#define TWL4030_KEYPAD_CTRL_RP_EN BIT(5) +#define TWL4030_KEYPAD_CTRL_TOLE_EN BIT(4) +#define TWL4030_KEYPAD_CTRL_TOE_EN BIT(3) +#define TWL4030_KEYPAD_CTRL_LK_EN BIT(2) +#define TWL4030_KEYPAD_CTRL_SOFTMODEN BIT(1) +#define TWL4030_KEYPAD_CTRL_SOFT_NRST BIT(0) /* USB */ #define TWL4030_USB_VENDOR_ID_LO 0x00 diff --git a/include/twl6030.h b/include/twl6030.h index 7898699..416d78b 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -25,9 +25,9 @@ #define VUSB_CFG_STATE 0xA2 #define MISC1 0xE4 -#define VAC_MEAS (1 << 2) -#define VBAT_MEAS (1 << 1) -#define BB_MEAS (1 << 0) +#define VAC_MEAS BIT(2) +#define VBAT_MEAS BIT(1) +#define BB_MEAS BIT(0) #define MISC2 0xE5 @@ -60,58 +60,58 @@ #define CHARGERUSB_CIN_LIMIT_500 0x9 #define CHARGERUSB_CIN_LIMIT_NONE 0xF /* CONTROLLER_INT_MASK */ -#define MVAC_FAULT (1 << 6) -#define MAC_EOC (1 << 5) -#define MBAT_REMOVED (1 << 4) -#define MFAULT_WDG (1 << 3) -#define MBAT_TEMP (1 << 2) -#define MVBUS_DET (1 << 1) -#define MVAC_DET (1 << 0) +#define MVAC_FAULT BIT(6) +#define MAC_EOC BIT(5) +#define MBAT_REMOVED BIT(4) +#define MFAULT_WDG BIT(3) +#define MBAT_TEMP BIT(2) +#define MVBUS_DET BIT(1) +#define MVAC_DET BIT(0) /* CHARGERUSB_INT_MASK */ -#define MASK_MCURRENT_TERM (1 << 3) -#define MASK_MCHARGERUSB_STAT (1 << 2) -#define MASK_MCHARGERUSB_THMREG (1 << 1) -#define MASK_MCHARGERUSB_FAULT (1 << 0) +#define MASK_MCURRENT_TERM BIT(3) +#define MASK_MCHARGERUSB_STAT BIT(2) +#define MASK_MCHARGERUSB_THMREG BIT(1) +#define MASK_MCHARGERUSB_FAULT BIT(0) /* CHARGERUSB_VOREG */ #define CHARGERUSB_VOREG_3P52 0x01 #define CHARGERUSB_VOREG_4P0 0x19 #define CHARGERUSB_VOREG_4P2 0x23 #define CHARGERUSB_VOREG_4P76 0x3F /* CHARGERUSB_CTRL1 */ -#define SUSPEND_BOOT (1 << 7) -#define OPA_MODE (1 << 6) -#define HZ_MODE (1 << 5) -#define TERM (1 << 4) +#define SUSPEND_BOOT BIT(7) +#define OPA_MODE BIT(6) +#define HZ_MODE BIT(5) +#define TERM BIT(4) /* CHARGERUSB_CTRL2 */ #define CHARGERUSB_CTRL2_VITERM_50 (0 << 5) -#define CHARGERUSB_CTRL2_VITERM_100 (1 << 5) +#define CHARGERUSB_CTRL2_VITERM_100 BIT(5) #define CHARGERUSB_CTRL2_VITERM_150 (2 << 5) #define CHARGERUSB_CTRL2_VITERM_400 (7 << 5) /* CONTROLLER_CTRL1 */ -#define CONTROLLER_CTRL1_EN_CHARGER (1 << 4) -#define CONTROLLER_CTRL1_SEL_CHARGER (1 << 3) +#define CONTROLLER_CTRL1_EN_CHARGER BIT(4) +#define CONTROLLER_CTRL1_SEL_CHARGER BIT(3) /* CONTROLLER_STAT1 */ -#define CHRG_EXTCHRG_STATZ (1 << 7) -#define CHRG_DET_N (1 << 5) -#define VAC_DET (1 << 3) -#define VBUS_DET (1 << 2) +#define CHRG_EXTCHRG_STATZ BIT(7) +#define CHRG_DET_N BIT(5) +#define VAC_DET BIT(3) +#define VBUS_DET BIT(2) #define FG_REG_10 0xCA #define FG_REG_11 0xCB #define TOGGLE1 0x90 -#define FGS (1 << 5) -#define FGR (1 << 4) -#define GPADCS (1 << 1) -#define GPADCR (1 << 0) +#define FGS BIT(5) +#define FGR BIT(4) +#define GPADCS BIT(1) +#define GPADCR BIT(0) #define CTRL_P2 0x34 -#define CTRL_P2_SP2 (1 << 2) -#define CTRL_P2_EOCP2 (1 << 1) -#define CTRL_P2_BUSY (1 << 0) +#define CTRL_P2_SP2 BIT(2) +#define CTRL_P2_EOCP2 BIT(1) +#define CTRL_P2_BUSY BIT(0) #define TWL6032_CTRL_P1 0x36 -#define CTRL_P1_SP1 (1 << 3) +#define CTRL_P1_SP1 BIT(3) #define GPCH0_LSB 0x57 #define GPCH0_MSB 0x58 @@ -127,8 +127,8 @@ #define TWL6030_GPADC_CTRL 0x2e #define TWL6032_GPADC_CTRL2 0x2f -#define GPADC_CTRL2_CH18_SCALER_EN (1 << 2) -#define GPADC_CTRL_SCALER_DIV4 (1 << 3) +#define GPADC_CTRL2_CH18_SCALER_EN BIT(2) +#define GPADC_CTRL_SCALER_DIV4 BIT(3) #define TWL6030_VBAT_MULT 40 * 1000 #define TWL6032_VBAT_MULT 25 * 1000 diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index e9349b5..da9581f 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -23,45 +23,45 @@ #define PORT_PTS_UTMI (0 << 30) #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) -#define PORT_PTS_PTW (1 << 28) -#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ -#define PORT_PTS_PHCD (1 << 23) -#define PORT_PP (1 << 12) -#define PORT_PR (1 << 8) +#define PORT_PTS_PTW BIT(28) +#define PORT_PFSC BIT(24) /* Defined on Page 39-44 of the mpc5151 ERM */ +#define PORT_PTS_PHCD BIT(23) +#define PORT_PP BIT(12) +#define PORT_PR BIT(8) /* USBMODE Register bits */ #define CM_IDLE (0 << 0) -#define CM_RESERVED (1 << 0) +#define CM_RESERVED BIT(0) #define CM_DEVICE (2 << 0) #define CM_HOST (3 << 0) -#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ +#define ES_BE BIT(2) /* Big Endian Select, default is LE */ #define USBMODE_RESERVED_2 (0 << 2) -#define SLOM (1 << 3) -#define SDIS (1 << 4) +#define SLOM BIT(3) +#define SDIS BIT(4) /* CONTROL Register bits */ -#define ULPI_INT_EN (1 << 0) -#define WU_INT_EN (1 << 1) -#define USB_EN (1 << 2) -#define LSF_EN (1 << 3) -#define KEEP_OTG_ON (1 << 4) -#define OTG_PORT (1 << 5) +#define ULPI_INT_EN BIT(0) +#define WU_INT_EN BIT(1) +#define USB_EN BIT(2) +#define LSF_EN BIT(3) +#define KEEP_OTG_ON BIT(4) +#define OTG_PORT BIT(5) #define REFSEL_12MHZ (0 << 6) -#define REFSEL_16MHZ (1 << 6) +#define REFSEL_16MHZ BIT(6) #define REFSEL_48MHZ (2 << 6) -#define PLL_RESET (1 << 8) -#define UTMI_PHY_EN (1 << 9) +#define PLL_RESET BIT(8) +#define UTMI_PHY_EN BIT(9) #define PHY_CLK_SEL_UTMI (0 << 10) -#define PHY_CLK_SEL_ULPI (1 << 10) +#define PHY_CLK_SEL_ULPI BIT(10) #define CLKIN_SEL_USB_CLK (0 << 11) -#define CLKIN_SEL_USB_CLK2 (1 << 11) +#define CLKIN_SEL_USB_CLK2 BIT(11) #define CLKIN_SEL_SYS_CLK (2 << 11) #define CLKIN_SEL_SYS_CLK2 (3 << 11) #define RESERVED_18 (0 << 13) #define RESERVED_17 (0 << 14) #define RESERVED_16 (0 << 15) -#define WU_INT (1 << 16) -#define PHY_CLK_VALID (1 << 17) +#define WU_INT BIT(16) +#define PHY_CLK_VALID BIT(17) #define FSL_SOC_USB_PORTSC2 0x188 @@ -122,19 +122,19 @@ #define FSL_SOC_USB_USBMODE 0x1a8 #define USBGENCTRL 0x200 /* NOTE: big endian */ -#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ -#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ -#define GC_PPP (1 << 3) /* Port Power Polarity */ -#define GC_PFP (1 << 2) /* Power Fault Polarity */ -#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ -#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ +#define GC_WU_INT_CLR BIT(5) /* Wakeup int clear */ +#define GC_ULPI_SEL BIT(4) /* ULPI i/f select (usb0 only)*/ +#define GC_PPP BIT(3) /* Port Power Polarity */ +#define GC_PFP BIT(2) /* Power Fault Polarity */ +#define GC_WU_ULPI_EN BIT(1) /* Wakeup on ULPI event */ +#define GC_WU_IE BIT(1) /* Wakeup interrupt enable */ #define ISIPHYCTRL 0x204 /* NOTE: big endian */ -#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ -#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ -#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ -#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ -#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ +#define PHYCTRL_PHYE BIT(4) /* On-chip UTMI PHY enable */ +#define PHYCTRL_BSENH BIT(3) /* Bit Stuff Enable High */ +#define PHYCTRL_BSEN BIT(2) /* Bit Stuff Enable */ +#define PHYCTRL_LSFE BIT(1) /* Line State Filter Enable */ +#define PHYCTRL_PXE BIT(0) /* PHY oscillator enable */ #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ @@ -254,31 +254,31 @@ struct usb_ehci { */ /* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) +#define MXC_EHCI_PHY_LOW_POWER_SUSPEND BIT(23) +#define MXC_EHCI_FORCE_FS BIT(24) #define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) +#define MXC_EHCI_UTMI_16BIT BIT(28) +#define MXC_EHCI_SERIAL BIT(29) #define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) +#define MXC_EHCI_MODE_PHILIPS BIT(30) #define MXC_EHCI_MODE_ULPI (2 << 30) #define MXC_EHCI_MODE_SERIAL (3 << 30) /* values for flags field */ #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) -#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) +#define MXC_EHCI_INTERFACE_DIFF_BI BIT(0) #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) #define MXC_EHCI_INTERFACE_MASK (0xf) -#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) -#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) -#define MXC_EHCI_TTL_ENABLED (1 << 8) +#define MXC_EHCI_POWER_PINS_ENABLED BIT(5) +#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH BIT(6) +#define MXC_EHCI_OC_PIN_ACTIVE_LOW BIT(7) +#define MXC_EHCI_TTL_ENABLED BIT(8) -#define MXC_EHCI_INTERNAL_PHY (1 << 9) -#define MXC_EHCI_IPPUE_DOWN (1 << 10) -#define MXC_EHCI_IPPUE_UP (1 << 11) +#define MXC_EHCI_INTERNAL_PHY BIT(9) +#define MXC_EHCI_IPPUE_DOWN BIT(10) +#define MXC_EHCI_IPPUE_UP BIT(11) int usb_phy_mode(int port); /* Board-specific initialization */ diff --git a/include/usb/fotg210.h b/include/usb/fotg210.h index b83e8f5..f727113 100644 --- a/include/usb/fotg210.h +++ b/include/usb/fotg210.h @@ -67,102 +67,102 @@ struct fotg210_regs { }; /* Miscellaneous Register */ -#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */ +#define MISCR_SUSPEND BIT(6) /* Put transceiver in suspend mode */ #define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ #define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ #define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ /* OTG Control Status Register */ #define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */ -#define OTGCSR_SPD_LOW (1 << 22) +#define OTGCSR_SPD_LOW BIT(22) #define OTGCSR_SPD_FULL (0 << 22) #define OTGCSR_SPD_MASK (3 << 22) #define OTGCSR_SPD_SHIFT 22 #define OTGCSR_SPD(x) (((x) >> 22) & 0x03) #define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */ -#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */ +#define OTGCSR_DEV_B BIT(21) /* Acts as B-device */ #define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */ -#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */ -#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */ -#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */ -#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */ -#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */ -#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/ +#define OTGCSR_ROLE_D BIT(20) /* Acts as Device */ +#define OTGCSR_A_VBUS_VLD BIT(19) /* A-device VBUS Valid */ +#define OTGCSR_A_SESS_VLD BIT(18) /* A-device Session Valid */ +#define OTGCSR_B_SESS_VLD BIT(17) /* B-device Session Valid */ +#define OTGCSR_B_SESS_END BIT(16) /* B-device Session End */ +#define OTGCSR_HFT_LONG BIT(11) /* HDISCON noise filter = 270 us*/ #define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/ -#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/ +#define OTGCSR_VFT_LONG BIT(10) /* VBUS noise filter = 472 us*/ #define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/ -#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/ +#define OTGCSR_IDFT_LONG BIT(9) /* ID noise filter = 4 ms*/ #define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/ #define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */ -#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */ -#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */ -#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */ -#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */ -#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */ -#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */ -#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */ -#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */ +#define OTGCSR_A_SRPR_DATA BIT(8) /* A-device: SRP responds to DATA-LINE */ +#define OTGCSR_A_SRP_EN BIT(7) /* A-device SRP detection enabled */ +#define OTGCSR_A_HNP BIT(6) /* Set role=A-device with HNP enabled */ +#define OTGCSR_A_BUSDROP BIT(5) /* A-device drop bus (power-down) */ +#define OTGCSR_A_BUSREQ BIT(4) /* A-device request bus */ +#define OTGCSR_B_VBUS_DISC BIT(2) /* B-device discharges VBUS */ +#define OTGCSR_B_HNP BIT(1) /* B-device enable HNP */ +#define OTGCSR_B_BUSREQ BIT(0) /* B-device request bus */ /* OTG Interrupt Status Register */ -#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGISR_OVD (1 << 10) /* over-current detected */ -#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */ +#define OTGISR_APRM BIT(12) /* Mini-A plug removed */ +#define OTGISR_BPRM BIT(11) /* Mini-B plug removed */ +#define OTGISR_OVD BIT(10) /* over-current detected */ +#define OTGISR_IDCHG BIT(9) /* ID(A/B) changed */ +#define OTGISR_RLCHG BIT(8) /* Role(Host/Device) changed */ +#define OTGISR_BSESSEND BIT(6) /* B-device Session End */ +#define OTGISR_AVBUSERR BIT(5) /* A-device VBUS Error */ +#define OTGISR_ASRP BIT(4) /* A-device SRP detected */ +#define OTGISR_BSRP BIT(0) /* B-device SRP complete */ /* OTG Interrupt Enable Register */ -#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGIER_OVD (1 << 10) /* over-current detected */ -#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */ +#define OTGIER_APRM BIT(12) /* Mini-A plug removed */ +#define OTGIER_BPRM BIT(11) /* Mini-B plug removed */ +#define OTGIER_OVD BIT(10) /* over-current detected */ +#define OTGIER_IDCHG BIT(9) /* ID(A/B) changed */ +#define OTGIER_RLCHG BIT(8) /* Role(Host/Device) changed */ +#define OTGIER_BSESSEND BIT(6) /* B-device Session End */ +#define OTGIER_AVBUSERR BIT(5) /* A-device VBUS Error */ +#define OTGIER_ASRP BIT(4) /* A-device SRP detected */ +#define OTGIER_BSRP BIT(0) /* B-device SRP complete */ /* Global Interrupt Status Register (W1C) */ -#define ISR_HOST (1 << 2) /* USB Host interrupt */ -#define ISR_OTG (1 << 1) /* USB OTG interrupt */ -#define ISR_DEV (1 << 0) /* USB Device interrupt */ +#define ISR_HOST BIT(2) /* USB Host interrupt */ +#define ISR_OTG BIT(1) /* USB OTG interrupt */ +#define ISR_DEV BIT(0) /* USB Device interrupt */ #define ISR_MASK 0x07 /* Global Interrupt Mask Register */ -#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */ +#define IMR_IRQLH BIT(3) /* Interrupt triggered at level-high */ #define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */ -#define IMR_HOST (1 << 2) /* USB Host interrupt */ -#define IMR_OTG (1 << 1) /* USB OTG interrupt */ -#define IMR_DEV (1 << 0) /* USB Device interrupt */ +#define IMR_HOST BIT(2) /* USB Host interrupt */ +#define IMR_OTG BIT(1) /* USB OTG interrupt */ +#define IMR_DEV BIT(0) /* USB Device interrupt */ #define IMR_MASK 0x0f /* Device Control Register */ -#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */ -#define DEVCTRL_HS (1 << 6) /* High Speed Mode */ +#define DEVCTRL_FS_FORCED BIT(9) /* Forced to be Full-Speed Mode */ +#define DEVCTRL_HS BIT(6) /* High Speed Mode */ #define DEVCTRL_FS (0 << 6) /* Full Speed Mode */ -#define DEVCTRL_EN (1 << 5) /* Chip Enable */ -#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */ -#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */ -#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */ -#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */ -#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */ +#define DEVCTRL_EN BIT(5) /* Chip Enable */ +#define DEVCTRL_RESET BIT(4) /* Chip Software Reset */ +#define DEVCTRL_SUSPEND BIT(3) /* Enter Suspend Mode */ +#define DEVCTRL_GIRQ_EN BIT(2) /* Global Interrupt Enabled */ +#define DEVCTRL_HALFSPD BIT(1) /* Half speed mode for FPGA test */ +#define DEVCTRL_RWAKEUP BIT(0) /* Enable remote wake-up */ /* Device Address Register */ -#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */ +#define DEVADDR_CONF BIT(7) /* SET_CONFIGURATION has been executed */ #define DEVADDR_ADDR(x) ((x) & 0x7f) #define DEVADDR_ADDR_MASK 0x7f /* Device Test Register */ -#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */ -#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */ -#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */ -#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */ -#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */ -#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */ -#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */ +#define DEVTEST_NOSOF BIT(6) /* Do not generate SOF */ +#define DEVTEST_TST_MODE BIT(5) /* Enter Test Mode */ +#define DEVTEST_TST_NOTS BIT(4) /* Do not toggle sequence */ +#define DEVTEST_TST_NOCRC BIT(3) /* Do not append CRC */ +#define DEVTEST_TST_CLREA BIT(2) /* Clear External Side Address */ +#define DEVTEST_TST_CXLP BIT(1) /* EP0 loopback test */ +#define DEVTEST_TST_CLRFF BIT(0) /* Clear FIFO */ /* SOF Frame Number Register */ #define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */ @@ -172,43 +172,43 @@ struct fotg210_regs { #define SOFMTR_TMR(x) ((x) & 0xffff) /* PHY Test Mode Selector Register */ -#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */ -#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */ -#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */ -#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */ -#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */ +#define PHYTMSR_TST_PKT BIT(4) /* Packet send test */ +#define PHYTMSR_TST_SE0NAK BIT(3) /* High-Speed quiescent state */ +#define PHYTMSR_TST_KSTA BIT(2) /* High-Speed K state */ +#define PHYTMSR_TST_JSTA BIT(1) /* High-Speed J state */ +#define PHYTMSR_UNPLUG BIT(0) /* Enable soft-detachment */ /* CX FIFO Register */ #define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */ #define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */ -#define CXFIFO_FIFOE_FIFO0 (1 << 8) -#define CXFIFO_FIFOE_FIFO1 (1 << 9) -#define CXFIFO_FIFOE_FIFO2 (1 << 10) -#define CXFIFO_FIFOE_FIFO3 (1 << 11) +#define CXFIFO_FIFOE_FIFO0 BIT(8) +#define CXFIFO_FIFOE_FIFO1 BIT(9) +#define CXFIFO_FIFOE_FIFO2 BIT(10) +#define CXFIFO_FIFOE_FIFO3 BIT(11) #define CXFIFO_FIFOE_MASK (0x0f << 8) -#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */ -#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */ -#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */ -#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */ -#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */ -#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */ +#define CXFIFO_CXFIFOE BIT(5) /* CX FIFO empty */ +#define CXFIFO_CXFIFOF BIT(4) /* CX FIFO full */ +#define CXFIFO_CXFIFOCLR BIT(3) /* CX FIFO clear */ +#define CXFIFO_CXSTALL BIT(2) /* CX Stall */ +#define CXFIFO_TSTPKTFIN BIT(1) /* Test packet data transfer finished */ +#define CXFIFO_CXFIN BIT(0) /* CX data transfer finished */ /* IDLE Counter Register */ #define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */ /* Group Interrupt Mask(Disable) Register */ -#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */ -#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */ -#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */ +#define GIMR_GRP2 BIT(2) /* Disable interrupt group 2 */ +#define GIMR_GRP1 BIT(1) /* Disable interrupt group 1 */ +#define GIMR_GRP0 BIT(0) /* Disable interrupt group 0 */ #define GIMR_MASK 0x07 /* Group Interrupt Mask(Disable) Register 0 (CX) */ -#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ +#define GIMR0_CXABORT BIT(5) /* CX command abort interrupt */ +#define GIMR0_CXERR BIT(4) /* CX command error interrupt */ +#define GIMR0_CXEND BIT(3) /* CX command end interrupt */ +#define GIMR0_CXOUT BIT(2) /* EP0-OUT packet interrupt */ +#define GIMR0_CXIN BIT(1) /* EP0-IN packet interrupt */ +#define GIMR0_CXSETUP BIT(0) /* EP0-SETUP packet interrupt */ #define GIMR0_MASK 0x3f /* Group Interrupt Mask(Disable) Register 1 (FIFO) */ @@ -220,31 +220,31 @@ struct fotg210_regs { #define GIMR1_MASK 0xf00ff /* Group Interrupt Mask(Disable) Register 2 (Device) */ -#define GIMR2_WAKEUP (1 << 10) /* Device waked up */ -#define GIMR2_IDLE (1 << 9) /* Device idle */ -#define GIMR2_DMAERR (1 << 8) /* DMA error */ -#define GIMR2_DMAFIN (1 << 7) /* DMA finished */ -#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GIMR2_RESET (1 << 0) /* Reset Interrupt */ +#define GIMR2_WAKEUP BIT(10) /* Device waked up */ +#define GIMR2_IDLE BIT(9) /* Device idle */ +#define GIMR2_DMAERR BIT(8) /* DMA error */ +#define GIMR2_DMAFIN BIT(7) /* DMA finished */ +#define GIMR2_ZLPRX BIT(6) /* Zero-Length-Packet Rx Interrupt */ +#define GIMR2_ZLPTX BIT(5) /* Zero-Length-Packet Tx Interrupt */ +#define GIMR2_ISOCABT BIT(4) /* ISOC Abort Interrupt */ +#define GIMR2_ISOCERR BIT(3) /* ISOC Error Interrupt */ +#define GIMR2_RESUME BIT(2) /* Resume state change Interrupt */ +#define GIMR2_SUSPEND BIT(1) /* Suspend state change Interrupt */ +#define GIMR2_RESET BIT(0) /* Reset Interrupt */ #define GIMR2_MASK 0x7ff /* Group Interrupt Status Register */ -#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */ -#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */ -#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */ +#define GISR_GRP2 BIT(2) /* Interrupt group 2 */ +#define GISR_GRP1 BIT(1) /* Interrupt group 1 */ +#define GISR_GRP0 BIT(0) /* Interrupt group 0 */ /* Group Interrupt Status Register 0 (CX) */ -#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GISR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GISR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ +#define GISR0_CXABORT BIT(5) /* CX command abort interrupt */ +#define GISR0_CXERR BIT(4) /* CX command error interrupt */ +#define GISR0_CXEND BIT(3) /* CX command end interrupt */ +#define GISR0_CXOUT BIT(2) /* EP0-OUT packet interrupt */ +#define GISR0_CXIN BIT(1) /* EP0-IN packet interrupt */ +#define GISR0_CXSETUP BIT(0) /* EP0-SETUP packet interrupt */ /* Group Interrupt Status Register 1 (FIFO) */ #define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */ @@ -253,17 +253,17 @@ struct fotg210_regs { #define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */ /* Group Interrupt Status Register 2 (Device) */ -#define GISR2_WAKEUP (1 << 10) /* Device waked up */ -#define GISR2_IDLE (1 << 9) /* Device idle */ -#define GISR2_DMAERR (1 << 8) /* DMA error */ -#define GISR2_DMAFIN (1 << 7) /* DMA finished */ -#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GISR2_RESET (1 << 0) /* Reset Interrupt */ +#define GISR2_WAKEUP BIT(10) /* Device waked up */ +#define GISR2_IDLE BIT(9) /* Device idle */ +#define GISR2_DMAERR BIT(8) /* DMA error */ +#define GISR2_DMAFIN BIT(7) /* DMA finished */ +#define GISR2_ZLPRX BIT(6) /* Zero-Length-Packet Rx Interrupt */ +#define GISR2_ZLPTX BIT(5) /* Zero-Length-Packet Tx Interrupt */ +#define GISR2_ISOCABT BIT(4) /* ISOC Abort Interrupt */ +#define GISR2_ISOCERR BIT(3) /* ISOC Error Interrupt */ +#define GISR2_RESUME BIT(2) /* Resume state change Interrupt */ +#define GISR2_SUSPEND BIT(1) /* Suspend state change Interrupt */ +#define GISR2_RESET BIT(0) /* Reset Interrupt */ /* Receive Zero-Length-Packet Register */ #define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */ @@ -275,16 +275,16 @@ struct fotg210_regs { #define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */ /* IN Endpoint Register */ -#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */ +#define IEP_SENDZLP BIT(15) /* Send Zero-Length-Packet */ #define IEP_TNRHB(x) (((x) & 0x03) << 13) \ /* Transaction Number for High-Bandwidth EP(ISOC) */ -#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define IEP_STALL (1 << 11) /* Stall */ +#define IEP_RESET BIT(12) /* Reset Toggle Sequence */ +#define IEP_STALL BIT(11) /* Stall */ #define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ /* OUT Endpoint Register */ -#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define OEP_STALL (1 << 11) /* Stall */ +#define OEP_RESET BIT(12) /* Reset Toggle Sequence */ +#define OEP_STALL BIT(11) /* Stall */ #define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ /* Endpoint Map Register (EP1 ~ EP4) */ @@ -315,7 +315,7 @@ struct fotg210_regs { /* FIFO Map Register */ #define FIFOMAP_BIDIR (2 << 4) -#define FIFOMAP_IN (1 << 4) +#define FIFOMAP_IN BIT(4) #define FIFOMAP_OUT (0 << 4) #define FIFOMAP_DIR_MASK 0x30 #define FIFOMAP_EP(x) ((x) & 0x0f) @@ -325,17 +325,17 @@ struct fotg210_regs { #define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) /* FIFO Configuration Register */ -#define FIFOCFG_EN (1 << 5) -#define FIFOCFG_BLKSZ_1024 (1 << 4) +#define FIFOCFG_EN BIT(5) +#define FIFOCFG_BLKSZ_1024 BIT(4) #define FIFOCFG_BLKSZ_512 (0 << 4) #define FIFOCFG_3BLK (2 << 2) -#define FIFOCFG_2BLK (1 << 2) +#define FIFOCFG_2BLK BIT(2) #define FIFOCFG_1BLK (0 << 2) #define FIFOCFG_NBLK_MASK 3 #define FIFOCFG_NBLK_SHIFT 2 #define FIFOCFG_INTR (3 << 0) #define FIFOCFG_BULK (2 << 0) -#define FIFOCFG_ISOC (1 << 0) +#define FIFOCFG_ISOC BIT(0) #define FIFOCFG_RSVD (0 << 0) /* Reserved */ #define FIFOCFG_TYPE_MASK 3 #define FIFOCFG_TYPE_SHIFT 0 @@ -343,21 +343,21 @@ struct fotg210_regs { #define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) /* FIFO Control Status Register */ -#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */ +#define FIFOCSR_RESET BIT(12) /* FIFO Reset */ #define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */ /* DMA Target FIFO Register */ -#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */ +#define DMAFIFO_CX BIT(4) /* DMA FIFO = CX FIFO */ #define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */ /* DMA Control Register */ #define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */ #define DMACTRL_LEN_SHIFT 8 -#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */ -#define DMACTRL_ABORT (1 << 3) /* DMA abort */ -#define DMACTRL_IO2IO (1 << 2) /* IO to IO */ +#define DMACTRL_CLRFF BIT(4) /* Clear FIFO upon DMA abort */ +#define DMACTRL_ABORT BIT(3) /* DMA abort */ +#define DMACTRL_IO2IO BIT(2) /* IO to IO */ #define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */ -#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */ -#define DMACTRL_START (1 << 0) /* DMA start */ +#define DMACTRL_MEM2FIFO BIT(1) /* Memory to FIFO */ +#define DMACTRL_START BIT(0) /* DMA start */ #endif diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h index e2d8553..905bdc2 100644 --- a/include/usb/fusbh200.h +++ b/include/usb/fusbh200.h @@ -25,7 +25,7 @@ struct fusbh200_regs { }; /* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ +#define EASSTR_RUNNING BIT(6) /* Put transceiver in running/resume mode */ #define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ #define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ #define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ @@ -33,28 +33,28 @@ struct fusbh200_regs { /* Bus Monitor Control Status Register */ #define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) +#define BMCSR_SPD_LOW BIT(9) #define BMCSR_SPD_FULL (0 << 9) #define BMCSR_SPD_MASK (3 << 9) #define BMCSR_SPD_SHIFT 9 #define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ +#define BMCSR_VBUS BIT(8) /* VBUS Valid */ +#define BMCSR_VBUS_OFF BIT(4) /* VBUS Off */ #define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ +#define BMCSR_IRQLH BIT(3) /* IRQ triggered at level-high */ #define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ +#define BMCSR_HALFSPD BIT(2) /* Half speed mode for FPGA test */ +#define BMCSR_HFT_LONG BIT(1) /* HDISCON noise filter = 270 us*/ #define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ +#define BMCSR_VFT_LONG BIT(1) /* VBUS noise filter = 472 us*/ #define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ /* Bus Monitor Interrupt Status Register */ /* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ +#define BMISR_DMAERR BIT(4) /* DMA error */ +#define BMISR_DMA BIT(3) /* DMA complete */ +#define BMISR_DEVRM BIT(2) /* device removed */ +#define BMISR_OVD BIT(1) /* over-current detected */ +#define BMISR_VBUSERR BIT(0) /* VBUS error */ #endif diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 7f49a4e..6793084 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -16,7 +16,7 @@ #include #include -#define PHY0_SLEEP (1 << 5) +#define PHY0_SLEEP BIT(5) /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index 99166c4..8815b52 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -21,7 +21,7 @@ #ifndef __USB_ULPI_H__ #define __USB_ULPI_H__ -#define ULPI_ERROR (1 << 8) /* overflow from any register value */ +#define ULPI_ERROR BIT(8) /* overflow from any register value */ #ifndef CONFIG_USB_ULPI_TIMEOUT #define CONFIG_USB_ULPI_TIMEOUT 1000 /* timeout in us */ @@ -240,37 +240,37 @@ struct ulpi_regs { /* Function Control */ #define ULPI_FC_XCVRSEL_MASK (3 << 0) #define ULPI_FC_HIGH_SPEED (0 << 0) -#define ULPI_FC_FULL_SPEED (1 << 0) +#define ULPI_FC_FULL_SPEED BIT(0) #define ULPI_FC_LOW_SPEED (2 << 0) #define ULPI_FC_FS4LS (3 << 0) -#define ULPI_FC_TERMSELECT (1 << 2) +#define ULPI_FC_TERMSELECT BIT(2) #define ULPI_FC_OPMODE_MASK (3 << 3) #define ULPI_FC_OPMODE_NORMAL (0 << 3) -#define ULPI_FC_OPMODE_NONDRIVING (1 << 3) +#define ULPI_FC_OPMODE_NONDRIVING BIT(3) #define ULPI_FC_OPMODE_DISABLE_NRZI (2 << 3) #define ULPI_FC_OPMODE_NOSYNC_NOEOP (3 << 3) -#define ULPI_FC_RESET (1 << 5) -#define ULPI_FC_SUSPENDM (1 << 6) +#define ULPI_FC_RESET BIT(5) +#define ULPI_FC_SUSPENDM BIT(6) /* Interface Control */ -#define ULPI_IFACE_6_PIN_SERIAL_MODE (1 << 0) -#define ULPI_IFACE_3_PIN_SERIAL_MODE (1 << 1) -#define ULPI_IFACE_CARKITMODE (1 << 2) -#define ULPI_IFACE_CLOCKSUSPENDM (1 << 3) -#define ULPI_IFACE_AUTORESUME (1 << 4) -#define ULPI_IFACE_EXTVBUS_COMPLEMENT (1 << 5) -#define ULPI_IFACE_PASSTHRU (1 << 6) -#define ULPI_IFACE_PROTECT_IFC_DISABLE (1 << 7) +#define ULPI_IFACE_6_PIN_SERIAL_MODE BIT(0) +#define ULPI_IFACE_3_PIN_SERIAL_MODE BIT(1) +#define ULPI_IFACE_CARKITMODE BIT(2) +#define ULPI_IFACE_CLOCKSUSPENDM BIT(3) +#define ULPI_IFACE_AUTORESUME BIT(4) +#define ULPI_IFACE_EXTVBUS_COMPLEMENT BIT(5) +#define ULPI_IFACE_PASSTHRU BIT(6) +#define ULPI_IFACE_PROTECT_IFC_DISABLE BIT(7) /* OTG Control */ -#define ULPI_OTG_ID_PULLUP (1 << 0) -#define ULPI_OTG_DP_PULLDOWN (1 << 1) -#define ULPI_OTG_DM_PULLDOWN (1 << 2) -#define ULPI_OTG_DISCHRGVBUS (1 << 3) -#define ULPI_OTG_CHRGVBUS (1 << 4) -#define ULPI_OTG_DRVVBUS (1 << 5) -#define ULPI_OTG_DRVVBUS_EXT (1 << 6) -#define ULPI_OTG_EXTVBUSIND (1 << 7) +#define ULPI_OTG_ID_PULLUP BIT(0) +#define ULPI_OTG_DP_PULLDOWN BIT(1) +#define ULPI_OTG_DM_PULLDOWN BIT(2) +#define ULPI_OTG_DISCHRGVBUS BIT(3) +#define ULPI_OTG_CHRGVBUS BIT(4) +#define ULPI_OTG_DRVVBUS BIT(5) +#define ULPI_OTG_DRVVBUS_EXT BIT(6) +#define ULPI_OTG_EXTVBUSIND BIT(7) /* * USB Interrupt Enable Rising, @@ -278,42 +278,42 @@ struct ulpi_regs { * USB Interrupt Status and * USB Interrupt Latch */ -#define ULPI_INT_HOST_DISCONNECT (1 << 0) -#define ULPI_INT_VBUS_VALID (1 << 1) -#define ULPI_INT_SESS_VALID (1 << 2) -#define ULPI_INT_SESS_END (1 << 3) -#define ULPI_INT_IDGRD (1 << 4) +#define ULPI_INT_HOST_DISCONNECT BIT(0) +#define ULPI_INT_VBUS_VALID BIT(1) +#define ULPI_INT_SESS_VALID BIT(2) +#define ULPI_INT_SESS_END BIT(3) +#define ULPI_INT_IDGRD BIT(4) /* Debug */ -#define ULPI_DEBUG_LINESTATE0 (1 << 0) -#define ULPI_DEBUG_LINESTATE1 (1 << 1) +#define ULPI_DEBUG_LINESTATE0 BIT(0) +#define ULPI_DEBUG_LINESTATE1 BIT(1) /* Carkit Control */ -#define ULPI_CARKIT_CTRL_CARKITPWR (1 << 0) -#define ULPI_CARKIT_CTRL_IDGNDDRV (1 << 1) -#define ULPI_CARKIT_CTRL_TXDEN (1 << 2) -#define ULPI_CARKIT_CTRL_RXDEN (1 << 3) -#define ULPI_CARKIT_CTRL_SPKLEFTEN (1 << 4) -#define ULPI_CARKIT_CTRL_SPKRIGHTEN (1 << 5) -#define ULPI_CARKIT_CTRL_MICEN (1 << 6) +#define ULPI_CARKIT_CTRL_CARKITPWR BIT(0) +#define ULPI_CARKIT_CTRL_IDGNDDRV BIT(1) +#define ULPI_CARKIT_CTRL_TXDEN BIT(2) +#define ULPI_CARKIT_CTRL_RXDEN BIT(3) +#define ULPI_CARKIT_CTRL_SPKLEFTEN BIT(4) +#define ULPI_CARKIT_CTRL_SPKRIGHTEN BIT(5) +#define ULPI_CARKIT_CTRL_MICEN BIT(6) /* Carkit Interrupt Enable */ -#define ULPI_CARKIT_INT_EN_IDFLOAT_RISE (1 << 0) -#define ULPI_CARKIT_INT_EN_IDFLOAT_FALL (1 << 1) -#define ULPI_CARKIT_INT_EN_CARINTDET (1 << 2) -#define ULPI_CARKIT_INT_EN_DP_RISE (1 << 3) -#define ULPI_CARKIT_INT_EN_DP_FALL (1 << 4) +#define ULPI_CARKIT_INT_EN_IDFLOAT_RISE BIT(0) +#define ULPI_CARKIT_INT_EN_IDFLOAT_FALL BIT(1) +#define ULPI_CARKIT_INT_EN_CARINTDET BIT(2) +#define ULPI_CARKIT_INT_EN_DP_RISE BIT(3) +#define ULPI_CARKIT_INT_EN_DP_FALL BIT(4) /* Carkit Interrupt Status and Latch */ -#define ULPI_CARKIT_INT_IDFLOAT (1 << 0) -#define ULPI_CARKIT_INT_CARINTDET (1 << 1) -#define ULPI_CARKIT_INT_DP (1 << 2) +#define ULPI_CARKIT_INT_IDFLOAT BIT(0) +#define ULPI_CARKIT_INT_CARINTDET BIT(1) +#define ULPI_CARKIT_INT_DP BIT(2) /* Carkit Pulse Control*/ -#define ULPI_CARKIT_PLS_CTRL_TXPLSEN (1 << 0) -#define ULPI_CARKIT_PLS_CTRL_RXPLSEN (1 << 1) -#define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2) -#define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3) +#define ULPI_CARKIT_PLS_CTRL_TXPLSEN BIT(0) +#define ULPI_CARKIT_PLS_CTRL_RXPLSEN BIT(1) +#define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN BIT(2) +#define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN BIT(3) #endif /* __USB_ULPI_H__ */ diff --git a/include/zfs/spa.h b/include/zfs/spa.h index eb54d90..d625442 100644 --- a/include/zfs/spa.h +++ b/include/zfs/spa.h @@ -53,7 +53,7 @@ /* * Size of block to hold the configuration data (a packed nvlist) */ -#define SPA_CONFIG_BLOCKSIZE (1 << 14) +#define SPA_CONFIG_BLOCKSIZE BIT(14) /* * The DVA size encodings for LSIZE and PSIZE support blocks up to 32MB. diff --git a/lib/lzma/LzmaDec.c b/lib/lzma/LzmaDec.c index 4f45f80..51f5388 100644 --- a/lib/lzma/LzmaDec.c +++ b/lib/lzma/LzmaDec.c @@ -34,7 +34,7 @@ /* #define _LZMA_SIZE_OPT */ #ifdef _LZMA_SIZE_OPT -#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) +#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, BIT(6), i) #else #define TREE_6_DECODE(probs, i) \ { i = 1; \ @@ -116,7 +116,7 @@ StopCompilingDueBUG #endif -#define LZMA_DIC_MIN (1 << 12) +#define LZMA_DIC_MIN BIT(12) /* First LZMA-symbol is always decoded. And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization diff --git a/lib/lzma/Types.h b/lib/lzma/Types.h index 8afcba5..d86e191 100644 --- a/lib/lzma/Types.h +++ b/lib/lzma/Types.h @@ -169,7 +169,7 @@ SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); -#define LookToRead_BUF_SIZE (1 << 14) +#define LookToRead_BUF_SIZE BIT(14) typedef struct { diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d512fa5..aaef844 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -481,7 +481,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) *vstart = CONFIG_SYS_SDRAM_BASE; *size = (gd->ram_size >= 256 << 20 ? - 256 << 20 : gd->ram_size) - (1 << 20); + 256 << 20 : gd->ram_size) - BIT(20); /* Limit area to be tested with the board info struct */ if ((*vstart) + (*size) > (ulong)bd) diff --git a/tools/ifdtool.c b/tools/ifdtool.c index 590ccc9..4798b3a 100644 --- a/tools/ifdtool.c +++ b/tools/ifdtool.c @@ -201,7 +201,7 @@ static void dump_fcba(struct fcba_t *fcba) printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", - (fcba->flcomp & (1 << 30)) ? "" : "not "); + (fcba->flcomp & BIT(30)) ? "" : "not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); @@ -209,7 +209,7 @@ static void dump_fcba(struct fcba_t *fcba) printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); printf("\n Fast Read Support: %ssupported", - (fcba->flcomp & (1 << 20)) ? "" : "not "); + (fcba->flcomp & BIT(20)) ? "" : "not "); printf("\n Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 17) & 7); printf("\n Component 2 Density: "); @@ -248,26 +248,26 @@ static const char *get_enabled(int flag) static void decode_flmstr(uint32_t flmstr) { printf(" Platform Data Region Write Access: %s\n", - get_enabled(flmstr & (1 << 28))); + get_enabled(flmstr & BIT(28))); printf(" GbE Region Write Access: %s\n", - get_enabled(flmstr & (1 << 27))); + get_enabled(flmstr & BIT(27))); printf(" Intel ME Region Write Access: %s\n", - get_enabled(flmstr & (1 << 26))); + get_enabled(flmstr & BIT(26))); printf(" Host CPU/BIOS Region Write Access: %s\n", - get_enabled(flmstr & (1 << 25))); + get_enabled(flmstr & BIT(25))); printf(" Flash Descriptor Write Access: %s\n", - get_enabled(flmstr & (1 << 24))); + get_enabled(flmstr & BIT(24))); printf(" Platform Data Region Read Access: %s\n", - get_enabled(flmstr & (1 << 20))); + get_enabled(flmstr & BIT(20))); printf(" GbE Region Read Access: %s\n", - get_enabled(flmstr & (1 << 19))); + get_enabled(flmstr & BIT(19))); printf(" Intel ME Region Read Access: %s\n", - get_enabled(flmstr & (1 << 18))); + get_enabled(flmstr & BIT(18))); printf(" Host CPU/BIOS Region Read Access: %s\n", - get_enabled(flmstr & (1 << 17))); + get_enabled(flmstr & BIT(17))); printf(" Flash Descriptor Read Access: %s\n", - get_enabled(flmstr & (1 << 16))); + get_enabled(flmstr & BIT(16))); printf(" Requester ID: 0x%04x\n\n", flmstr & 0xffff); @@ -308,11 +308,11 @@ static void dump_vscc(uint32_t vscc) printf(" Lower Erase Opcode: 0x%02x\n", vscc >> 24); printf(" Lower Write Enable on Write Status: 0x%02x\n", - vscc & (1 << 20) ? 0x06 : 0x50); + vscc & BIT(20) ? 0x06 : 0x50); printf(" Lower Write Status Required: %s\n", - vscc & (1 << 19) ? "Yes" : "No"); + vscc & BIT(19) ? "Yes" : "No"); printf(" Lower Write Granularity: %d bytes\n", - vscc & (1 << 18) ? 64 : 1); + vscc & BIT(18) ? 64 : 1); printf(" Lower Block / Sector Erase Size: "); switch ((vscc >> 16) & 0x3) { case 0: @@ -332,11 +332,11 @@ static void dump_vscc(uint32_t vscc) printf(" Upper Erase Opcode: 0x%02x\n", (vscc >> 8) & 0xff); printf(" Upper Write Enable on Write Status: 0x%02x\n", - vscc & (1 << 4) ? 0x06 : 0x50); + vscc & BIT(4) ? 0x06 : 0x50); printf(" Upper Write Status Required: %s\n", - vscc & (1 << 3) ? "Yes" : "No"); + vscc & BIT(3) ? "Yes" : "No"); printf(" Upper Write Granularity: %d bytes\n", - vscc & (1 << 2) ? 64 : 1); + vscc & BIT(2) ? 64 : 1); printf(" Upper Block / Sector Erase Size: "); switch (vscc & 0x3) { case 0: @@ -555,7 +555,7 @@ static void set_em100_mode(char *image, int size) struct fcba_t *fcba; fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); - fcba->flcomp &= ~(1 << 30); + fcba->flcomp &= ~BIT(30); set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ); } diff --git a/tools/mxsimage.c b/tools/mxsimage.c index 98fc644..c6f7fd1 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -37,8 +37,8 @@ #define SB_HAB_DCD_WRITE 0xccUL #define SB_HAB_DCD_CHECK 0xcfUL #define SB_HAB_DCD_NOOP 0xc0UL -#define SB_HAB_DCD_MASK_BIT (1 << 3) -#define SB_HAB_DCD_SET_BIT (1 << 4) +#define SB_HAB_DCD_MASK_BIT BIT(3) +#define SB_HAB_DCD_SET_BIT BIT(4) /* Addr.n = Value.n */ #define SB_DCD_WRITE \ diff --git a/tools/mxsimage.h b/tools/mxsimage.h index 88f72eb..75e796a 100644 --- a/tools/mxsimage.h +++ b/tools/mxsimage.h @@ -82,7 +82,7 @@ struct sb_boot_image_header { #define SB_VERSION_MINOR 1 /* Enable to HTLLC boot report. */ -#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0) +#define SB_IMAGE_FLAG_DISPLAY_PROGRESS BIT(0) #define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS struct sb_key_dictionary_key { @@ -133,7 +133,7 @@ struct sb_sections_header { uint32_t section_flags; }; -#define SB_SECTION_FLAG_BOOTABLE (1 << 0) +#define SB_SECTION_FLAG_BOOTABLE BIT(0) struct sb_command { struct {