diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index d576d31..54baa42 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -53,8 +53,8 @@ static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
 }
 
 /* Bits for the status register */
-#define STAT_WIP	(1 << 0)
-#define STAT_WEL	(1 << 1)
+#define STAT_WIP	BIT(0)
+#define STAT_WEL	BIT(1)
 
 /* Assume all SPI flashes have 3 byte addresses since they do atm */
 #define SF_ADDR_LEN	3
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 58007de..d273d30 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -92,13 +92,13 @@ enum {
 #endif
 
 /* Common status */
-#define STATUS_WIP			(1 << 0)
-#define STATUS_QEB_WINSPAN		(1 << 1)
-#define STATUS_QEB_MXIC			(1 << 6)
-#define STATUS_PEC			(1 << 7)
+#define STATUS_WIP			BIT(0)
+#define STATUS_QEB_WINSPAN		BIT(1)
+#define STATUS_QEB_MXIC			BIT(6)
+#define STATUS_PEC			BIT(7)
 
 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD			(1 << 7) /* SR write protect */
+#define STATUS_SRWD			BIT(7) /* SR write protect */
 #endif
 
 /* Flash timeout values */
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index a4d03d9..2302117 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -29,19 +29,19 @@ struct altera_spi_regs {
 	u32	slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK	(1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK	(1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK	(1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK	(1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK	(1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK		(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK	(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK	(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK	(1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK	(1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK	(1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK	(1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK	BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK	BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK	BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK	BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK	BIT(7)
+#define ALTERA_SPI_STATUS_E_MSK		BIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK	BIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK	BIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK	BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK	BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK	BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK	BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
 
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 1538a23..5b892d2 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -15,19 +15,19 @@
 #define ATMEL_SPI_VERSION		0x00fc
 
 /* Bits in CR */
-#define ATMEL_SPI_CR_SPIEN		(1 << 0)
-#define ATMEL_SPI_CR_SPIDIS		(1 << 1)
-#define ATMEL_SPI_CR_SWRST		(1 << 7)
-#define ATMEL_SPI_CR_LASTXFER		(1 << 24)
+#define ATMEL_SPI_CR_SPIEN		BIT(0)
+#define ATMEL_SPI_CR_SPIDIS		BIT(1)
+#define ATMEL_SPI_CR_SWRST		BIT(7)
+#define ATMEL_SPI_CR_LASTXFER		BIT(24)
 
 /* Bits in MR */
-#define ATMEL_SPI_MR_MSTR		(1 << 0)
-#define ATMEL_SPI_MR_PS			(1 << 1)
-#define ATMEL_SPI_MR_PCSDEC		(1 << 2)
-#define ATMEL_SPI_MR_FDIV		(1 << 3)
-#define ATMEL_SPI_MR_MODFDIS		(1 << 4)
-#define ATMEL_SPI_MR_WDRBT		(1 << 5)
-#define ATMEL_SPI_MR_LLB		(1 << 7)
+#define ATMEL_SPI_MR_MSTR		BIT(0)
+#define ATMEL_SPI_MR_PS			BIT(1)
+#define ATMEL_SPI_MR_PCSDEC		BIT(2)
+#define ATMEL_SPI_MR_FDIV		BIT(3)
+#define ATMEL_SPI_MR_MODFDIS		BIT(4)
+#define ATMEL_SPI_MR_WDRBT		BIT(5)
+#define ATMEL_SPI_MR_LLB		BIT(7)
 #define ATMEL_SPI_MR_PCS(x)		(((x) & 15) << 16)
 #define ATMEL_SPI_MR_DLYBCS(x)		((x) << 24)
 
@@ -38,25 +38,25 @@
 /* Bits in TDR */
 #define ATMEL_SPI_TDR_TD(x)		(x)
 #define ATMEL_SPI_TDR_PCS(x)		((x) << 16)
-#define ATMEL_SPI_TDR_LASTXFER		(1 << 24)
+#define ATMEL_SPI_TDR_LASTXFER		BIT(24)
 
 /* Bits in SR/IER/IDR/IMR */
-#define ATMEL_SPI_SR_RDRF		(1 << 0)
-#define ATMEL_SPI_SR_TDRE		(1 << 1)
-#define ATMEL_SPI_SR_MODF		(1 << 2)
-#define ATMEL_SPI_SR_OVRES		(1 << 3)
-#define ATMEL_SPI_SR_ENDRX		(1 << 4)
-#define ATMEL_SPI_SR_ENDTX		(1 << 5)
-#define ATMEL_SPI_SR_RXBUFF		(1 << 6)
-#define ATMEL_SPI_SR_TXBUFE		(1 << 7)
-#define ATMEL_SPI_SR_NSSR		(1 << 8)
-#define ATMEL_SPI_SR_TXEMPTY		(1 << 9)
-#define ATMEL_SPI_SR_SPIENS		(1 << 16)
+#define ATMEL_SPI_SR_RDRF		BIT(0)
+#define ATMEL_SPI_SR_TDRE		BIT(1)
+#define ATMEL_SPI_SR_MODF		BIT(2)
+#define ATMEL_SPI_SR_OVRES		BIT(3)
+#define ATMEL_SPI_SR_ENDRX		BIT(4)
+#define ATMEL_SPI_SR_ENDTX		BIT(5)
+#define ATMEL_SPI_SR_RXBUFF		BIT(6)
+#define ATMEL_SPI_SR_TXBUFE		BIT(7)
+#define ATMEL_SPI_SR_NSSR		BIT(8)
+#define ATMEL_SPI_SR_TXEMPTY		BIT(9)
+#define ATMEL_SPI_SR_SPIENS		BIT(16)
 
 /* Bits in CSRx */
-#define ATMEL_SPI_CSRx_CPOL		(1 << 0)
-#define ATMEL_SPI_CSRx_NCPHA		(1 << 1)
-#define ATMEL_SPI_CSRx_CSAAT		(1 << 3)
+#define ATMEL_SPI_CSRx_CPOL		BIT(0)
+#define ATMEL_SPI_CSRx_NCPHA		BIT(1)
+#define ATMEL_SPI_CSRx_CSAAT		BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x)		((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x)		((x) << 8)
 #define ATMEL_SPI_CSRx_SCBR_MAX		0xff
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
index eba01d1..8359d76 100644
--- a/drivers/spi/bfin_spi6xx.c
+++ b/drivers/spi/bfin_spi6xx.c
@@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
 		ssel = bfin_read32(&bss->regs->ssel);
 		ssel |= 1 << slave->cs;
 		if (bss->cs_pol)
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		else
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		bfin_write32(&bss->regs->ssel, ssel);
 	}
 
@@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 		u32 ssel;
 		ssel = bfin_read32(&bss->regs->ssel);
 		if (bss->cs_pol)
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		else
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		/* deassert cs */
 		bfin_write32(&bss->regs->ssel, ssel);
 		SSYNC();
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 00a115f..ff375e5 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -64,10 +64,10 @@
 #define	CQSPI_REG_CONFIG			0x00
 #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
 #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
-#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
-#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
-#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
-#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
+#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
+#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
+#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
+#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31
@@ -128,18 +128,18 @@
 #define	CQSPI_REG_IRQMASK			0x44
 
 #define	CQSPI_REG_INDIRECTRD			0x60
-#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
 #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
 #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
 
 #define	CQSPI_REG_CMDCTRL			0x90
-#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 << 0)
-#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
+#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
+#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
 #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
 #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
 #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
@@ -155,10 +155,10 @@
 #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
 
 #define	CQSPI_REG_INDIRECTWR			0x70
-#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
 #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0a036cc..0bd4f88 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
-#define BIT(x)			(1 << (x))
-
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK	0x1
 #define SPIGCR0_SPIRST_MASK	0x0
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 8f5c0fc..18f9786 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK				0x7f		/* cover 7 bits */
-#define SR_BUSY				(1 << 0)
-#define SR_TF_NOT_FULL			(1 << 1)
-#define SR_TF_EMPT			(1 << 2)
-#define SR_RF_NOT_EMPT			(1 << 3)
-#define SR_RF_FULL			(1 << 4)
-#define SR_TX_ERR			(1 << 5)
-#define SR_DCOL				(1 << 6)
+#define SR_BUSY				BIT(0)
+#define SR_TF_NOT_FULL			BIT(1)
+#define SR_TF_EMPT			BIT(2)
+#define SR_RF_NOT_EMPT			BIT(3)
+#define SR_RF_FULL			BIT(4)
+#define SR_TX_ERR			BIT(5)
+#define SR_DCOL				BIT(6)
 
 #define RX_TIMEOUT			1000		/* timeout in ms */
 
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index a46d8c1..0382eca 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 		writel(0, &regs->swap_cfg);
 	}
 
-	assert(count && count < (1 << 16));
+	assert(count && count < BIT(16));
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
 
@@ -343,7 +343,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	 */
 	bytelen = bitlen / 8;
 	for (upto = 0; !ret && upto < bytelen; upto += todo) {
-		todo = min(bytelen - upto, (1 << 16) - 4);
+		todo = min(bytelen - upto, BIT(16) - 4);
 		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
 		if (ret)
 			break;
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 6476f91..924a730 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* idle data value */
 #define DSPI_IDLE_VAL			0x0
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 375dc07..b1586d1 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM		4
 #define ESPI_FIFO_WIDTH_BIT	32
 
-#define ESPI_EV_RNE		(1 << 9)
-#define ESPI_EV_TNF		(1 << 8)
-#define ESPI_EV_DON		(1 << 14)
-#define ESPI_EV_TXE		(1 << 15)
+#define ESPI_EV_RNE		BIT(9)
+#define ESPI_EV_TNF		BIT(8)
+#define ESPI_EV_DON		BIT(14)
+#define ESPI_EV_TXE		BIT(15)
 #define ESPI_EV_RFCNT_SHIFT	24
 #define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN		(1 << 31)	/* Enable interface */
+#define ESPI_MODE_EN		BIT(31)	/* Enable interface */
 #define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)	((x) << 0)	/* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)		((x) << 30)
 #define ESPI_COM_TRANLEN(x)	((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH	(1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK	(1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST	(1 << 29)
-#define ESPI_CSMODE_DIV16		(1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH	BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK	BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST	BIT(29)
+#define ESPI_CSMODE_DIV16		BIT(28)
 #define ESPI_CSMODE_PM(x)		((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW	(1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW	BIT(20)
 #define ESPI_CSMODE_LEN(x)		((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)		((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)		((x) << 8)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 868df5f..e1a0ec9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ	50000000
@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 	/* Enable the module again (enable the DDR too) */
 	reg |= QSPI_MCR_DDR_EN_MASK;
 	/* Enable bit 29 for imx6sx */
-	reg |= (1 << 29);
+	reg |= BIT(29);
 
 	qspi_write32(priv->flags, &regs->mcr, reg);
 }
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 50354fd..feffb08 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -689,13 +689,13 @@ static int ich_spi_probe(struct udevice *bus)
 
 		ich9_spi = priv->base;
 		bios_cntl = ich_readb(priv, ich9_spi->bcr);
-		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
 		ich_writeb(priv, bios_cntl, ich9_spi->bcr);
 	} else {
 		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
 		if (plat->ich_version == 9)
-			bios_cntl &= ~(1 << 5);
+			bios_cntl &= ~BIT(5);
 		pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
 	}
 
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 0d59c36..00cbcbf 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -55,7 +55,7 @@ void spi_init(void)
 	 * some registers
 	 */
 	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
-	spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+	spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
 							     (16.67MHz typ.) */
 	spi->event = 0xffffffff;	/* Clear all SPI events */
 	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index ab7cd84..269a5c7 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -52,40 +52,40 @@ struct mcspi {
 
 /* per-register bitmasks */
 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	(1 << 0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
 
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
 
-#define OMAP3_MCSPI_MODULCTRL_SINGLE	(1 << 0)
-#define OMAP3_MCSPI_MODULCTRL_MS	(1 << 2)
-#define OMAP3_MCSPI_MODULCTRL_STEST	(1 << 3)
+#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
 
-#define OMAP3_MCSPI_CHCONF_PHA		(1 << 0)
-#define OMAP3_MCSPI_CHCONF_POL		(1 << 1)
+#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
 #define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
-#define OMAP3_MCSPI_CHCONF_EPOL		(1 << 6)
+#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
 #define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
-#define OMAP3_MCSPI_CHCONF_DMAW		(1 << 14)
-#define OMAP3_MCSPI_CHCONF_DMAR		(1 << 15)
-#define OMAP3_MCSPI_CHCONF_DPE0		(1 << 16)
-#define OMAP3_MCSPI_CHCONF_DPE1		(1 << 17)
-#define OMAP3_MCSPI_CHCONF_IS		(1 << 18)
-#define OMAP3_MCSPI_CHCONF_TURBO	(1 << 19)
-#define OMAP3_MCSPI_CHCONF_FORCE	(1 << 20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS		(1 << 0)
-#define OMAP3_MCSPI_CHSTAT_TXS		(1 << 1)
-#define OMAP3_MCSPI_CHSTAT_EOT		(1 << 2)
-
-#define OMAP3_MCSPI_CHCTRL_EN		(1 << 0)
+#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
 #define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
 
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	(1 << 0)
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
 
 struct omap3_spi_slave {
 	struct spi_slave slave;
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 77ede6b..7209e1d 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -21,19 +21,19 @@
 #define SPPCR_IO3FV	0x04
 #define SPPCR_IO2FV	0x02
 #define SPPCR_IO1FV	0x01
-#define SPBDCR_RXBC0	(1 << 0)
-#define SPCMD_SCKDEN	(1 << 15)
-#define SPCMD_SLNDEN	(1 << 14)
-#define SPCMD_SPNDEN	(1 << 13)
-#define SPCMD_SSLKP	(1 << 7)
-#define SPCMD_BRDV0	(1 << 2)
+#define SPBDCR_RXBC0	BIT(0)
+#define SPCMD_SCKDEN	BIT(15)
+#define SPCMD_SLNDEN	BIT(14)
+#define SPCMD_SPNDEN	BIT(13)
+#define SPCMD_SSLKP	BIT(7)
+#define SPCMD_BRDV0	BIT(2)
 #define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
 			SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
 #define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
-#define SPBFCR_TXRST	(1 << 7)
-#define SPBFCR_RXRST	(1 << 6)
+#define SPBFCR_TXRST	BIT(7)
+#define SPBFCR_RXRST	BIT(6)
 
 /* SH QSPI register set */
 struct sh_qspi_regs {
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 53ff9ea..5ae326b 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -33,54 +33,54 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND1 */
-#define SPI_CMD1_GO			(1 << 31)
-#define SPI_CMD1_M_S			(1 << 30)
+#define SPI_CMD1_GO			BIT(31)
+#define SPI_CMD1_M_S			BIT(30)
 #define SPI_CMD1_MODE_MASK		0x3
 #define SPI_CMD1_MODE_SHIFT		28
 #define SPI_CMD1_CS_SEL_MASK		0x3
 #define SPI_CMD1_CS_SEL_SHIFT		26
-#define SPI_CMD1_CS_POL_INACTIVE3	(1 << 25)
-#define SPI_CMD1_CS_POL_INACTIVE2	(1 << 24)
-#define SPI_CMD1_CS_POL_INACTIVE1	(1 << 23)
-#define SPI_CMD1_CS_POL_INACTIVE0	(1 << 22)
-#define SPI_CMD1_CS_SW_HW		(1 << 21)
-#define SPI_CMD1_CS_SW_VAL		(1 << 20)
+#define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
+#define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)
+#define SPI_CMD1_CS_POL_INACTIVE1	BIT(23)
+#define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
+#define SPI_CMD1_CS_SW_HW		BIT(21)
+#define SPI_CMD1_CS_SW_VAL		BIT(20)
 #define SPI_CMD1_IDLE_SDA_MASK		0x3
 #define SPI_CMD1_IDLE_SDA_SHIFT		18
-#define SPI_CMD1_BIDIR			(1 << 17)
-#define SPI_CMD1_LSBI_FE		(1 << 16)
-#define SPI_CMD1_LSBY_FE		(1 << 15)
-#define SPI_CMD1_BOTH_EN_BIT		(1 << 14)
-#define SPI_CMD1_BOTH_EN_BYTE		(1 << 13)
-#define SPI_CMD1_RX_EN			(1 << 12)
-#define SPI_CMD1_TX_EN			(1 << 11)
-#define SPI_CMD1_PACKED			(1 << 5)
+#define SPI_CMD1_BIDIR			BIT(17)
+#define SPI_CMD1_LSBI_FE		BIT(16)
+#define SPI_CMD1_LSBY_FE		BIT(15)
+#define SPI_CMD1_BOTH_EN_BIT		BIT(14)
+#define SPI_CMD1_BOTH_EN_BYTE		BIT(13)
+#define SPI_CMD1_RX_EN			BIT(12)
+#define SPI_CMD1_TX_EN			BIT(11)
+#define SPI_CMD1_PACKED			BIT(5)
 #define SPI_CMD1_BIT_LEN_MASK		0x1F
 #define SPI_CMD1_BIT_LEN_SHIFT		0
 
 /* COMMAND2 */
-#define SPI_CMD2_TX_CLK_TAP_DELAY	(1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
-#define SPI_CMD2_RX_CLK_TAP_DELAY	(1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
 
 /* TRANSFER STATUS */
-#define SPI_XFER_STS_RDY		(1 << 30)
+#define SPI_XFER_STS_RDY		BIT(30)
 
 /* FIFO STATUS */
-#define SPI_FIFO_STS_CS_INACTIVE	(1 << 31)
-#define SPI_FIFO_STS_FRAME_END		(1 << 30)
-#define SPI_FIFO_STS_RX_FIFO_FLUSH	(1 << 15)
-#define SPI_FIFO_STS_TX_FIFO_FLUSH	(1 << 14)
-#define SPI_FIFO_STS_ERR		(1 << 8)
-#define SPI_FIFO_STS_TX_FIFO_OVF	(1 << 7)
-#define SPI_FIFO_STS_TX_FIFO_UNR	(1 << 6)
-#define SPI_FIFO_STS_RX_FIFO_OVF	(1 << 5)
-#define SPI_FIFO_STS_RX_FIFO_UNR	(1 << 4)
-#define SPI_FIFO_STS_TX_FIFO_FULL	(1 << 3)
-#define SPI_FIFO_STS_TX_FIFO_EMPTY	(1 << 2)
-#define SPI_FIFO_STS_RX_FIFO_FULL	(1 << 1)
-#define SPI_FIFO_STS_RX_FIFO_EMPTY	(1 << 0)
+#define SPI_FIFO_STS_CS_INACTIVE	BIT(31)
+#define SPI_FIFO_STS_FRAME_END		BIT(30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH	BIT(15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH	BIT(14)
+#define SPI_FIFO_STS_ERR		BIT(8)
+#define SPI_FIFO_STS_TX_FIFO_OVF	BIT(7)
+#define SPI_FIFO_STS_TX_FIFO_UNR	BIT(6)
+#define SPI_FIFO_STS_RX_FIFO_OVF	BIT(5)
+#define SPI_FIFO_STS_RX_FIFO_UNR	BIT(4)
+#define SPI_FIFO_STS_TX_FIFO_FULL	BIT(3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY	BIT(2)
+#define SPI_FIFO_STS_RX_FIFO_FULL	BIT(1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY	BIT(0)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 78c74cd..5959ffd 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -20,37 +20,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_GO			BIT(30)
 #define SPI_CMD_ACTIVE_SCLK_SHIFT	26
 #define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_CK_SDA			BIT(21)
 #define SPI_CMD_ACTIVE_SDA_SHIFT	18
 #define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL			(1 << 16)
-#define SPI_CMD_TXEN			(1 << 15)
-#define SPI_CMD_RXEN			(1 << 14)
-#define SPI_CMD_CS_VAL			(1 << 13)
-#define SPI_CMD_CS_SOFT			(1 << 12)
-#define SPI_CMD_CS_DELAY		(1 << 9)
-#define SPI_CMD_CS3_EN			(1 << 8)
-#define SPI_CMD_CS2_EN			(1 << 7)
-#define SPI_CMD_CS1_EN			(1 << 6)
-#define SPI_CMD_CS0_EN			(1 << 5)
-#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_CS_POL			BIT(16)
+#define SPI_CMD_TXEN			BIT(15)
+#define SPI_CMD_RXEN			BIT(14)
+#define SPI_CMD_CS_VAL			BIT(13)
+#define SPI_CMD_CS_SOFT			BIT(12)
+#define SPI_CMD_CS_DELAY		BIT(9)
+#define SPI_CMD_CS3_EN			BIT(8)
+#define SPI_CMD_CS2_EN			BIT(7)
+#define SPI_CMD_CS1_EN			BIT(6)
+#define SPI_CMD_CS0_EN			BIT(5)
+#define SPI_CMD_BIT_LENGTH		BIT(4)
 #define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
 
-#define SPI_STAT_BSY			(1 << 31)
-#define SPI_STAT_RDY			(1 << 30)
-#define SPI_STAT_RXF_FLUSH		(1 << 29)
-#define SPI_STAT_TXF_FLUSH		(1 << 28)
-#define SPI_STAT_RXF_UNR		(1 << 27)
-#define SPI_STAT_TXF_OVF		(1 << 26)
-#define SPI_STAT_RXF_EMPTY		(1 << 25)
-#define SPI_STAT_RXF_FULL		(1 << 24)
-#define SPI_STAT_TXF_EMPTY		(1 << 23)
-#define SPI_STAT_TXF_FULL		(1 << 22)
-#define SPI_STAT_SEL_TXRX_N		(1 << 16)
-#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+#define SPI_STAT_BSY			BIT(31)
+#define SPI_STAT_RDY			BIT(30)
+#define SPI_STAT_RXF_FLUSH		BIT(29)
+#define SPI_STAT_TXF_FLUSH		BIT(28)
+#define SPI_STAT_RXF_UNR		BIT(27)
+#define SPI_STAT_TXF_OVF		BIT(26)
+#define SPI_STAT_RXF_EMPTY		BIT(25)
+#define SPI_STAT_RXF_FULL		BIT(24)
+#define SPI_STAT_TXF_EMPTY		BIT(23)
+#define SPI_STAT_TXF_FULL		BIT(22)
+#define SPI_STAT_SEL_TXRX_N		BIT(16)
+#define SPI_STAT_CUR_BLKCNT		BIT(15)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 597d6ad..8d96f29 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -33,40 +33,40 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND */
-#define SLINK_CMD_ENB			(1 << 31)
-#define SLINK_CMD_GO			(1 << 30)
-#define SLINK_CMD_M_S			(1 << 28)
-#define SLINK_CMD_CK_SDA		(1 << 21)
-#define SLINK_CMD_CS_POL		(1 << 13)
-#define SLINK_CMD_CS_VAL		(1 << 12)
-#define SLINK_CMD_CS_SOFT		(1 << 11)
-#define SLINK_CMD_BIT_LENGTH		(1 << 4)
+#define SLINK_CMD_ENB			BIT(31)
+#define SLINK_CMD_GO			BIT(30)
+#define SLINK_CMD_M_S			BIT(28)
+#define SLINK_CMD_CK_SDA		BIT(21)
+#define SLINK_CMD_CS_POL		BIT(13)
+#define SLINK_CMD_CS_VAL		BIT(12)
+#define SLINK_CMD_CS_SOFT		BIT(11)
+#define SLINK_CMD_BIT_LENGTH		BIT(4)
 #define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
 /* COMMAND2 */
-#define SLINK_CMD2_TXEN			(1 << 30)
-#define SLINK_CMD2_RXEN			(1 << 31)
-#define SLINK_CMD2_SS_EN		(1 << 18)
+#define SLINK_CMD2_TXEN			BIT(30)
+#define SLINK_CMD2_RXEN			BIT(31)
+#define SLINK_CMD2_SS_EN		BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT		18
 #define SLINK_CMD2_SS_EN_MASK		0x000C0000
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN	(1 << 17)
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN	BIT(17)
 /* STATUS */
-#define SLINK_STAT_BSY			(1 << 31)
-#define SLINK_STAT_RDY			(1 << 30)
-#define SLINK_STAT_ERR			(1 << 29)
-#define SLINK_STAT_RXF_FLUSH		(1 << 27)
-#define SLINK_STAT_TXF_FLUSH		(1 << 26)
-#define SLINK_STAT_RXF_OVF		(1 << 25)
-#define SLINK_STAT_TXF_UNR		(1 << 24)
-#define SLINK_STAT_RXF_EMPTY		(1 << 23)
-#define SLINK_STAT_RXF_FULL		(1 << 22)
-#define SLINK_STAT_TXF_EMPTY		(1 << 21)
-#define SLINK_STAT_TXF_FULL		(1 << 20)
-#define SLINK_STAT_TXF_OVF		(1 << 19)
-#define SLINK_STAT_RXF_UNR		(1 << 18)
-#define SLINK_STAT_CUR_BLKCNT		(1 << 15)
+#define SLINK_STAT_BSY			BIT(31)
+#define SLINK_STAT_RDY			BIT(30)
+#define SLINK_STAT_ERR			BIT(29)
+#define SLINK_STAT_RXF_FLUSH		BIT(27)
+#define SLINK_STAT_TXF_FLUSH		BIT(26)
+#define SLINK_STAT_RXF_OVF		BIT(25)
+#define SLINK_STAT_TXF_UNR		BIT(24)
+#define SLINK_STAT_RXF_EMPTY		BIT(23)
+#define SLINK_STAT_RXF_FULL		BIT(22)
+#define SLINK_STAT_TXF_EMPTY		BIT(21)
+#define SLINK_STAT_TXF_FULL		BIT(20)
+#define SLINK_STAT_TXF_OVF		BIT(19)
+#define SLINK_STAT_RXF_UNR		BIT(18)
+#define SLINK_STAT_CUR_BLKCNT		BIT(15)
 /* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT	(1 << 16)
-#define SLINK_STAT2_TXF_FULL_CNT	(1 << 0)
+#define SLINK_STAT2_RXF_FULL_CNT	BIT(16)
+#define SLINK_STAT2_TXF_FULL_CNT	BIT(0)
 
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 3356c0f..ca3acfd 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -18,13 +18,13 @@
 #define QSPI_TIMEOUT                    2000000
 #define QSPI_FCLK                       192000000
 /* clock control */
-#define QSPI_CLK_EN                     (1 << 31)
+#define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
 /* command */
 #define QSPI_EN_CS(n)                   (n << 28)
 #define QSPI_WLEN(n)                    ((n-1) << 19)
-#define QSPI_3_PIN                      (1 << 18)
-#define QSPI_RD_SNGL                    (1 << 16)
+#define QSPI_3_PIN                      BIT(18)
+#define QSPI_RD_SNGL                    BIT(16)
 #define QSPI_WR_SNGL                    (2 << 16)
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)
@@ -34,8 +34,8 @@
 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)                   (1 << (n*8))
 /* status */
-#define QSPI_WC                         (1 << 1)
-#define QSPI_BUSY                       (1 << 0)
+#define QSPI_WC                         BIT(1)
+#define QSPI_BUSY                       BIT(0)
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 650e494..3803c4c 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -28,24 +28,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST		(1 << 9)
-#define SPICR_MASTER_INHIBIT	(1 << 8)
-#define SPICR_MANUAL_SS		(1 << 7)
-#define SPICR_RXFIFO_RESEST	(1 << 6)
-#define SPICR_TXFIFO_RESEST	(1 << 5)
-#define SPICR_CPHA		(1 << 4)
-#define SPICR_CPOL		(1 << 3)
-#define SPICR_MASTER_MODE	(1 << 2)
-#define SPICR_SPE		(1 << 1)
-#define SPICR_LOOP		(1 << 0)
+#define SPICR_LSB_FIRST		BIT(9)
+#define SPICR_MASTER_INHIBIT	BIT(8)
+#define SPICR_MANUAL_SS		BIT(7)
+#define SPICR_RXFIFO_RESEST	BIT(6)
+#define SPICR_TXFIFO_RESEST	BIT(5)
+#define SPICR_CPHA		BIT(4)
+#define SPICR_CPOL		BIT(3)
+#define SPICR_MASTER_MODE	BIT(2)
+#define SPICR_SPE		BIT(1)
+#define SPICR_LOOP		BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT	(1 << 5)
-#define SPISR_MODF		(1 << 4)
-#define SPISR_TX_FULL		(1 << 3)
-#define SPISR_TX_EMPTY		(1 << 2)
-#define SPISR_RX_FULL		(1 << 1)
-#define SPISR_RX_EMPTY		(1 << 0)
+#define SPISR_SLAVE_MODE_SELECT	BIT(5)
+#define SPISR_MODF		BIT(4)
+#define SPISR_TX_FULL		BIT(3)
+#define SPISR_TX_EMPTY		BIT(2)
+#define SPISR_RX_FULL		BIT(1)
+#define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK	(0xff << 0)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index e9129da..ff1ec6a 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -14,17 +14,17 @@
 #include <asm/arch/hardware.h>
 
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
 #define ZYNQ_SPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_FIFO_DEPTH		128
 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index e724310..c098c9a 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -104,6 +104,7 @@ static inline unsigned int generic_hweight8(unsigned int w)
 	return (res & 0x0F) + ((res >> 4) & 0x0F);
 }
 
+#define BIT(nr)			(1UL << (nr))
 #define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
 #define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
 
diff --git a/include/spi.h b/include/spi.h
index 44abe68..8049b25 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,26 +30,26 @@
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE         (1 << 5)
+#define SPI_XFER_U_PAGE         BIT(5)
 
 /* SPI TX operation modes */
-#define SPI_OPM_TX_QPP		(1 << 0)
-#define SPI_OPM_TX_BP		(1 << 1)
+#define SPI_OPM_TX_QPP		BIT(0)
+#define SPI_OPM_TX_BP		BIT(1)
 
 /* SPI RX operation modes */
-#define SPI_OPM_RX_AS		(1 << 0)
-#define SPI_OPM_RX_AF		(1 << 1)
-#define SPI_OPM_RX_DOUT		(1 << 2)
-#define SPI_OPM_RX_DIO		(1 << 3)
-#define SPI_OPM_RX_QOF		(1 << 4)
-#define SPI_OPM_RX_QIOF		(1 << 5)
+#define SPI_OPM_RX_AS		BIT(0)
+#define SPI_OPM_RX_AF		BIT(1)
+#define SPI_OPM_RX_DOUT		BIT(2)
+#define SPI_OPM_RX_DIO		BIT(3)
+#define SPI_OPM_RX_QOF		BIT(4)
+#define SPI_OPM_RX_QIOF		BIT(5)
 #define SPI_OPM_RX_EXTN		(SPI_OPM_RX_AS | SPI_OPM_RX_AF | \
 				SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO | \
 				SPI_OPM_RX_QOF | SPI_OPM_RX_QIOF)
 
 /* SPI bus connection options - see enum spi_dual_flash */
-#define SPI_CONN_DUAL_SHARED		(1 << 0)
-#define SPI_CONN_DUAL_SEPARATED         (1 << 1)
+#define SPI_CONN_DUAL_SHARED		BIT(0)
+#define SPI_CONN_DUAL_SEPARATED         BIT(1)
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
