From patchwork Wed Apr 8 19:54:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 459452 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 22CCC14016A for ; Thu, 9 Apr 2015 05:56:39 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C57FEA74A9; Wed, 8 Apr 2015 21:56:10 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id H7hq4JesmKj1; Wed, 8 Apr 2015 21:56:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A2929A74B2; Wed, 8 Apr 2015 21:55:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87C0EA7483 for ; Wed, 8 Apr 2015 21:55:35 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id B4IjqbPaxOrV for ; Wed, 8 Apr 2015 21:55:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f53.google.com (mail-pa0-f53.google.com [209.85.220.53]) by theia.denx.de (Postfix) with ESMTPS id 34D3AA744E for ; Wed, 8 Apr 2015 21:55:20 +0200 (CEST) Received: by pabtp1 with SMTP id tp1so19083733pab.2 for ; Wed, 08 Apr 2015 12:55:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Laml77DIMjdMiK2d00382hxBOX2auZmoKju9Rtw/ivc=; b=GwiV5e343qAOgW9YWGgmFtHhcYtp3vc/BjTvKpEcRpOFiCx9mXzQ/gAaqv0vJqESf4 h9UYM1esWVlWXTel45MUXo01Cvp524Fmp7qSb5aieKP5pSHcP9xmyDf6uqpk26349pcY b0/tpf2wUO6wULrrCNQ8OY6Y3hEL6oFirpQ7sTm00gm4Nn0HATT0PZ602957VZ0VlZg0 LwyCxfXPx86kMapmp4V4XfbdULC4xu++8C2zbzs/B17e3o49O+EkNdXU4XPO/JdQOg7+ NPlqlT0wq2l4c4ywcGfBWY1sTic/QegY1w050+N9qDngDzhWK/qV0zrCNZvJ07Eq7bC4 YQ2w== X-Gm-Message-State: ALoCoQkoc2MKE2KxVxJhg+0vvxpkI92wdixz2Ij0qpeqsGNhDMxlIrjXj9KL+W+clM6FkoSZAo9f X-Received: by 10.66.241.36 with SMTP id wf4mr49953680pac.8.1428522919422; Wed, 08 Apr 2015 12:55:19 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id u5sm12130208pdu.57.2015.04.08.12.55.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Apr 2015 12:55:18 -0700 (PDT) From: Tim Harvey To: Stefano Babic Date: Wed, 8 Apr 2015 12:54:38 -0700 Message-Id: <1428522904-8111-9-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428522904-8111-1-git-send-email-tharvey@gateworks.com> References: <1428522904-8111-1-git-send-email-tharvey@gateworks.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 08/34] imx: ventana: set LTC3676 PMIC to appropriate values per datasheet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The IMX6 Datasheets specifies that when the IMX6 LDO is enabled (internal Anatop LDO's for VDD_ARM, VDD_SOC, and VDD_xPU) you need to provide 1350mV on VDD_ARM_IN and VDD_SOC_IN for IMX6Q@1GHz (Automotive) and 1275mV for IMX6DL@800MHz (Industrial). While we are still about 50mV shy on the IMX6Q operating at 1GHz we set it to the max we can and leave it up to the kernel to implement a regulator driver for the LTC3676 and put the LDO's in bypass mode which allows us to drop the voltages by 125mV respectively. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 42 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 51925d1..d93dd56 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1025,22 +1025,32 @@ int power_init_board(void) p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { puts("PMIC: LTC3676\n"); - /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ - if (is_cpu_type(MXC_CPU_MX6Q)) { - /* mask PGOOD during SW1 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB1B, reg); - /* set SW1 (VDD_SOC) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB1A, reg); - - /* mask PGOOD during SW3 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB3B, reg); - /*set SW3 (VDD_ARM) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB3A, reg); - } + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); } }