From patchwork Wed Apr 8 19:54:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 459473 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3F3361401E7 for ; Thu, 9 Apr 2015 06:00:03 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8D04BA74A9; Wed, 8 Apr 2015 21:58:03 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 01eGV-rxGtNR; Wed, 8 Apr 2015 21:58:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0759BA7570; Wed, 8 Apr 2015 21:56:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 57A94A7499 for ; Wed, 8 Apr 2015 21:56:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ts8QNQvMeFWN for ; Wed, 8 Apr 2015 21:56:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by theia.denx.de (Postfix) with ESMTPS id 2A8A3A74BB for ; Wed, 8 Apr 2015 21:55:35 +0200 (CEST) Received: by pacyx8 with SMTP id yx8so124366665pac.1 for ; Wed, 08 Apr 2015 12:55:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e6pXdkTtk81plG7wpTAcTg7wIhaVUO40Siieb5sSxGk=; b=PObo+61hOw/WVoOp2fi/Y2itNlGGuM5MqW1IQI8ei7kM4BI1Sta4UbEK0O25yDxwuM COkpC2XTg6+LnyfyklSuX3QdfqoKrabmfwOdZiBYFTpguTXUdl3Ke6gwQRHavMZkHV6D CgvSd99RZ4yUEglGsgA1iJWyYqEkA2uNxVMoN1AFKz61+jQA6K7PmUhEQUG3OWToBKu1 1Mnzk6ncKmS7NRIQy6Xmv47H7cBcyjotP8JZwx9eFh6FfrWR7TAyJHPXY9WiAJ/v0PAT M3+d4ScZ7lCgzXIVtdqV3GXYMhga3+eWgr4V5TBWQTEdbCpo5JSJfFArq5Lkqvf6nyrc R4ew== X-Gm-Message-State: ALoCoQlQiN76+tQuRVaa+ZEzk6jNtrQ5994atulUVCu1SXaZbcY40vg72/Qo1sKOfOOoRu/ks74u X-Received: by 10.68.229.138 with SMTP id sq10mr48329033pbc.136.1428522934339; Wed, 08 Apr 2015 12:55:34 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id u5sm12130208pdu.57.2015.04.08.12.55.33 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Apr 2015 12:55:33 -0700 (PDT) From: Tim Harvey To: Stefano Babic Date: Wed, 8 Apr 2015 12:54:54 -0700 Message-Id: <1428522904-8111-25-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428522904-8111-1-git-send-email-tharvey@gateworks.com> References: <1428522904-8111-1-git-send-email-tharvey@gateworks.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 24/34] imx: ventana: updated 16bit DDR calibration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Updated 16bit DDR calibration using values obtained from running the i.MX6 DDR Stress Test tool over a set of boards over full operationg temperature. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 668e112..baa2c6e 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -233,13 +233,15 @@ static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x001B0016, + .p0_mpwldectrl1 = 0x000C000E, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4324033A, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40403438, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40403D36, }; static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { @@ -255,13 +257,15 @@ static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x00420043, + .p0_mpwldectrl1 = 0x0016001A, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4238023B, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40404849, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40402E2F, }; static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {