From patchwork Mon Feb 23 19:16:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 442646 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1A046140119 for ; Tue, 24 Feb 2015 06:17:03 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6AE6D4A039; Mon, 23 Feb 2015 20:17:01 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 75cNELAP5pIS; Mon, 23 Feb 2015 20:17:01 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB2FD4A02F; Mon, 23 Feb 2015 20:17:00 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF4524A02F for ; Mon, 23 Feb 2015 20:16:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dzaP896Z1nGg for ; Mon, 23 Feb 2015 20:16:58 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gagarine.paulk.fr (gagarine.paulk.fr [109.190.93.129]) by theia.denx.de (Postfix) with ESMTPS id 88E9D4A02E for ; Mon, 23 Feb 2015 20:16:55 +0100 (CET) Received: by gagarine.paulk.fr (Postfix, from userid 65534) id B5110209D0; Mon, 23 Feb 2015 20:16:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on gagarine.paulk.fr X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from localhost.localdomain (collins [192.168.1.129]) by gagarine.paulk.fr (Postfix) with ESMTP id DDBED2094E; Mon, 23 Feb 2015 20:16:52 +0100 (CET) From: Paul Kocialkowski To: u-boot@lists.denx.de Date: Mon, 23 Feb 2015 20:16:44 +0100 Message-Id: <1424719005-18838-1-git-send-email-contact@paulk.fr> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424704032.2434.9.camel@collins> References: <1424704032.2434.9.camel@collins> Cc: Tom Rini Subject: [U-Boot] [PATCH] omap3: Variant and revision checks for ARM Cortex-A8 errata workarounds X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Not every version and revision of the Cortex-A8 ARM core requires the same errata workarounds. In addition, enabling those requires to have similar workarounds enabled in the kernel or it will cause numerous segmentation faults. This enables those workarounds when they are needed, according to what is done in Linux. Follow-up to the discussion from July 2013: http://lists.denx.de/pipermail/u-boot/2013-July/158377.html Signed-off-by: Paul Kocialkowski Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap3/board.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7..3c198fc 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -431,14 +431,31 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) static void omap3_setup_aux_cr(void) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 + u32 id, revision, variant; + u32 bits = 0; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (id)); + + variant = (id & 0xf00000) >> 20; + revision = id & 0x0f; + + /* + * Workaround for Cortex-A8 errata #454179, #430973 + * Set IBE bit + * Set Disable Branch Size Mispredicts (DBSM) bit + */ + if (variant < 2) + bits |= (1 << 6) | (1 << 7); + + /* + * Workaround for Cortex-A8 erratum #621766 * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 */ - omap3_update_aux_cr_secure(0xE0, 0); + if (variant == 2 && revision == 0) + bits |= (1 << 5); + + if (bits != 0) + omap3_update_aux_cr_secure(bits, 0); } #ifndef CONFIG_SYS_L2CACHE_OFF