From patchwork Tue Feb 10 06:13:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 438207 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4A15A140129 for ; Tue, 10 Feb 2015 17:13:41 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D88424B174; Tue, 10 Feb 2015 07:13:39 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 69EZy2SF4MCD; Tue, 10 Feb 2015 07:13:39 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 662E34A04F; Tue, 10 Feb 2015 07:13:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB50D4A04F for ; Tue, 10 Feb 2015 07:13:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IAQsnZ81iIfw for ; Tue, 10 Feb 2015 07:13:34 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by theia.denx.de (Postfix) with ESMTPS id 3F7644A04E for ; Tue, 10 Feb 2015 07:13:32 +0100 (CET) Received: by mail-pa0-f46.google.com with SMTP id lj1so39002160pab.5 for ; Mon, 09 Feb 2015 22:13:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=80PG69hCngVXN+cmS1PZME4hb6veEoolafx0LQwfC+M=; b=jRtffa440EBmGqSVTxHlRPiPMY09R4A6vtWCSQWDRcU6LeiwovhfHnnTp+T1kO/0cC VvK24KoudGoXENf+dTmKfLzimn4rusVPRIAtcqo7qdvmHpfts0IbLLK0C/xcN4fkSNVe l7QJrk9Lra5tNUzVIlkujwEjXY2SXg14GyF6JD3AG1ZD9sq4HRYdrB/9badKOGrh5VuB W9BE2TE8oSr9fZC/Xnl79OzD6bIC6XksCzsCa+gmnkU7WmmFpHs/Y6zBwjCbCSGsVM4j +K5dJMEIldVHR6xx8ysWXJaM4ryDWLBEXE1GSUhVGlaa1TTFcMSydthBoVPeSXvkgYl7 y3nw== X-Gm-Message-State: ALoCoQm/ND20tAhF5QGidesK6VsReu4UjhziYHQweHdPsD5mR8rZFOb/OB9qwYIl9VQ8HIXiUJPm X-Received: by 10.68.239.102 with SMTP id vr6mr35345997pbc.35.1423548810815; Mon, 09 Feb 2015 22:13:30 -0800 (PST) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id sl5sm18107095pbc.45.2015.02.09.22.13.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Feb 2015 22:13:29 -0800 (PST) From: Nobuhiro Iwamatsu To: u-boot@lists.denx.de, Nobuhiro Iwamatsu Date: Tue, 10 Feb 2015 15:13:19 +0900 Message-Id: <1423548799-24286-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 2.1.3 Cc: Nobuhiro Iwamatsu Subject: [U-Boot] [PATCH] arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" R8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we need to enable SMP bit of Auxiliary Control Register. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index d47546a..fc839ea 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -40,7 +40,7 @@ do_lowlevel_init: and r1, r1, #0x7F00 lsrs r1, r1, #8 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ - beq _exit_init_l2_a15 + beq _enable_actlr_smp /* surpress wfe if ca15 */ tst r4, #4 @@ -64,6 +64,14 @@ do_lowlevel_init: orrne r0, r0, #0x20 /* L2CTLR[5] */ #endif mcrne p15, 1, r0, c9, c0, 2 + + b _exit_init_l2_a15 + +_enable_actlr_smp: /* R8A7794 only (CA7) */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4