From patchwork Wed Oct 29 16:22:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suriyan Ramasami X-Patchwork-Id: 404695 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 561B014008E for ; Thu, 30 Oct 2014 03:23:14 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CBD374B995; Wed, 29 Oct 2014 17:23:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2tzVe1VjCmvM; Wed, 29 Oct 2014 17:23:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 53F0F4B988; Wed, 29 Oct 2014 17:23:12 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A99BB4B984 for ; Wed, 29 Oct 2014 17:23:07 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E13krg8L6pO9 for ; Wed, 29 Oct 2014 17:23:07 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oi0-f49.google.com (mail-oi0-f49.google.com [209.85.218.49]) by theia.denx.de (Postfix) with ESMTPS id 48D1D4B988 for ; Wed, 29 Oct 2014 17:22:59 +0100 (CET) Received: by mail-oi0-f49.google.com with SMTP id u20so2537701oif.36 for ; Wed, 29 Oct 2014 09:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X404D50oObXyyZslDteRn7Nhbw59ES603x7aXcvWCVc=; b=y+J3aVF9/MQY9RX7cNjLiC6ulsrs19InkBnVDmmneGcv4hSfD1KykSvQNqqgEn8Xuf E3oSRJXNvCWklb7+HhBNjiJ2Cr1k2iir+KiE4O3ZWM0Rnt5E571JxFCuWkfrrBk3sIEw d+8PujWwfwN9k21vpzGenD8v7w58EDm96Lg83h597rT2OH5Lc8KKtuzoQAInA9tYiv9A AVzgsHrfKUcXK55CN2DgvOxHeyJ3cTvU7+hDKRE+lseDKjADgVA6UE1Gw/3pFEPmK2+e E1JSxETcw5w4RZPZxyP4lV6ud+mFOuo2z6up9zVaA/UhuktqxjpIhTjhdsGlAcg3LO/x 3qJA== X-Received: by 10.60.102.211 with SMTP id fq19mr9726304oeb.2.1414599778269; Wed, 29 Oct 2014 09:22:58 -0700 (PDT) Received: from suriyanT430.us.oracle.com ([148.87.13.5]) by mx.google.com with ESMTPSA id n2sm1934280oel.17.2014.10.29.09.22.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 29 Oct 2014 09:22:57 -0700 (PDT) From: Suriyan Ramasami To: u-boot@lists.denx.de Date: Wed, 29 Oct 2014 09:22:42 -0700 Message-Id: <1414599763-15861-2-git-send-email-suriyan.r@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414599763-15861-1-git-send-email-suriyan.r@gmail.com> References: <1414599763-15861-1-git-send-email-suriyan.r@gmail.com> Cc: Suriyan Ramasami , Przemyslaw Marczak Subject: [U-Boot] [PATCH v3 2/3] arm: odroid: enable/disable usb host phy for exynos4412 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami --- Changes in v3: * Minkyu - do not mix cpu_is... and proid_is... Changes in v2: * Jaehoon - separate this patch out Changes in v1: * First try arch/arm/cpu/armv7/exynos/power.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 7 +++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index e1ab3d6..1520d64 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable) } } +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + void set_usbhost_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_set_usbhost_phy_ctrl(enable); } static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index e8a98a5..3f97b31 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -210,6 +210,13 @@ struct exynos4_power { unsigned int gps_alive_option; }; +struct exynos4412_power { + unsigned char res1[0x0704]; + unsigned int usbhost_phy_control; + unsigned int hsic1_phy_control; + unsigned int hsic2_phy_control; +}; + struct exynos5_power { unsigned int om_stat; unsigned char res1[0x18];