From patchwork Mon Oct 20 17:52:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suriyan Ramasami X-Patchwork-Id: 401212 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3DD0F140092 for ; Tue, 21 Oct 2014 04:52:41 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9BA44A73EF; Mon, 20 Oct 2014 19:52:39 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id euAiiKe2Fnom; Mon, 20 Oct 2014 19:52:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 04C894B61C; Mon, 20 Oct 2014 19:52:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BD5D24B61C for ; Mon, 20 Oct 2014 19:52:36 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hrl3CsjUrghl for ; Mon, 20 Oct 2014 19:52:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by theia.denx.de (Postfix) with ESMTPS id 5C61B4B5D6 for ; Mon, 20 Oct 2014 19:52:31 +0200 (CEST) Received: by mail-pa0-f48.google.com with SMTP id eu11so5631638pac.7 for ; Mon, 20 Oct 2014 10:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W1p7pYPKico4xSfrVLcsoXRb+nN9ydInHEyZpeEC/KI=; b=RcAUHGaYVRdq+9Wj36BaMeJrIEW6vtP9UHqY+YTx8gHtRsJuM0v0Rt4KKQZubJcbvD PkueGqP8GxJsDlJBwPXzBGaBIp+f/IkorYvsSV944j/YFCuAqVXHdwXlb63c9qwj1Mkx OQ48dP0bJ3ws3ax7nSiMC6lC2pv2occDP8/cl5Eesyj8cZDMqyv4yLGLtcQS0St5/xYQ 4Quz8cblaXF4VfydNndkqKSUw+4DnvTbXtByQ0dZe0pp/f+aRF5WGZEhxpgxaSzHQ7Ms 3FX6L3DfTSZlsEoYyr7RezZoF7BKKYELkh4l4VhursRAVpmQEArVxT0QwHh0Sq96h4aV wSrQ== X-Received: by 10.66.65.206 with SMTP id z14mr29690662pas.46.1413827550485; Mon, 20 Oct 2014 10:52:30 -0700 (PDT) Received: from localhost.localdomain (c-73-189-84-218.hsd1.ca.comcast.net. [73.189.84.218]) by mx.google.com with ESMTPSA id ic3sm9708018pbc.26.2014.10.20.10.52.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Oct 2014 10:52:29 -0700 (PDT) From: Suriyan Ramasami To: u-boot@lists.denx.de Date: Mon, 20 Oct 2014 10:52:02 -0700 Message-Id: <1413827523-8341-2-git-send-email-suriyan.r@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413827523-8341-1-git-send-email-suriyan.r@gmail.com> References: <1413827523-8341-1-git-send-email-suriyan.r@gmail.com> Cc: marex@denx.de, jeroen@myspectrum.nl, Suriyan Ramasami , jh80.chung@samsung.com, p.marczak@samsung.com, jwerner@chromium.org Subject: [U-Boot] [PATCH v2 2/3] arm: odroid: enable/disable usb host phy for exynos4412 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami --- arch/arm/cpu/armv7/exynos/power.c | 26 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 7 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index e1ab3d6..6578a07 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -53,10 +53,36 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable) } } +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + void set_usbhost_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); + else if (proid_is_exynos4412()) + exynos4412_set_usbhost_phy_ctrl(enable); } static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index e8a98a5..3f97b31 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -210,6 +210,13 @@ struct exynos4_power { unsigned int gps_alive_option; }; +struct exynos4412_power { + unsigned char res1[0x0704]; + unsigned int usbhost_phy_control; + unsigned int hsic1_phy_control; + unsigned int hsic2_phy_control; +}; + struct exynos5_power { unsigned int om_stat; unsigned char res1[0x18];