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[U-Boot,v3,06/10] ARM: sunxi-mmc: Add mmc support for sun6i / A31

Message ID 1412338590-26538-7-git-send-email-wens@csie.org
State Accepted
Delegated to: Ian Campbell
Headers show

Commit Message

Chen-Yu Tsai Oct. 3, 2014, 12:16 p.m. UTC 
From: Hans de Goede <hdegoede@redhat.com>

The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
 drivers/mmc/sunxi_mmc.c               | 11 +++++++----
 2 files changed, 11 insertions(+), 5 deletions(-)
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Patch

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3..6a31184 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,10 @@  struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-	u32 fifo;		/* 0x100 FIFO access address */
+#if defined(CONFIG_SUN6I)
+	u32 res2[64];
+#endif
+	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index bc2c4b3..8f4b50b 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -19,7 +19,6 @@ 
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;
-	unsigned database;
 	unsigned fatal_err;
 	unsigned mod_clk;
 	struct sunxi_mmc *reg;
@@ -57,7 +56,6 @@  static int mmc_resource_init(int sdc_no)
 		printf("Wrong mmc number %d\n", sdc_no);
 		return -1;
 	}
-	mmchost->database = (unsigned int)mmchost->reg + 0x100;
 	mmchost->mmc_no = sdc_no;
 
 	return 0;
@@ -75,6 +73,11 @@  static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
+#if defined(CONFIG_SUN6I)
+	/* unassert reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
 	/* config mod clock */
 	pll_clk = clock_get_pll6();
 	/* should be close to 100 MHz but no more, so round up */
@@ -194,9 +197,9 @@  static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 		}
 
 		if (reading)
-			buff[i] = readl(mmchost->database);
+			buff[i] = readl(&mmchost->reg->fifo);
 		else
-			writel(buff[i], mmchost->database);
+			writel(buff[i], &mmchost->reg->fifo);
 	}
 
 	return 0;